diff options
Diffstat (limited to 'firmware/export/imx31l.h')
| -rwxr-xr-x | firmware/export/imx31l.h | 103 |
1 files changed, 70 insertions, 33 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 637b89b0ab..7dc2659b33 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
| @@ -516,32 +516,41 @@ | |||
| 516 | #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) | 516 | #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) |
| 517 | 517 | ||
| 518 | /* CSPI */ | 518 | /* CSPI */ |
| 519 | #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00)) | 519 | #define CSPI_RXDATA_I 0x00 /* Offset - 0x00 */ |
| 520 | #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04)) | 520 | #define CSPI_TXDATA_I 0x01 /* Offset - 0x04 */ |
| 521 | #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08)) | 521 | #define CSPI_CONREG_I 0x02 /* Offset - 0x08 */ |
| 522 | #define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C)) | 522 | #define CSPI_INTREG_I 0x03 /* Offset - 0x0C */ |
| 523 | #define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10)) | 523 | #define CSPI_DMAREG_I 0x04 /* Offset - 0x10 */ |
| 524 | #define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14)) | 524 | #define CSPI_STATREG_I 0x05 /* Offset - 0x14 */ |
| 525 | #define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18)) | 525 | #define CSPI_PERIODREG_I 0x06 /* Offset - 0x18 */ |
| 526 | #define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0)) | 526 | #define CSPI_TESTREG_I 0x70 /* Offset - 0x1C0 */ |
| 527 | 527 | ||
| 528 | #define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00)) | 528 | #define CSPI_RXDATA1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_RXDATA_I]) |
| 529 | #define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04)) | 529 | #define CSPI_TXDATA1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TXDATA_I]) |
| 530 | #define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08)) | 530 | #define CSPI_CONREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_CONREG_I]) |
| 531 | #define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C)) | 531 | #define CSPI_INTREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_INTREG_I]) |
| 532 | #define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10)) | 532 | #define CSPI_DMAREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_DMAREG_I]) |
| 533 | #define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14)) | 533 | #define CSPI_STATREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_STATREG_I]) |
| 534 | #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18)) | 534 | #define CSPI_PERIODREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_PERIODREG_I]) |
| 535 | #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0)) | 535 | #define CSPI_TESTREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TESTREG_I]) |
| 536 | 536 | ||
| 537 | #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00)) | 537 | #define CSPI_RXDATA2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_RXDATA_I]) |
| 538 | #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04)) | 538 | #define CSPI_TXDATA2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TXDATA_I]) |
| 539 | #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08)) | 539 | #define CSPI_CONREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_CONREG_I]) |
| 540 | #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C)) | 540 | #define CSPI_INTREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_INTREG_I]) |
| 541 | #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10)) | 541 | #define CSPI_DMAREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_DMAREG_I]) |
| 542 | #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14)) | 542 | #define CSPI_STATREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_STATREG_I]) |
| 543 | #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18)) | 543 | #define CSPI_PERIODREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_PERIODREG_I]) |
| 544 | #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0)) | 544 | #define CSPI_TESTREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TESTREG_I]) |
| 545 | |||
| 546 | #define CSPI_RXDATA3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_RXDATA_I]) | ||
| 547 | #define CSPI_TXDATA3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TXDATA_I]) | ||
| 548 | #define CSPI_CONREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_CONREG_I]) | ||
| 549 | #define CSPI_INTREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_INTREG_I]) | ||
| 550 | #define CSPI_DMAREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_DMAREG_I]) | ||
| 551 | #define CSPI_STATREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_STATREG_I]) | ||
| 552 | #define CSPI_PERIODREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_PERIODREG_I]) | ||
| 553 | #define CSPI_TESTREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TESTREG_I]) | ||
| 545 | 554 | ||
| 546 | /* CSPI CONREG flags/fields */ | 555 | /* CSPI CONREG flags/fields */ |
| 547 | #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24) | 556 | #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24) |
| @@ -563,6 +572,7 @@ | |||
| 563 | #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16) | 572 | #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16) |
| 564 | #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16) | 573 | #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16) |
| 565 | #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16) | 574 | #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16) |
| 575 | #define CSPI_BITCOUNT(n) ((n) << 8) | ||
| 566 | #define CSPI_CONREG_SSPOL (1 << 7) | 576 | #define CSPI_CONREG_SSPOL (1 << 7) |
| 567 | #define CSPI_CONREG_SSCTL (1 << 6) | 577 | #define CSPI_CONREG_SSCTL (1 << 6) |
| 568 | #define CSPI_CONREG_PHA (1 << 6) | 578 | #define CSPI_CONREG_PHA (1 << 6) |
| @@ -581,7 +591,7 @@ | |||
| 581 | #define CSPI_INTREG_RREN (1 << 3) | 591 | #define CSPI_INTREG_RREN (1 << 3) |
| 582 | #define CSPI_INTREG_TFEN (1 << 2) | 592 | #define CSPI_INTREG_TFEN (1 << 2) |
| 583 | #define CSPI_INTREG_THEN (1 << 1) | 593 | #define CSPI_INTREG_THEN (1 << 1) |
| 584 | #define CSPI_INTREF_TEEN (1 << 0) | 594 | #define CSPI_INTREG_TEEN (1 << 0) |
| 585 | 595 | ||
| 586 | /* CSPI DMAREG flags */ | 596 | /* CSPI DMAREG flags */ |
| 587 | #define CSPI_DMAREG_RFDEN (1 << 5) | 597 | #define CSPI_DMAREG_RFDEN (1 << 5) |
| @@ -764,12 +774,6 @@ | |||
| 764 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) | 774 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) |
| 765 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) | 775 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) |
| 766 | 776 | ||
| 767 | #define CG_OFF 0x0 /* Always off */ | ||
| 768 | #define CG_ON_RUN 0x1 /* On in run mode, off in wait and doze */ | ||
| 769 | #define CG_ON_RUN_WAIT 0x2 /* On in run and wait modes, off in doze */ | ||
| 770 | #define CG_ON_ALL 0x3 /* Always on */ | ||
| 771 | #define CG_MASK 0x3 /* bitmask */ | ||
| 772 | |||
| 773 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) | 777 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) |
| 774 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) | 778 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) |
| 775 | #define CGR0_GPT(cg) ((cg) << 2*2) | 779 | #define CGR0_GPT(cg) ((cg) << 2*2) |
| @@ -812,6 +816,39 @@ | |||
| 812 | #define CGR2_RTIC(cg) ((cg) << 5*2) | 816 | #define CGR2_RTIC(cg) ((cg) << 5*2) |
| 813 | #define CGR2_FIR(cg) ((cg) << 6*2) | 817 | #define CGR2_FIR(cg) ((cg) << 6*2) |
| 814 | 818 | ||
| 819 | #define WIM_GPIO3 (1 << 0) | ||
| 820 | #define WIM_GPIO2 (1 << 1) | ||
| 821 | #define WIM_GPIO1 (1 << 2) | ||
| 822 | #define WIM_PCMCIA (1 << 3) | ||
| 823 | #define WIM_WDT (1 << 4) | ||
| 824 | #define WIM_USB_OTG (1 << 5) | ||
| 825 | #define WIM_IPI_INT_UH2 (1 << 6) | ||
| 826 | #define WIM_IPI_INT_UH1 (1 << 7) | ||
| 827 | #define WIM_IPI_INT_UART5_ANDED (1 << 8) | ||
| 828 | #define WIM_IPI_INT_UART4_ANDED (1 << 9) | ||
| 829 | #define WIM_IPI_INT_UART3_ANDED (1 << 10) | ||
| 830 | #define WIM_IPI_INT_UART2_ANDED (1 << 11) | ||
| 831 | #define WIM_IPI_INT_UART1_ANDED (1 << 12) | ||
| 832 | #define WIM_IPI_INT_SIM_DATA_IRQ (1 << 13) | ||
| 833 | #define WIM_IPI_INT_SDHC2 (1 << 14) | ||
| 834 | #define WIM_IPI_INT_SDHC1 (1 << 15) | ||
| 835 | #define WIM_IPI_INT_RTC (1 << 16) | ||
| 836 | #define WIM_IPI_INT_PWM (1 << 17) | ||
| 837 | #define WIM_IPI_INT_KPP (1 << 18) | ||
| 838 | #define WIM_IPI_INT_IIM (1 << 19) | ||
| 839 | #define WIM_IPI_INT_GPT (1 << 20) | ||
| 840 | #define WIM_IPI_INT_FIR (1 << 21) | ||
| 841 | #define WIM_IPI_INT_EPIT2 (1 << 22) | ||
| 842 | #define WIM_IPI_INT_EPIT1 (1 << 23) | ||
| 843 | #define WIM_IPI_INT_CSPI2 (1 << 24) | ||
| 844 | #define WIM_IPI_INT_CSPI1 (1 << 25) | ||
| 845 | #define WIM_IPI_INT_POWER_FAIL (1 << 26) | ||
| 846 | #define WIM_IPI_INT_CSPI3 (1 << 27) | ||
| 847 | #define WIM_RESERVED28 (1 << 28) | ||
| 848 | #define WIM_RESERVED29 (1 << 29) | ||
| 849 | #define WIM_RESERVED30 (1 << 30) | ||
| 850 | #define WIM_RESERVED31 (1 << 31) | ||
| 851 | |||
| 815 | /* WEIM - CS0 */ | 852 | /* WEIM - CS0 */ |
| 816 | #define CSCRU 0x00 | 853 | #define CSCRU 0x00 |
| 817 | #define CSCRL 0x04 | 854 | #define CSCRL 0x04 |