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Diffstat (limited to 'firmware/export/i2c-pp5020.h')
-rw-r--r--firmware/export/i2c-pp5020.h43
1 files changed, 6 insertions, 37 deletions
diff --git a/firmware/export/i2c-pp5020.h b/firmware/export/i2c-pp5020.h
index 8487c678cf..c0dc969e8b 100644
--- a/firmware/export/i2c-pp5020.h
+++ b/firmware/export/i2c-pp5020.h
@@ -18,48 +18,17 @@
18 ****************************************************************************/ 18 ****************************************************************************/
19 19
20/* 20/*
21 * Driver for ARM i2c driver 21 * PP5020 i2c driver
22 *
23 * 22 *
24 */ 23 */
25 24
26#ifndef _I2C_ARM_H 25#ifndef _I2C_PP5020_H
27#define _I2C_ARM_H 26#define _I2C_PP5020_H
28 27
29/* TODO: Implement: i2c-pp5020.h */ 28/* TODO: Fully implement i2c driver */
30 29
31void i2c_init(void); 30void i2c_init(void);
32int i2c_write(int device, unsigned char *buf, int count); 31int i2c_readbyte(unsigned int dev_addr, int addr);
33void i2c_close(void); 32int ipod_i2c_send(unsigned int addr, int data0, int data1);
34
35#define MAX_LOOP 0x100 /* TODO: select a better value */
36
37/* PLLCR control */
38#define QSPISEL (1 << 11) /* Selects QSPI or I2C interface */
39
40/* Offsets to I2C registers from base address */
41#define O_MADR 0x00 /* Slave Address */
42#define O_MFDR 0x04 /* Frequency divider */
43#define O_MBCR 0x08 /* Control register */
44#define O_MBSR 0x0c /* Status register */
45#define O_MBDR 0x10 /* Data register */
46
47/* MBSR - Status register */
48#define ICF (1 << 7) /* Transfer Complete */
49#define IAAS (1 << 6) /* Addressed As Alave */
50#define IBB (1 << 5) /* Bus Busy */
51#define IAL (1 << 4) /* Arbitration Lost */
52#define SRW (1 << 2) /* Slave R/W */
53#define IFF (1 << 1) /* I2C Interrupt */
54#define RXAK (1 << 0) /* No Ack bit */
55
56/* MBCR - Control register */
57#define IEN (1 << 7) /* I2C Enable */
58#define IIEN (1 << 6) /* Interrupt Enable */
59#define MSTA (1 << 5) /* Master/Slave select */
60#define MTX (1 << 4) /* Transmit/Receive */
61#define TXAK (1 << 3) /* Transfer ACK */
62#define RSTA (1 << 2) /* Restart.. */
63
64 33
65#endif 34#endif