diff options
Diffstat (limited to 'firmware/export/i2c-coldfire.h')
| -rw-r--r-- | firmware/export/i2c-coldfire.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/firmware/export/i2c-coldfire.h b/firmware/export/i2c-coldfire.h index e5b34ddea6..b0d21a8631 100644 --- a/firmware/export/i2c-coldfire.h +++ b/firmware/export/i2c-coldfire.h | |||
| @@ -44,31 +44,31 @@ void i2c_adjust_prescale(int multiplier); | |||
| 44 | #define MAX_LOOP 0x100 /* TODO: select a better value */ | 44 | #define MAX_LOOP 0x100 /* TODO: select a better value */ |
| 45 | 45 | ||
| 46 | /* PLLCR control */ | 46 | /* PLLCR control */ |
| 47 | #define QSPISEL (1 << 11) /* Selects QSPI or I2C interface */ | 47 | #define QSPISEL (1 << 11) /* Selects QSPI or I2C interface */ |
| 48 | 48 | ||
| 49 | /* Offsets to I2C registers from base address */ | 49 | /* Offsets to I2C registers from base address */ |
| 50 | #define O_MADR 0x00 /* Slave Address */ | 50 | #define O_MADR 0x00 /* Slave Address */ |
| 51 | #define O_MFDR 0x04 /* Frequency divider */ | 51 | #define O_MFDR 0x04 /* Frequency divider */ |
| 52 | #define O_MBCR 0x08 /* Control register */ | 52 | #define O_MBCR 0x08 /* Control register */ |
| 53 | #define O_MBSR 0x0c /* Status register */ | 53 | #define O_MBSR 0x0c /* Status register */ |
| 54 | #define O_MBDR 0x10 /* Data register */ | 54 | #define O_MBDR 0x10 /* Data register */ |
| 55 | 55 | ||
| 56 | /* MBSR - Status register */ | 56 | /* MBSR - Status register */ |
| 57 | #define ICF (1 << 7) /* Transfer Complete */ | 57 | #define ICF (1 << 7) /* Transfer Complete */ |
| 58 | #define IAAS (1 << 6) /* Addressed As Alave */ | 58 | #define IAAS (1 << 6) /* Addressed As Alave */ |
| 59 | #define IBB (1 << 5) /* Bus Busy */ | 59 | #define IBB (1 << 5) /* Bus Busy */ |
| 60 | #define IAL (1 << 4) /* Arbitration Lost */ | 60 | #define IAL (1 << 4) /* Arbitration Lost */ |
| 61 | #define SRW (1 << 2) /* Slave R/W */ | 61 | #define SRW (1 << 2) /* Slave R/W */ |
| 62 | #define IIF (1 << 1) /* I2C Interrupt */ | 62 | #define IIF (1 << 1) /* I2C Interrupt */ |
| 63 | #define RXAK (1 << 0) /* No Ack bit */ | 63 | #define RXAK (1 << 0) /* No Ack bit */ |
| 64 | 64 | ||
| 65 | /* MBCR - Control register */ | 65 | /* MBCR - Control register */ |
| 66 | #define IEN (1 << 7) /* I2C Enable */ | 66 | #define IEN (1 << 7) /* I2C Enable */ |
| 67 | #define IIEN (1 << 6) /* Interrupt Enable */ | 67 | #define IIEN (1 << 6) /* Interrupt Enable */ |
| 68 | #define MSTA (1 << 5) /* Master/Slave select */ | 68 | #define MSTA (1 << 5) /* Master/Slave select */ |
| 69 | #define MTX (1 << 4) /* Transmit/Receive */ | 69 | #define MTX (1 << 4) /* Transmit/Receive */ |
| 70 | #define TXAK (1 << 3) /* Transfer ACK */ | 70 | #define TXAK (1 << 3) /* Transfer ACK */ |
| 71 | #define RSTA (1 << 2) /* Restart.. */ | 71 | #define RSTA (1 << 2) /* Restart.. */ |
| 72 | 72 | ||
| 73 | 73 | ||
| 74 | #endif | 74 | #endif |