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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20/*
21 * Driver for MCF52xx's I2C interface
22 * 2005-02-17 hubble@mochine.com
23 *
24 */
25
26#ifndef _I2C_COLDFIRE_H
27#define _I2C_COLDFIRE_H
28
29void i2c_init(void);
30int i2c_write(int device, unsigned char *buf, int count);
31void i2c_close(void);
32
33
34#define MAX_LOOP 0x100 /* TODO: select a better value */
35
36/* PLLCR control */
37#define QSPISEL (1 << 11) /* Selects QSPI or I2C interface */
38
39/* Offsets to I2C registers from base address */
40#define O_MADR 0x00 /* Slave Address */
41#define O_MFDR 0x04 /* Frequency divider */
42#define O_MBCR 0x08 /* Control register */
43#define O_MBSR 0x0c /* Status register */
44#define O_MBDR 0x10 /* Data register */
45
46/* MBSR - Status register */
47#define ICF (1 << 7) /* Transfer Complete */
48#define IAAS (1 << 6) /* Addressed As Alave */
49#define IBB (1 << 5) /* Bus Busy */
50#define IAL (1 << 4) /* Arbitration Lost */
51#define SRW (1 << 2) /* Slave R/W */
52#define IFF (1 << 1) /* I2C Interrupt */
53#define RXAK (1 << 0) /* No Ack bit */
54
55/* MBCR - Control register */
56#define IEN (1 << 7) /* I2C Enable */
57#define IIEN (1 << 6) /* Interrupt Enable */
58#define MSTA (1 << 5) /* Master/Slave select */
59#define MTX (1 << 4) /* Transmit/Receive */
60#define TXAK (1 << 3) /* Transfer ACK */
61#define RSTA (1 << 2) /* Restart.. */
62
63
64#endif