diff options
Diffstat (limited to 'firmware/drivers')
-rw-r--r-- | firmware/drivers/wm8731l.c | 52 |
1 files changed, 50 insertions, 2 deletions
diff --git a/firmware/drivers/wm8731l.c b/firmware/drivers/wm8731l.c index 990ad0ebbc..52d8d1e404 100644 --- a/firmware/drivers/wm8731l.c +++ b/firmware/drivers/wm8731l.c | |||
@@ -89,6 +89,27 @@ static void codec_set_active(int active) | |||
89 | */ | 89 | */ |
90 | static void i2s_reset(void) | 90 | static void i2s_reset(void) |
91 | { | 91 | { |
92 | #if CONFIG_CPU == PP5020 | ||
93 | /* I2S soft reset */ | ||
94 | outl(inl(0x70002800) | 0x80000000, 0x70002800); | ||
95 | outl(inl(0x70002800) & ~0x80000000, 0x70002800); | ||
96 | |||
97 | /* BIT.FORMAT [11:10] = I2S (default) */ | ||
98 | outl(inl(0x70002800) & ~0xc00, 0x70002800); | ||
99 | /* BIT.SIZE [9:8] = 16bit (default) */ | ||
100 | outl(inl(0x70002800) & ~0x300, 0x70002800); | ||
101 | |||
102 | /* FIFO.FORMAT [6:4] = 32 bit LSB */ | ||
103 | /* since BIT.SIZ < FIFO.FORMAT low 16 bits will be 0 */ | ||
104 | outl(inl(0x70002800) | 0x30, 0x70002800); | ||
105 | |||
106 | /* RX_ATN_LVL=1 == when 12 slots full */ | ||
107 | /* TX_ATN_LVL=1 == when 12 slots empty */ | ||
108 | outl(inl(0x7000280c) | 0x33, 0x7000280c); | ||
109 | |||
110 | /* Rx.CLR = 1, TX.CLR = 1 */ | ||
111 | outl(inl(0x7000280c) | 0x1100, 0x7000280c); | ||
112 | #elif CONFIG_CPU == PP5002 | ||
92 | /* I2S device reset */ | 113 | /* I2S device reset */ |
93 | outl(inl(0xcf005030) | 0x80, 0xcf005030); | 114 | outl(inl(0xcf005030) | 0x80, 0xcf005030); |
94 | outl(inl(0xcf005030) & ~0x80, 0xcf005030); | 115 | outl(inl(0xcf005030) & ~0x80, 0xcf005030); |
@@ -102,6 +123,7 @@ static void i2s_reset(void) | |||
102 | 123 | ||
103 | /* reset DAC and ADC fifo */ | 124 | /* reset DAC and ADC fifo */ |
104 | outl(inl(0xc000251c) | 0x30000, 0xc000251c); | 125 | outl(inl(0xc000251c) | 0x30000, 0xc000251c); |
126 | #endif | ||
105 | } | 127 | } |
106 | 128 | ||
107 | /* | 129 | /* |
@@ -112,6 +134,27 @@ int wmcodec_init(void) { | |||
112 | /* reset I2C */ | 134 | /* reset I2C */ |
113 | i2c_init(); | 135 | i2c_init(); |
114 | 136 | ||
137 | #if CONFIG_CPU == PP5020 | ||
138 | /* normal outputs for CDI and I2S pin groups */ | ||
139 | outl(inl(0x70000020) & ~0x300, 0x70000020); | ||
140 | |||
141 | /*mini2?*/ | ||
142 | outl(inl(0x70000010) & ~0x3000000, 0x70000010); | ||
143 | /*mini2?*/ | ||
144 | |||
145 | /* device reset */ | ||
146 | outl(inl(0x60006004) | 0x800, 0x60006004); | ||
147 | outl(inl(0x60006004) & ~0x800, 0x60006004); | ||
148 | |||
149 | /* device enable */ | ||
150 | outl(inl(0x6000600C) | 0x807, 0x6000600C); | ||
151 | |||
152 | /* enable external dev clock clocks */ | ||
153 | outl(inl(0x6000600c) | 0x2, 0x6000600c); | ||
154 | |||
155 | /* external dev clock to 24MHz */ | ||
156 | outl(inl(0x70000018) & ~0xc, 0x70000018); | ||
157 | #else | ||
115 | /* device reset */ | 158 | /* device reset */ |
116 | outl(inl(0xcf005030) | 0x80, 0xcf005030); | 159 | outl(inl(0xcf005030) | 0x80, 0xcf005030); |
117 | outl(inl(0xcf005030) & ~0x80, 0xcf005030); | 160 | outl(inl(0xcf005030) & ~0x80, 0xcf005030); |
@@ -135,6 +178,7 @@ int wmcodec_init(void) { | |||
135 | outl(inl(0xcf000008) | 0x8, 0xcf000008); | 178 | outl(inl(0xcf000008) | 0x8, 0xcf000008); |
136 | outl(inl(0xcf000018) | 0x8, 0xcf000018); | 179 | outl(inl(0xcf000018) | 0x8, 0xcf000018); |
137 | outl(inl(0xcf000028) & ~0x8, 0xcf000028); | 180 | outl(inl(0xcf000028) & ~0x8, 0xcf000028); |
181 | #endif | ||
138 | 182 | ||
139 | return 0; | 183 | return 0; |
140 | } | 184 | } |
@@ -142,7 +186,7 @@ int wmcodec_init(void) { | |||
142 | /* Silently enable / disable audio output */ | 186 | /* Silently enable / disable audio output */ |
143 | void wmcodec_enable_output(bool enable) | 187 | void wmcodec_enable_output(bool enable) |
144 | { | 188 | { |
145 | if (enable) | 189 | if (enable) |
146 | { | 190 | { |
147 | /* reset the I2S controller into known state */ | 191 | /* reset the I2S controller into known state */ |
148 | i2s_reset(); | 192 | i2s_reset(); |
@@ -151,9 +195,13 @@ void wmcodec_enable_output(bool enable) | |||
151 | 195 | ||
152 | codec_set_active(0x0); | 196 | codec_set_active(0x0); |
153 | 197 | ||
198 | #ifdef HAVE_WM8721 | ||
154 | /* DACSEL=1 */ | 199 | /* DACSEL=1 */ |
155 | /* BYPASS=1 */ | 200 | wm8731_write(0x4, 0x10); |
201 | #elif defined HAVE_WM8731 | ||
202 | /* DACSEL=1, BYPASS=1 */ | ||
156 | wm8731_write(0x4, 0x18); | 203 | wm8731_write(0x4, 0x18); |
204 | #endif | ||
157 | 205 | ||
158 | /* set power register to POWEROFF=0 on OUTPD=0, DACPD=0 */ | 206 | /* set power register to POWEROFF=0 on OUTPD=0, DACPD=0 */ |
159 | wm8731_write(PWRMGMT, 0x67); | 207 | wm8731_write(PWRMGMT, 0x67); |