diff options
Diffstat (limited to 'firmware/drivers/uda1380.c')
-rw-r--r-- | firmware/drivers/uda1380.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c index d6dfe6623b..82bf6d1ae1 100644 --- a/firmware/drivers/uda1380.c +++ b/firmware/drivers/uda1380.c | |||
@@ -272,7 +272,7 @@ void uda1380_enable_recording(bool source_mic) | |||
272 | { | 272 | { |
273 | /* VGA_GAIN: 0=0 dB, F=30dB */ | 273 | /* VGA_GAIN: 0=0 dB, F=30dB */ |
274 | /* Output of left ADC is fed into right bitstream */ | 274 | /* Output of left ADC is fed into right bitstream */ |
275 | uda1380_regs[REG_PWR] &= ~(PON_PLL | PON_PGAR | PON_ADCR); | 275 | uda1380_regs[REG_PWR] &= ~(PON_PGAR | PON_ADCR); |
276 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL); | 276 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL); |
277 | uda1380_regs[REG_ADC] &= ~SKIP_DCFIL; | 277 | uda1380_regs[REG_ADC] &= ~SKIP_DCFIL; |
278 | uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK) | 278 | uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK) |
@@ -282,7 +282,7 @@ void uda1380_enable_recording(bool source_mic) | |||
282 | else | 282 | else |
283 | { | 283 | { |
284 | /* PGA_GAIN: 0=0 dB, F=24dB */ | 284 | /* PGA_GAIN: 0=0 dB, F=24dB */ |
285 | uda1380_regs[REG_PWR] &= ~(PON_PLL | PON_LNA); | 285 | uda1380_regs[REG_PWR] &= ~PON_LNA; |
286 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL | 286 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL |
287 | | PON_PGAR | PON_ADCR); | 287 | | PON_PGAR | PON_ADCR); |
288 | uda1380_write_reg(REG_ADC, EN_DCFIL); | 288 | uda1380_write_reg(REG_ADC, EN_DCFIL); |
@@ -305,8 +305,9 @@ void uda1380_disable_recording(void) | |||
305 | 305 | ||
306 | uda1380_write_reg(REG_I2S, I2S_IFMT_IIS); | 306 | uda1380_write_reg(REG_I2S, I2S_IFMT_IIS); |
307 | 307 | ||
308 | uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR | PON_PGAL | PON_PGAR); | 308 | uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR | |
309 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PLL); | 309 | PON_PGAL | PON_PGAR); |
310 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]); | ||
310 | 311 | ||
311 | uda1380_regs[REG_0] &= ~EN_ADC; | 312 | uda1380_regs[REG_0] &= ~EN_ADC; |
312 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); | 313 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); |