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Diffstat (limited to 'firmware/drivers/uda1380.c')
-rw-r--r--firmware/drivers/uda1380.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c
index 82bf6d1ae1..841e7fbd19 100644
--- a/firmware/drivers/uda1380.c
+++ b/firmware/drivers/uda1380.c
@@ -97,7 +97,7 @@ int uda1380_write_reg(unsigned char reg, unsigned short value)
97/** 97/**
98 * Sets left and right master volume (0(max) to 252(muted)) 98 * Sets left and right master volume (0(max) to 252(muted))
99 */ 99 */
100int uda1380_set_master_vol(int vol_l, int vol_r) 100int audiohw_set_master_vol(int vol_l, int vol_r)
101{ 101{
102 return uda1380_write_reg(REG_MASTER_VOL, 102 return uda1380_write_reg(REG_MASTER_VOL,
103 MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r)); 103 MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
@@ -106,7 +106,7 @@ int uda1380_set_master_vol(int vol_l, int vol_r)
106/** 106/**
107 * Sets mixer volume for both channels (0(max) to 228(muted)) 107 * Sets mixer volume for both channels (0(max) to 228(muted))
108 */ 108 */
109int uda1380_set_mixer_vol(int channel1, int channel2) 109int audiohw_set_mixer_vol(int channel1, int channel2)
110{ 110{
111 return uda1380_write_reg(REG_MIX_VOL, 111 return uda1380_write_reg(REG_MIX_VOL,
112 MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2)); 112 MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
@@ -115,7 +115,7 @@ int uda1380_set_mixer_vol(int channel1, int channel2)
115/** 115/**
116 * Sets the bass value (0-12) 116 * Sets the bass value (0-12)
117 */ 117 */
118void uda1380_set_bass(int value) 118void audiohw_set_bass(int value)
119{ 119{
120 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK) 120 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK)
121 | BASSL(value) | BASSR(value)); 121 | BASSL(value) | BASSR(value));
@@ -124,7 +124,7 @@ void uda1380_set_bass(int value)
124/** 124/**
125 * Sets the treble value (0-3) 125 * Sets the treble value (0-3)
126 */ 126 */
127void uda1380_set_treble(int value) 127void audiohw_set_treble(int value)
128{ 128{
129 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK) 129 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK)
130 | TREBLEL(value) | TREBLER(value)); 130 | TREBLEL(value) | TREBLER(value));
@@ -134,7 +134,7 @@ void uda1380_set_treble(int value)
134 * Mute (mute=1) or enable sound (mute=0) 134 * Mute (mute=1) or enable sound (mute=0)
135 * 135 *
136 */ 136 */
137int uda1380_mute(int mute) 137int audiohw_mute(int mute)
138{ 138{
139 unsigned int value = uda1380_regs[REG_MUTE]; 139 unsigned int value = uda1380_regs[REG_MUTE];
140 140
@@ -147,7 +147,7 @@ int uda1380_mute(int mute)
147} 147}
148 148
149/* Returns 0 if successful or -1 if some register failed */ 149/* Returns 0 if successful or -1 if some register failed */
150int uda1380_set_regs(void) 150int audiohw_set_regs(void)
151{ 151{
152 int i; 152 int i;
153 memset(uda1380_regs, 0, sizeof(uda1380_regs)); 153 memset(uda1380_regs, 0, sizeof(uda1380_regs));
@@ -166,7 +166,7 @@ int uda1380_set_regs(void)
166} 166}
167 167
168/* Silently enable / disable audio output */ 168/* Silently enable / disable audio output */
169void uda1380_enable_output(bool enable) 169void audiohw_enable_output(bool enable)
170{ 170{
171 if (enable) { 171 if (enable) {
172 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP); 172 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
@@ -176,7 +176,7 @@ void uda1380_enable_output(bool enable)
176 } 176 }
177} 177}
178 178
179void uda1380_reset(void) 179void audiohw_reset(void)
180{ 180{
181#ifdef IRIVER_H300_SERIES 181#ifdef IRIVER_H300_SERIES
182 int mask = set_irq_level(HIGHEST_IRQ_LEVEL); 182 int mask = set_irq_level(HIGHEST_IRQ_LEVEL);
@@ -203,7 +203,7 @@ void uda1380_reset(void)
203 * 44100: 2 = 25 to 50 MCLK SCLK, LRCK: Audio Clk / 4 (default) 203 * 44100: 2 = 25 to 50 MCLK SCLK, LRCK: Audio Clk / 4 (default)
204 * 88200: 3 = 50 to 100 MCLK SCLK, LRCK: Audio Clk / 2 <= TODO: Needs WSPLL 204 * 88200: 3 = 50 to 100 MCLK SCLK, LRCK: Audio Clk / 2 <= TODO: Needs WSPLL
205 */ 205 */
206void uda1380_set_frequency(unsigned fsel) 206void audiohw_set_frequency(unsigned fsel)
207{ 207{
208 static const unsigned short values_reg[4][2] = 208 static const unsigned short values_reg[4][2] =
209 { 209 {
@@ -231,21 +231,21 @@ void uda1380_set_frequency(unsigned fsel)
231} 231}
232 232
233/* Initialize UDA1380 codec with default register values (uda1380_defaults) */ 233/* Initialize UDA1380 codec with default register values (uda1380_defaults) */
234int uda1380_init(void) 234int audiohw_init(void)
235{ 235{
236 recgain_mic = 0; 236 recgain_mic = 0;
237 recgain_line = 0; 237 recgain_line = 0;
238 238
239 uda1380_reset(); 239 audiohw_reset();
240 240
241 if (uda1380_set_regs() == -1) 241 if (audiohw_set_regs() == -1)
242 return -1; 242 return -1;
243 243
244 return 0; 244 return 0;
245} 245}
246 246
247/* Nice shutdown of UDA1380 codec */ 247/* Nice shutdown of UDA1380 codec */
248void uda1380_close(void) 248void audiohw_close(void)
249{ 249{
250 /* First enable mute and sleep a while */ 250 /* First enable mute and sleep a while */
251 uda1380_write_reg(REG_MUTE, MUTE_MASTER); 251 uda1380_write_reg(REG_MUTE, MUTE_MASTER);
@@ -263,7 +263,7 @@ void uda1380_close(void)
263 * 263 *
264 * source_mic: true=record from microphone, false=record from line-in (or radio) 264 * source_mic: true=record from microphone, false=record from line-in (or radio)
265 */ 265 */
266void uda1380_enable_recording(bool source_mic) 266void audiohw_enable_recording(bool source_mic)
267{ 267{
268 uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK); 268 uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK);
269 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC); 269 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
@@ -298,7 +298,7 @@ void uda1380_enable_recording(bool source_mic)
298/** 298/**
299 * Stop sending samples on the I2S bus 299 * Stop sending samples on the I2S bus
300 */ 300 */
301void uda1380_disable_recording(void) 301void audiohw_disable_recording(void)
302{ 302{
303 uda1380_write_reg(REG_PGA, MUTE_ADC); 303 uda1380_write_reg(REG_PGA, MUTE_ADC);
304 sleep(HZ/8); 304 sleep(HZ/8);
@@ -327,7 +327,7 @@ void uda1380_disable_recording(void)
327 be a peak or a dip. The small glitch is caused by the time between 327 be a peak or a dip. The small glitch is caused by the time between
328 setting the two gains 328 setting the two gains
329 */ 329 */
330void uda1380_set_recvol(int left, int right, int type) 330void audiohw_set_recvol(int left, int right, int type)
331{ 331{
332 int left_ag, right_ag; 332 int left_ag, right_ag;
333 333
@@ -412,7 +412,7 @@ void uda1380_set_recvol(int left, int right, int type)
412 * Enable or disable recording monitor (so one can listen to the recording) 412 * Enable or disable recording monitor (so one can listen to the recording)
413 * 413 *
414 */ 414 */
415void uda1380_set_monitor(int enable) 415void audiohw_set_monitor(int enable)
416{ 416{
417 if (enable) /* enable channel 2 */ 417 if (enable) /* enable channel 2 */
418 uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2); 418 uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2);