diff options
Diffstat (limited to 'firmware/drivers/sh7034.h')
-rw-r--r-- | firmware/drivers/sh7034.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/firmware/drivers/sh7034.h b/firmware/drivers/sh7034.h index 6d6fb6d714..bd894120e7 100644 --- a/firmware/drivers/sh7034.h +++ b/firmware/drivers/sh7034.h | |||
@@ -95,20 +95,20 @@ | |||
95 | 95 | ||
96 | #define SAR0_ADDR 0x05FFFF40 | 96 | #define SAR0_ADDR 0x05FFFF40 |
97 | #define DAR0_ADDR 0x05FFFF44 | 97 | #define DAR0_ADDR 0x05FFFF44 |
98 | #define OR_ADDR 0x05FFFF48 | 98 | #define DMAOR_ADDR 0x05FFFF48 |
99 | #define DTCR0_ADDR 0x05FFFF4A | 99 | #define DTCR0_ADDR 0x05FFFF4A |
100 | #define CHCR0_ADDR 0x05FFFF4E | 100 | #define CHCR0_ADDR 0x05FFFF4E |
101 | #define SAR1_ADDR 0x05FFFF50 | 101 | #define SAR1_ADDR 0x05FFFF50 |
102 | #define DAR1_ADDR 0x05FFFF54 | 102 | #define DAR1_ADDR 0x05FFFF54 |
103 | #define DTCR1_ADDR 0x05FFFF5A | 103 | #define DTCR1_ADDR 0x05FFFF5A |
104 | #define CHCR1_ADDR 0x05FFFF5E | 104 | #define CHCR1_ADDR 0x05FFFF5E |
105 | #define SAR2_ADDR 0x05FFFF60 | 105 | #define SAR2_ADDR 0x05FFFF60 |
106 | #define DAR2_ADDR 0x05FFFF64 | 106 | #define DAR2_ADDR 0x05FFFF64 |
107 | #define DTCR2_ADDR 0x05FFFF6A | 107 | #define DTCR2_ADDR 0x05FFFF6A |
108 | #define CHCR2_ADDR 0x05FFFF6E | 108 | #define CHCR2_ADDR 0x05FFFF6E |
109 | #define SAR3_ADDR 0x05FFFF70 | 109 | #define SAR3_ADDR 0x05FFFF70 |
110 | #define DAR3_ADDR 0x05FFFF74 | 110 | #define DAR3_ADDR 0x05FFFF74 |
111 | #define DTCR3_ADDR 0x05FFFF7A | 111 | #define DTCR3_ADDR 0x05FFFF7A |
112 | #define CHCR3_ADDR 0x05FFFF7E | 112 | #define CHCR3_ADDR 0x05FFFF7E |
113 | 113 | ||
114 | #define IPRA_ADDR 0x05FFFF84 | 114 | #define IPRA_ADDR 0x05FFFF84 |
@@ -231,20 +231,20 @@ | |||
231 | 231 | ||
232 | #define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) | 232 | #define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) |
233 | #define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) | 233 | #define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) |
234 | #define DMAOR (*((volatile unsigned long*)DMAOR_ADDR)) | 234 | #define DMAOR (*((volatile unsigned short*)DMAOR_ADDR)) |
235 | #define DTCR0 (*((volatile unsigned long*)DTCR0_ADDR)) | 235 | #define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR)) |
236 | #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) | 236 | #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) |
237 | #define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) | 237 | #define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) |
238 | #define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) | 238 | #define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) |
239 | #define DTCR1 (*((volatile unsigned long*)DTCR1_ADDR)) | 239 | #define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR)) |
240 | #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) | 240 | #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) |
241 | #define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) | 241 | #define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) |
242 | #define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) | 242 | #define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) |
243 | #define DTCR2 (*((volatile unsigned long*)DTCR2_ADDR)) | 243 | #define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR)) |
244 | #define HCR2 (*((volatile unsigned short*)CHCR2_ADDR)) | 244 | #define HCR2 (*((volatile unsigned short*)CHCR2_ADDR)) |
245 | #define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) | 245 | #define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) |
246 | #define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) | 246 | #define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) |
247 | #define DTCR3 (*((volatile unsigned long*)DTCR3_ADDR)) | 247 | #define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR)) |
248 | #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) | 248 | #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) |
249 | 249 | ||
250 | #define IPRA (*((volatile unsigned short*)IPRA_ADDR)) | 250 | #define IPRA (*((volatile unsigned short*)IPRA_ADDR)) |