diff options
Diffstat (limited to 'firmware/drivers/audio')
-rw-r--r-- | firmware/drivers/audio/uda1380.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/firmware/drivers/audio/uda1380.c b/firmware/drivers/audio/uda1380.c index 11a0604a1b..0add100393 100644 --- a/firmware/drivers/audio/uda1380.c +++ b/firmware/drivers/audio/uda1380.c | |||
@@ -29,6 +29,17 @@ | |||
29 | 29 | ||
30 | #include "audiohw.h" | 30 | #include "audiohw.h" |
31 | 31 | ||
32 | /* The UDA1380 requires a clock signal at a multiple of the sample rate | ||
33 | (256Fs, 384Fs, 512Fs or 768Fs, where Fs = sample rate). | ||
34 | Some targets are able to supply this clock directly to the SYSCLK input. | ||
35 | The H100 and H300 coldfire targets are limited in the selection of | ||
36 | frequencies for this clock signal so they use a PLL inside the UDA1380 | ||
37 | (called the WSPLL) to regenerate it from the LRCK signal off the IIS bus. | ||
38 | */ | ||
39 | #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) | ||
40 | #define USE_WSPLL | ||
41 | #endif | ||
42 | |||
32 | const struct sound_settings_info audiohw_settings[] = { | 43 | const struct sound_settings_info audiohw_settings[] = { |
33 | [SOUND_VOLUME] = {"dB", 0, 1, -84, 0, -25}, | 44 | [SOUND_VOLUME] = {"dB", 0, 1, -84, 0, -25}, |
34 | [SOUND_BASS] = {"dB", 0, 2, 0, 24, 0}, | 45 | [SOUND_BASS] = {"dB", 0, 2, 0, 24, 0}, |
@@ -83,8 +94,11 @@ short recgain_line; | |||
83 | #define NUM_DEFAULT_REGS 13 | 94 | #define NUM_DEFAULT_REGS 13 |
84 | unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = | 95 | unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = |
85 | { | 96 | { |
86 | REG_0, EN_DAC | EN_INT | EN_DEC | ADC_CLK | DAC_CLK | | 97 | REG_0, EN_DAC | EN_INT | EN_DEC | |
87 | SYSCLK_256FS | WSPLL_25_50, | 98 | #ifdef USE_WSPLL |
99 | ADC_CLK | DAC_CLK | WSPLL_25_50 | | ||
100 | #endif | ||
101 | SYSCLK_256FS, | ||
88 | REG_I2S, I2S_IFMT_IIS, | 102 | REG_I2S, I2S_IFMT_IIS, |
89 | REG_PWR, PON_PLL | PON_BIAS, | 103 | REG_PWR, PON_PLL | PON_BIAS, |
90 | /* PON_HP & PON_DAC is enabled later */ | 104 | /* PON_HP & PON_DAC is enabled later */ |
@@ -295,7 +309,9 @@ void audiohw_close(void) | |||
295 | */ | 309 | */ |
296 | void audiohw_enable_recording(bool source_mic) | 310 | void audiohw_enable_recording(bool source_mic) |
297 | { | 311 | { |
312 | #ifdef USE_WSPLL | ||
298 | uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK); | 313 | uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK); |
314 | #endif | ||
299 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC); | 315 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC); |
300 | 316 | ||
301 | if (source_mic) | 317 | if (source_mic) |
@@ -340,7 +356,9 @@ void audiohw_disable_recording(void) | |||
340 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]); | 356 | uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]); |
341 | 357 | ||
342 | uda1380_regs[REG_0] &= ~EN_ADC; | 358 | uda1380_regs[REG_0] &= ~EN_ADC; |
359 | #ifdef USE_WSPLL | ||
343 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); | 360 | uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK); |
361 | #endif | ||
344 | 362 | ||
345 | uda1380_write_reg(REG_ADC, SKIP_DCFIL); | 363 | uda1380_write_reg(REG_ADC, SKIP_DCFIL); |
346 | } | 364 | } |