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path: root/firmware/drivers/ata_mmc.c
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Diffstat (limited to 'firmware/drivers/ata_mmc.c')
-rw-r--r--firmware/drivers/ata_mmc.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/firmware/drivers/ata_mmc.c b/firmware/drivers/ata_mmc.c
index 6876ce0ec9..2e5bd3d78f 100644
--- a/firmware/drivers/ata_mmc.c
+++ b/firmware/drivers/ata_mmc.c
@@ -173,21 +173,20 @@ static void mmc_tick(void);
173 173
174/* implementation */ 174/* implementation */
175 175
176void mmc_select_clock(int card_no) 176void mmc_enable_int_flash_clock(bool on)
177{ 177{
178 /* set clock gate for external card / reset for internal card if the 178 /* Internal flash clock is enabled by setting PA12 high with the new
179 * MMC clock polarity bit is 0, vice versa if it is 1 */ 179 * clock circuit, and by setting it low with the old clock circuit */
180 if ((card_no != 0) ^ new_mmc_circuit) 180 if (on ^ new_mmc_circuit)
181 or_b(0x10, &PADRH); /* set clock gate PA12 */
182 else
183 and_b(~0x10, &PADRH); /* clear clock gate PA12 */ 181 and_b(~0x10, &PADRH); /* clear clock gate PA12 */
182 else
183 or_b(0x10, &PADRH); /* set clock gate PA12 */
184} 184}
185 185
186static int select_card(int card_no) 186static int select_card(int card_no)
187{ 187{
188 mutex_lock(&mmc_mutex); 188 mutex_lock(&mmc_mutex);
189 led(true); 189 led(true);
190 mmc_select_clock(card_no);
191 last_disk_activity = current_tick; 190 last_disk_activity = current_tick;
192 191
193 if (!card_info[card_no].initialized) 192 if (!card_info[card_no].initialized)
@@ -1061,7 +1060,6 @@ bool mmc_touched(void)
1061 unsigned char response; 1060 unsigned char response;
1062 1061
1063 mutex_lock(&mmc_mutex); 1062 mutex_lock(&mmc_mutex);
1064 mmc_select_clock(1);
1065 setup_sci1(7); /* safe value */ 1063 setup_sci1(7); /* safe value */
1066 and_b(~0x02, &PADRH); /* assert CS */ 1064 and_b(~0x02, &PADRH); /* assert CS */
1067 send_cmd(CMD_SEND_OP_COND, 0, &response); 1065 send_cmd(CMD_SEND_OP_COND, 0, &response);
@@ -1144,6 +1142,7 @@ void ata_enable(bool on)
1144 { 1142 {
1145 PBCR1 |= 0x08A0; /* as SCK1, TxD1, RxD1 */ 1143 PBCR1 |= 0x08A0; /* as SCK1, TxD1, RxD1 */
1146 IPRE &= 0x0FFF; /* disable SCI1 interrupts for the CPU */ 1144 IPRE &= 0x0FFF; /* disable SCI1 interrupts for the CPU */
1145 mmc_enable_int_flash_clock(true); /* always enabled in SPI mode */
1147 } 1146 }
1148 and_b(~0x80, &PADRL); /* assert reset */ 1147 and_b(~0x80, &PADRL); /* assert reset */
1149 sleep(HZ/20); 1148 sleep(HZ/20);
@@ -1183,13 +1182,13 @@ int ata_init(void)
1183 } 1182 }
1184#endif 1183#endif
1185 1184
1185 new_mmc_circuit = ((read_hw_mask() & MMC_CLOCK_POLARITY) != 0);
1186 ata_enable(true); 1186 ata_enable(true);
1187 1187
1188 if ( !initialized ) 1188 if ( !initialized )
1189 { 1189 {
1190 if (!last_mmc_status) 1190 if (!last_mmc_status)
1191 mmc_status = MMC_UNTOUCHED; 1191 mmc_status = MMC_UNTOUCHED;
1192 new_mmc_circuit = ((read_hw_mask() & MMC_CLOCK_POLARITY) != 0);
1193#ifdef HAVE_HOTSWAP 1192#ifdef HAVE_HOTSWAP
1194 queue_init(&mmc_queue); 1193 queue_init(&mmc_queue);
1195 create_thread(mmc_thread, mmc_stack, 1194 create_thread(mmc_thread, mmc_stack,