diff options
Diffstat (limited to 'firmware/drivers/ata.c')
-rw-r--r-- | firmware/drivers/ata.c | 59 |
1 files changed, 43 insertions, 16 deletions
diff --git a/firmware/drivers/ata.c b/firmware/drivers/ata.c index 3f5458d2c5..a603c51648 100644 --- a/firmware/drivers/ata.c +++ b/firmware/drivers/ata.c | |||
@@ -30,6 +30,10 @@ | |||
30 | #include "string.h" | 30 | #include "string.h" |
31 | #include "hwcompat.h" | 31 | #include "hwcompat.h" |
32 | 32 | ||
33 | #ifdef TARGET_TREE | ||
34 | #include "ata-target.h" | ||
35 | #endif | ||
36 | |||
33 | #define SECTOR_SIZE (512) | 37 | #define SECTOR_SIZE (512) |
34 | 38 | ||
35 | #if (CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250) | 39 | #if (CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250) |
@@ -68,6 +72,11 @@ | |||
68 | #define READ_PATTERN3 0xaa00 | 72 | #define READ_PATTERN3 0xaa00 |
69 | #define READ_PATTERN4 0x5500 | 73 | #define READ_PATTERN4 0x5500 |
70 | 74 | ||
75 | #define READ_PATTERN1_MASK 0xff00 | ||
76 | #define READ_PATTERN2_MASK 0xff00 | ||
77 | #define READ_PATTERN3_MASK 0xff00 | ||
78 | #define READ_PATTERN4_MASK 0xff00 | ||
79 | |||
71 | #define SET_REG(reg,val) reg = ((val) << 8) | 80 | #define SET_REG(reg,val) reg = ((val) << 8) |
72 | #define SET_16BITREG(reg,val) reg = (val) | 81 | #define SET_16BITREG(reg,val) reg = (val) |
73 | 82 | ||
@@ -111,6 +120,11 @@ | |||
111 | #define READ_PATTERN3 0xaa | 120 | #define READ_PATTERN3 0xaa |
112 | #define READ_PATTERN4 0x55 | 121 | #define READ_PATTERN4 0x55 |
113 | 122 | ||
123 | #define READ_PATTERN1_MASK 0xff | ||
124 | #define READ_PATTERN2_MASK 0xff | ||
125 | #define READ_PATTERN3_MASK 0xff | ||
126 | #define READ_PATTERN4_MASK 0xff | ||
127 | |||
114 | #define SET_REG(reg,val) reg = (val) | 128 | #define SET_REG(reg,val) reg = (val) |
115 | #define SET_16BITREG(reg,val) reg = (val) | 129 | #define SET_16BITREG(reg,val) reg = (val) |
116 | 130 | ||
@@ -150,6 +164,11 @@ | |||
150 | #define READ_PATTERN3 0xaa | 164 | #define READ_PATTERN3 0xaa |
151 | #define READ_PATTERN4 0x55 | 165 | #define READ_PATTERN4 0x55 |
152 | 166 | ||
167 | #define READ_PATTERN1_MASK 0xff | ||
168 | #define READ_PATTERN2_MASK 0xff | ||
169 | #define READ_PATTERN3_MASK 0xff | ||
170 | #define READ_PATTERN4_MASK 0xff | ||
171 | |||
153 | #define SET_REG(reg,val) reg = (val) | 172 | #define SET_REG(reg,val) reg = (val) |
154 | #define SET_16BITREG(reg,val) reg = (val) | 173 | #define SET_16BITREG(reg,val) reg = (val) |
155 | 174 | ||
@@ -207,6 +226,10 @@ | |||
207 | #define READ_PATTERN3 0xaa | 226 | #define READ_PATTERN3 0xaa |
208 | #define READ_PATTERN4 0x55 | 227 | #define READ_PATTERN4 0x55 |
209 | 228 | ||
229 | #define READ_PATTERN1_MASK 0xff | ||
230 | #define READ_PATTERN2_MASK 0xff | ||
231 | #define READ_PATTERN3_MASK 0xff | ||
232 | #define READ_PATTERN4_MASK 0xff | ||
210 | 233 | ||
211 | static unsigned char ide_sector_data[SECTOR_SIZE] __attribute__ ((section(".idata"))); | 234 | static unsigned char ide_sector_data[SECTOR_SIZE] __attribute__ ((section(".idata"))); |
212 | static unsigned ide_reg_temp __attribute__ ((section(".idata"))); | 235 | static unsigned ide_reg_temp __attribute__ ((section(".idata"))); |
@@ -280,6 +303,11 @@ int ide_read_register(int reg) { | |||
280 | #define READ_PATTERN3 0xaa | 303 | #define READ_PATTERN3 0xaa |
281 | #define READ_PATTERN4 0x55 | 304 | #define READ_PATTERN4 0x55 |
282 | 305 | ||
306 | #define READ_PATTERN1_MASK 0xff | ||
307 | #define READ_PATTERN2_MASK 0xff | ||
308 | #define READ_PATTERN3_MASK 0xff | ||
309 | #define READ_PATTERN4_MASK 0xff | ||
310 | |||
283 | #define SET_REG(reg,val) reg = (val) | 311 | #define SET_REG(reg,val) reg = (val) |
284 | #define SET_16BITREG(reg,val) reg = (val) | 312 | #define SET_16BITREG(reg,val) reg = (val) |
285 | 313 | ||
@@ -986,13 +1014,12 @@ static int check_registers(void) | |||
986 | SET_REG(ATA_LCYL, WRITE_PATTERN3); | 1014 | SET_REG(ATA_LCYL, WRITE_PATTERN3); |
987 | SET_REG(ATA_HCYL, WRITE_PATTERN4); | 1015 | SET_REG(ATA_HCYL, WRITE_PATTERN4); |
988 | 1016 | ||
989 | if ((ATA_NSECTOR == READ_PATTERN1) && | 1017 | if (((ATA_NSECTOR & READ_PATTERN1_MASK) == READ_PATTERN1) && |
990 | (ATA_SECTOR == READ_PATTERN2) && | 1018 | ((ATA_SECTOR & READ_PATTERN2_MASK) == READ_PATTERN2) && |
991 | (ATA_LCYL == READ_PATTERN3) && | 1019 | ((ATA_LCYL & READ_PATTERN3_MASK) == READ_PATTERN3) && |
992 | (ATA_HCYL == READ_PATTERN4)) | 1020 | ((ATA_HCYL & READ_PATTERN4_MASK) == READ_PATTERN4)) |
993 | return 0; | 1021 | return 0; |
994 | } | 1022 | } |
995 | |||
996 | return -2; | 1023 | return -2; |
997 | #endif | 1024 | #endif |
998 | } | 1025 | } |
@@ -1143,7 +1170,9 @@ int ata_hard_reset(void) | |||
1143 | { | 1170 | { |
1144 | int ret; | 1171 | int ret; |
1145 | 1172 | ||
1146 | #if CONFIG_CPU == SH7034 | 1173 | #ifdef TARGET_TREE |
1174 | ata_reset(); | ||
1175 | #elif CONFIG_CPU == SH7034 | ||
1147 | /* state HRR0 */ | 1176 | /* state HRR0 */ |
1148 | and_b(~0x02, &PADRH); /* assert _RESET */ | 1177 | and_b(~0x02, &PADRH); /* assert _RESET */ |
1149 | sleep(1); /* > 25us */ | 1178 | sleep(1); /* > 25us */ |
@@ -1157,8 +1186,6 @@ int ata_hard_reset(void) | |||
1157 | 1186 | ||
1158 | or_l(0x00080000, &GPIO_OUT); | 1187 | or_l(0x00080000, &GPIO_OUT); |
1159 | sleep(1); /* > 25us */ | 1188 | sleep(1); /* > 25us */ |
1160 | #elif defined(IAUDIO_X5) | ||
1161 | /* X5 TODO */ | ||
1162 | #elif CONFIG_CPU == TCC730 | 1189 | #elif CONFIG_CPU == TCC730 |
1163 | 1190 | ||
1164 | P6 &= ~0x40; | 1191 | P6 &= ~0x40; |
@@ -1285,6 +1312,7 @@ static void io_address_detect(void) | |||
1285 | } | 1312 | } |
1286 | #endif | 1313 | #endif |
1287 | 1314 | ||
1315 | #ifndef TARGET_TREE | ||
1288 | void ata_enable(bool on) | 1316 | void ata_enable(bool on) |
1289 | { | 1317 | { |
1290 | #if CONFIG_CPU == SH7034 | 1318 | #if CONFIG_CPU == SH7034 |
@@ -1302,9 +1330,6 @@ void ata_enable(bool on) | |||
1302 | 1330 | ||
1303 | or_l(0x00040000, &GPIO_ENABLE); | 1331 | or_l(0x00040000, &GPIO_ENABLE); |
1304 | or_l(0x00040000, &GPIO_FUNCTION); | 1332 | or_l(0x00040000, &GPIO_FUNCTION); |
1305 | #elif defined(IAUDIO_X5) | ||
1306 | /* X5 TODO */ | ||
1307 | (void)on; | ||
1308 | #elif CONFIG_CPU == TCC730 | 1333 | #elif CONFIG_CPU == TCC730 |
1309 | 1334 | ||
1310 | #elif (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020) | 1335 | #elif (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020) |
@@ -1312,6 +1337,7 @@ void ata_enable(bool on) | |||
1312 | (void)on; | 1337 | (void)on; |
1313 | #endif | 1338 | #endif |
1314 | } | 1339 | } |
1340 | #endif | ||
1315 | 1341 | ||
1316 | static int identify(void) | 1342 | static int identify(void) |
1317 | { | 1343 | { |
@@ -1456,13 +1482,12 @@ static int init_and_check(bool hard_reset) | |||
1456 | int ata_init(void) | 1482 | int ata_init(void) |
1457 | { | 1483 | { |
1458 | int rc; | 1484 | int rc; |
1459 | #if CONFIG_CPU == TCC730 | 1485 | #ifdef TARGET_TREE |
1486 | bool coldstart = ata_is_coldstart(); | ||
1487 | #elif CONFIG_CPU == TCC730 | ||
1460 | bool coldstart = (P1 & 0x80) == 0; | 1488 | bool coldstart = (P1 & 0x80) == 0; |
1461 | #elif defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) | 1489 | #elif defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) |
1462 | bool coldstart = (GPIO_FUNCTION & 0x00080000) == 0; | 1490 | bool coldstart = (GPIO_FUNCTION & 0x00080000) == 0; |
1463 | #elif defined(IAUDIO_X5) | ||
1464 | /* X5 TODO */ | ||
1465 | bool coldstart = true; | ||
1466 | #elif (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020) | 1491 | #elif (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020) |
1467 | bool coldstart = false; | 1492 | bool coldstart = false; |
1468 | /* TODO: Implement coldstart variable */ | 1493 | /* TODO: Implement coldstart variable */ |
@@ -1477,7 +1502,9 @@ int ata_init(void) | |||
1477 | 1502 | ||
1478 | ata_led(false); | 1503 | ata_led(false); |
1479 | 1504 | ||
1480 | #if CONFIG_CPU == SH7034 | 1505 | #ifdef TARGET_TREE |
1506 | ata_device_init(); | ||
1507 | #elif CONFIG_CPU == SH7034 | ||
1481 | /* Port A setup */ | 1508 | /* Port A setup */ |
1482 | or_b(0x02, &PAIORH); /* output for ATA reset */ | 1509 | or_b(0x02, &PAIORH); /* output for ATA reset */ |
1483 | or_b(0x02, &PADRH); /* release ATA reset */ | 1510 | or_b(0x02, &PADRH); /* release ATA reset */ |