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Diffstat (limited to 'firmware/drivers/ata.c')
-rw-r--r--firmware/drivers/ata.c130
1 files changed, 1 insertions, 129 deletions
diff --git a/firmware/drivers/ata.c b/firmware/drivers/ata.c
index 4017d5f3f7..c882c22fe1 100644
--- a/firmware/drivers/ata.c
+++ b/firmware/drivers/ata.c
@@ -84,104 +84,6 @@
84#define SET_REG(reg,val) reg = (val) 84#define SET_REG(reg,val) reg = (val)
85#define SET_16BITREG(reg,val) reg = (val) 85#define SET_16BITREG(reg,val) reg = (val)
86 86
87#elif CONFIG_CPU == TCC730
88
89/* Plain C read & write loops */
90#define PREFER_C_READING
91#define PREFER_C_WRITING
92
93#define SWAP_WORDS
94
95#define ATA_DATA_IDX (0xD0)
96#define ATA_ERROR_IDX (0xD2)
97#define ATA_NSECTOR_IDX (0xD4)
98#define ATA_SECTOR_IDX (0xD6)
99#define ATA_LCYL_IDX (0xD8)
100#define ATA_HCYL_IDX (0xDA)
101#define ATA_SELECT_IDX (0xDC)
102#define ATA_COMMAND_IDX (0xDE)
103#define ATA_CONTROL_IDX (0xEC)
104
105#define ATA_FEATURE_IDX ATA_ERROR_IDX
106#define ATA_STATUS_IDX ATA_COMMAND_IDX
107#define ATA_ALT_STATUS_IDX ATA_CONTROL_IDX
108
109#define SET_REG(reg, value) (ide_write_register(reg ## _IDX, value))
110#define SET_16BITREG(reg, value) (ide_write_register(reg ## _IDX, value))
111#define GET_REG(reg) (ide_read_register(reg))
112
113#define ATA_DATA (GET_REG(ATA_DATA_IDX))
114#define ATA_ERROR (GET_REG(ATA_ERROR_IDX))
115#define ATA_NSECTOR (GET_REG(ATA_NSECTOR_IDX))
116#define ATA_SECTOR (GET_REG(ATA_SECTOR_IDX))
117#define ATA_LCYL (GET_REG(ATA_LCYL_IDX))
118#define ATA_HCYL (GET_REG(ATA_HCYL_IDX))
119#define ATA_SELECT (GET_REG(ATA_SELECT_IDX))
120#define ATA_COMMAND (GET_REG(ATA_COMMAND_IDX))
121
122#define ATA_CONTROL (GET_REG(ATA_CONTROL_IDX))
123
124#define STATUS_BSY 0x80
125#define STATUS_RDY 0x40
126#define STATUS_DF 0x20
127#define STATUS_DRQ 0x08
128#define STATUS_ERR 0x01
129
130#define ERROR_ABRT 0x04
131
132#define WRITE_PATTERN1 0xa5
133#define WRITE_PATTERN2 0x5a
134#define WRITE_PATTERN3 0xaa
135#define WRITE_PATTERN4 0x55
136
137#define READ_PATTERN1 0xa5
138#define READ_PATTERN2 0x5a
139#define READ_PATTERN3 0xaa
140#define READ_PATTERN4 0x55
141
142#define READ_PATTERN1_MASK 0xff
143#define READ_PATTERN2_MASK 0xff
144#define READ_PATTERN3_MASK 0xff
145#define READ_PATTERN4_MASK 0xff
146
147static unsigned char ide_sector_data[SECTOR_SIZE] __attribute__ ((section(".idata")));
148static unsigned ide_reg_temp __attribute__ ((section(".idata")));
149
150void ide_write_register(int reg, int value) {
151 /* Archos firmware code does (sometimes!) this:
152 set the RAM speed to 8 cycles.
153 MIUSCFG |= 0x7;
154 */
155
156 ide_reg_temp = value;
157
158 long extAddr = (long)reg << 16;
159 ddma_transfer(1, 1, &ide_reg_temp, extAddr, 2);
160
161 /* set the RAM speed to 6 cycles.
162 unsigned char miuscfg = MIUSCFG;
163 miuscfg = (miuscfg & ~7) | 5;
164 */
165}
166
167int ide_read_register(int reg) {
168 /* set the RAM speed to 6 cycles.
169 unsigned char miuscfg = MIUSCFG;
170 miuscfg = (miuscfg & ~7) | 5;
171 MIUSCFG = miuscfg; */
172
173 long extAddr = (long)reg << 16;
174 ddma_transfer(0, 1, &ide_reg_temp, extAddr, 2);
175
176 /* This is done like this in the archos firmware...
177 miuscfg = MIUSCFG;
178 miuscfg = (miuscfg & ~7) | 5;
179 MIUSCFG = miuscfg;
180 Though I'd expect MIUSCFG &= ~0x7; (1 cycle) */
181
182 return ide_reg_temp;
183}
184
185#endif 87#endif
186 88
187#ifndef NOINLINE_ATTR 89#ifndef NOINLINE_ATTR
@@ -349,16 +251,7 @@ static void copy_read_sectors(unsigned char* buf, int wordcount)
349 } while (++wbuf < wbufend); /* tail loop is faster */ 251 } while (++wbuf < wbufend); /* tail loop is faster */
350 } 252 }
351#else /* !PREFER_C_READING */ 253#else /* !PREFER_C_READING */
352#if CONFIG_CPU == TCC730 254#if defined(CPU_COLDFIRE)
353 int sectorcount = wordcount / 0x100;
354 do {
355 /* Slurp an entire sector with a single dma transfer */
356 ddma_transfer(0, 1, ide_sector_data, ATA_DATA_IDX << 16, SECTOR_SIZE);
357 memcpy(buf, ide_sector_data, SECTOR_SIZE);
358 buf += SECTOR_SIZE;
359 sectorcount--;
360 } while (sectorcount > 0);
361#elif defined(CPU_COLDFIRE)
362 unsigned char* bufend = buf + 2 * wordcount; 255 unsigned char* bufend = buf + 2 * wordcount;
363 /* coldfire asm reading, utilising line bursts */ 256 /* coldfire asm reading, utilising line bursts */
364 /* this assumes there is at least one full line to copy */ 257 /* this assumes there is at least one full line to copy */
@@ -1416,23 +1309,6 @@ int ata_hard_reset(void)
1416 /* state HRR1 */ 1309 /* state HRR1 */
1417 or_b(0x02, &PADRH); /* negate _RESET */ 1310 or_b(0x02, &PADRH); /* negate _RESET */
1418 sleep(1); /* > 2ms */ 1311 sleep(1); /* > 2ms */
1419#elif CONFIG_CPU == TCC730
1420
1421 P6 &= ~0x40;
1422 ddma_transfer(0, 1, ide_sector_data, 0xF00000, SECTOR_SIZE);
1423 P6 |= 0x40;
1424
1425 /*
1426 What can the following do?
1427 P1 |= 0x04;
1428 P10CON &= ~0x56;
1429 sleep(1);
1430
1431 P10CON |= 0x56;
1432 P10 &= ~0x56;
1433 P1 &= ~0x04;
1434 sleep(1);
1435 */
1436#endif 1312#endif
1437 1313
1438 /* state HRR2 */ 1314 /* state HRR2 */
@@ -1561,8 +1437,6 @@ void ata_enable(bool on)
1561 or_b(0x80, &PADRL); /* disable ATA */ 1437 or_b(0x80, &PADRL); /* disable ATA */
1562 1438
1563 or_b(0x80, &PAIORL); 1439 or_b(0x80, &PAIORL);
1564#elif CONFIG_CPU == TCC730
1565
1566#endif 1440#endif
1567} 1441}
1568#endif 1442#endif
@@ -1712,8 +1586,6 @@ int ata_init(void)
1712 int rc; 1586 int rc;
1713#ifdef TARGET_TREE 1587#ifdef TARGET_TREE
1714 bool coldstart = ata_is_coldstart(); 1588 bool coldstart = ata_is_coldstart();
1715#elif CONFIG_CPU == TCC730
1716 bool coldstart = (P1 & 0x80) == 0;
1717#else 1589#else
1718 bool coldstart = (PACR2 & 0x4000) != 0; 1590 bool coldstart = (PACR2 & 0x4000) != 0;
1719#endif 1591#endif