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-rw-r--r--firmware/crt0.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S
index ee8beb7f2f..887f7de1f9 100644
--- a/firmware/crt0.S
+++ b/firmware/crt0.S
@@ -190,8 +190,8 @@ irq_handler:
190 190
191 /* Set up the DRAM controller. The refresh is based on the 11.2896MHz 191 /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
192 clock (5.6448MHz bus frequency). We haven't yet started the PLL */ 192 clock (5.6448MHz bus frequency). We haven't yet started the PLL */
193 move.l #0x80010000,%d0 193 move.w #0x8001,%d0
194 move.l %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ 194 move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */
195 195
196 /* Note: we place the SDRAM on an 0x1000000 (16M) offset because 196 /* Note: we place the SDRAM on an 0x1000000 (16M) offset because
197 the 5249 BGA chip has a fault which disables the use of A24. The 197 the 5249 BGA chip has a fault which disables the use of A24. The