diff options
Diffstat (limited to 'firmware/crt0.S')
-rw-r--r-- | firmware/crt0.S | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 78dce1ad2e..9b33f56232 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -78,12 +78,39 @@ start: | |||
78 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 78 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
79 | move.l #0x80050000,%d0 | 79 | move.l #0x80050000,%d0 |
80 | move.l %d0,(0x100,%a0) /* DCR - Synchronous, 80 cycle refresh */ | 80 | move.l %d0,(0x100,%a0) /* DCR - Synchronous, 80 cycle refresh */ |
81 | move.l #0x3000a520,%d0 | 81 | |
82 | move.l %d0,(0x108,%a0) /* DACR0 - Base 0x30000000, Banks on 23 and up, | 82 | /* Note: we place the SDRAM on an 0x1000000 (16M) offset because |
83 | CAS latency 3, Refresh enable */ | 83 | the 5249 BGA chip has a fault which disables the use of A24. The |
84 | move.l #0x01fc0001,%d0 | 84 | suggested workaround by FreeScale is to offset the base address by |
85 | half the DRAM size and increase the mask to the double. | ||
86 | In our case this means that we set the base address 16M ahead and | ||
87 | use a 64M mask. | ||
88 | */ | ||
89 | move.l #0x31002520,%d0 | ||
90 | move.l %d0,(0x108,%a0) /* DACR0 - Base 0x31000000, Banks on 23 and up, | ||
91 | CAS latency 1, No refresh yet */ | ||
92 | move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */ | ||
85 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | 93 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ |
86 | 94 | ||
95 | /* Precharge */ | ||
96 | move.l #0x31002528,%d0 | ||
97 | move.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a | ||
98 | Precharge command */ | ||
99 | move.l #0xabcd1234,%d0 | ||
100 | move.l %d0,0x31000000 /* Issue precharge command */ | ||
101 | |||
102 | /* Refresh */ | ||
103 | move.l #0x3100a520,%d0 | ||
104 | move.l %d0,(0x108,%a0) /* Enable refresh */ | ||
105 | |||
106 | /* Mode Register init */ | ||
107 | move.l #0x3100a560,%d0 /* DACR0[IMRS] = 1, next access will set the | ||
108 | Mode Register */ | ||
109 | move.l %d0,(0x108,%a0) | ||
110 | |||
111 | move.l #0xabcd1234,%d0 | ||
112 | move.l %d0,0x31001000 /* A12=1 means CASL=1 */ | ||
113 | |||
87 | lea _iramcopy,%a2 | 114 | lea _iramcopy,%a2 |
88 | lea _iramstart,%a3 | 115 | lea _iramstart,%a3 |
89 | lea _iramend,%a4 | 116 | lea _iramend,%a4 |