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-rw-r--r--firmware/boot.lds104
1 files changed, 65 insertions, 39 deletions
diff --git a/firmware/boot.lds b/firmware/boot.lds
index c0f19bc430..fc876b1d20 100644
--- a/firmware/boot.lds
+++ b/firmware/boot.lds
@@ -80,7 +80,10 @@ INPUT(target/sh/crt0.o)
80#define FLASHORIG 0x001f0000 80#define FLASHORIG 0x001f0000
81#define FLASHSIZE 2M 81#define FLASHSIZE 2M
82#elif CONFIG_CPU == IMX31L 82#elif CONFIG_CPU == IMX31L
83#define DRAMORIG 0x80000000 83#define DRAMORIG (0x02000000-0x00100000)
84#undef DRAMSIZE
85#define DRAMSIZE (1 << 20) /* Limit 1 MB for bootloader */
86#define IRAM DRAM
84#define IRAMORIG 0x1FFFC000 87#define IRAMORIG 0x1FFFC000
85#define IRAMSIZE 16K 88#define IRAMSIZE 16K
86#define FLASHORIG 0x0000000 89#define FLASHORIG 0x0000000
@@ -115,7 +118,12 @@ MEMORY
115#endif 118#endif
116 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE 119 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
117} 120}
118#elif !defined(CPU_PP) && (CONFIG_CPU!=S3C2440) && (CONFIG_CPU!=IMX31L) 121#elif CONFIG_CPU == IMX31L
122MEMORY
123{
124 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
125}
126#elif !defined(CPU_PP) && (CONFIG_CPU!=S3C2440)
119MEMORY 127MEMORY
120{ 128{
121 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE 129 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
@@ -302,48 +310,66 @@ SECTIONS
302} 310}
303#elif (CONFIG_CPU==IMX31L) 311#elif (CONFIG_CPU==IMX31L)
304{ 312{
305#if 0 313 . = DRAMORIG;
314
315 .text :
316 {
317 *(.init.text)
318 *(.text*)
319 *(.icode)
320 *(.glue_7)
321 *(.glue_7t)
322 . = ALIGN(0x4);
323 } > DRAM
324
325 .rodata :
326 {
327 *(.rodata) /* problems without this, dunno why */
328 *(.rodata*)
329 *(.rodata.str1.1)
330 *(.rodata.str1.4)
331 . = ALIGN(0x4);
332
333 /* Pseudo-allocate the copies of the data sections */
334 _datacopy = .;
335 } > DRAM
336
337 .data :
338 {
339 *(.irodata)
340 *(.idata)
341 *(.data*)
342 . = ALIGN(0x4);
343 _dataend = . ;
344 } > DRAM
345
346 .stack :
347 {
348 *(.stack)
349 _stackbegin = .;
350 stackbegin = .;
351 . += 0x2000;
352 _stackend = .;
353 stackend = .;
354 } > IRAM
355
356 .bss :
357 {
358 _edata = .;
359 *(.bss*);
360 *(.ibss);
361 *(COMMON)
362 _end = .;
363 } > DRAM
364
306 .vectors 0x0 : 365 .vectors 0x0 :
307 { 366 {
308 _vectorsstart = .; 367 _vectorsstart = .;
309 *(.vectors); 368 *(.vectors);
369 KEEP(*(.vectors));
310 _vectorsend = .; 370 _vectorsend = .;
311 } AT> DRAM 371 } AT > DRAM
312#endif 372 _vectorscopy = LOADADDR(.vectors);
313 . = 0x82000000;
314
315 .text :
316 {
317 *(.init.text)
318 *(.text*)
319 }
320
321 .data :
322 {
323 *(.icode)
324 *(.irodata)
325 *(.idata)
326 *(.data*)
327 _dataend = . ;
328 }
329
330 .stack :
331 {
332 *(.stack)
333 _stackbegin = .;
334 stackbegin = .;
335 . += 0x2000;
336 _stackend = .;
337 stackend = .;
338 }
339
340 .bss :
341 {
342 _edata = .;
343 *(.bss*);
344 *(.ibss);
345 _end = .;
346 }
347} 373}
348#else 374#else
349{ 375{