diff options
Diffstat (limited to 'bootloader/rk27xx.c')
-rw-r--r-- | bootloader/rk27xx.c | 151 |
1 files changed, 145 insertions, 6 deletions
diff --git a/bootloader/rk27xx.c b/bootloader/rk27xx.c index 37778db6dc..d94b080345 100644 --- a/bootloader/rk27xx.c +++ b/bootloader/rk27xx.c | |||
@@ -15,9 +15,56 @@ | |||
15 | #include "common.h" | 15 | #include "common.h" |
16 | #include "version.h" | 16 | #include "version.h" |
17 | 17 | ||
18 | // 441 Hz samples table, 44100 Hz and 441 Hz -> 100 samples | ||
19 | const int16_t samples[] = { | ||
20 | 0, 2057, 4106, 6139, 8148, 10125, 12062, 13951, 15785, 17557, | ||
21 | 19259, 20886, 22430, 23886, 25247, 26509, 27666, 28713, 29648, 30465, | ||
22 | 31163, 31737, 32186, 32508, 32702, 32767, 32702, 32508, 32186, 31737, | ||
23 | 31163, 30465, 29648, 28713, 27666, 26509, 25247, 23886, 22430, 20886, | ||
24 | 19259, 17557, 15785, 13951, 12062, 10125, 8148, 6139, 4106, 2057, | ||
25 | 0, -2057, -4106, -6139, -8148, -10125, -12062, -13951, -15785, -17557, | ||
26 | -19259, -20886, -22430, -23886, -25247, -26509, -27666, -28713, -29648, -30465, | ||
27 | -31163, -31737, -32186, -32508, -32702, -32767, -32702, -32508, -32186, -31737, | ||
28 | -31163, -30465, -29648, -28713, -27666, -26509, -25247, -23886, -22430, -20886, | ||
29 | -19259, -17557, -15785, -13951, -12062, -10125, -8148, -6139, -4106, -2057 }; | ||
30 | |||
18 | extern int show_logo( void ); | 31 | extern int show_logo( void ); |
32 | |||
33 | void INT_HDMA(void) | ||
34 | { | ||
35 | #if 0 | ||
36 | // static uint32_t i; | ||
37 | // printf("hdma int: %d", i++); | ||
38 | |||
39 | HDMA_ISRC0 = (uint32_t)&samples; | ||
40 | HDMA_IDST0 = (uint32_t)&I2S_TXR; | ||
41 | HDMA_ICNT0 = (sizeof(samples)/4) - 1; | ||
42 | HDMA_CON0 = (1<<22)| // slice mode | ||
43 | (1<<21)| // channel enable | ||
44 | (1<<18)| // interrupt mode | ||
45 | (5<<13)| // transfer mode inc8 | ||
46 | (6<<9) | // hdreq from i2s tx | ||
47 | (0<<7) | // source address increment | ||
48 | (1<<5) | // destination address fixed | ||
49 | (2<<3) | // data size word | ||
50 | (1<<0); // enable hardware triggered dma | ||
51 | |||
52 | HDMA_ISR = (1<<13) | // mask ch1 page overflow | ||
53 | (1<<11) | // mask ch1 page count down | ||
54 | (1<<9); // mask ch1 interrupts | ||
55 | #endif | ||
56 | return; | ||
57 | } | ||
58 | |||
59 | static int codec_write(uint8_t reg, uint8_t data) | ||
60 | { | ||
61 | uint8_t tmp = data; | ||
62 | return i2c_write(0x27<<1, reg<<1, 1, &tmp); | ||
63 | } | ||
64 | |||
19 | void main(void) | 65 | void main(void) |
20 | { | 66 | { |
67 | int i; | ||
21 | 68 | ||
22 | _backlight_init(); | 69 | _backlight_init(); |
23 | 70 | ||
@@ -33,13 +80,105 @@ void main(void) | |||
33 | show_logo(); | 80 | show_logo(); |
34 | sleep(HZ*2); | 81 | sleep(HZ*2); |
35 | 82 | ||
83 | printf("show logo passed"); | ||
84 | // I2S init | ||
85 | SCU_CLKCFG &= ~((1<<17) | (1<<16)); // enable i2s, i2c pclk | ||
86 | //SCU_CLKCFG |= ((1<<17) | (1<<16)); | ||
87 | I2S_OPR = (1<<17) | // reset Tx | ||
88 | (1<<16) | // reset Rx | ||
89 | (1<<6) | // disable HDMA Req1 | ||
90 | (1<<5); // disable HDMA Req2 | ||
91 | |||
92 | I2S_TXCTL = (1<<16) | // LRCK/SCLK = 64 | ||
93 | (4<<8) | // MCLK/SCK = 4 | ||
94 | (1<<4) | // 16bit samples | ||
95 | (0<<3) | // stereo mode | ||
96 | (0<<1); // I2S | ||
97 | |||
98 | I2S_RXCTL = (1<<16) | // LRCK/SCLK = 64 | ||
99 | (4<<8) | // MCLK/SCK = 4 | ||
100 | (1<<4) | // 16bit samples | ||
101 | (0<<3) | // stereo mode | ||
102 | (0<<1); // I2S | ||
103 | |||
104 | I2S_FIFOSTS = (1<<18) | // Tx int trigger half full | ||
105 | (1<<16); // Rx int trigger half full | ||
106 | |||
107 | // I2S start | ||
108 | I2S_OPR = (1<<17) | (1<<16); | ||
109 | sleep(HZ/100); | ||
110 | |||
111 | I2S_OPR = (0<<6) | // req channel 1 enable | ||
112 | (1<<5) | // req channel 2 disable | ||
113 | (0<<4) | // HDMA req channel 1 Tx | ||
114 | (0<<2) | // normal I2S operation (no loopback) | ||
115 | (1<<1); // Tx start | ||
116 | |||
117 | printf("I2S config passed"); | ||
118 | |||
119 | HDMA_ISRC0 = (uint32_t)&samples; | ||
120 | HDMA_IDST0 = (uint32_t)&I2S_TXR; | ||
121 | HDMA_ICNT0 = (sizeof(samples)/4) - 1; | ||
122 | HDMA_ISCNT0 = 7; | ||
123 | HDMA_IPNCNTD0 = 1; | ||
124 | HDMA_CON0 = (1<<22)| // slice mode | ||
125 | (1<<21)| // channel enable | ||
126 | (1<<18)| // interrupt mode | ||
127 | (5<<13)| // transfer mode inc8 | ||
128 | (6<<9) | // hdreq from i2s tx | ||
129 | (0<<7) | // source address increment | ||
130 | (1<<5) | // destination address fixed | ||
131 | (2<<3) | // data size word | ||
132 | (1<<0); // enable hardware triggered dma | ||
133 | |||
134 | HDMA_ISR = (1<<13) | // mask ch1 page overflow | ||
135 | (1<<11) | // mask ch1 page count down | ||
136 | (1<<9); // mask ch1 interrupts | ||
137 | |||
138 | INTC_IMR |= (1<<12); | ||
139 | INTC_IECR |= (1<<12); | ||
140 | |||
141 | printf("HDMA config passed"); | ||
142 | |||
143 | i2c_init(); | ||
144 | |||
145 | printf("I2C config passed"); | ||
146 | |||
147 | // codec init | ||
148 | codec_write(0x00, (1<<3)|(1<<2)|(1<<1)|(1<<0)); // AICR | ||
149 | codec_write(0x01, (1<<7)|(1<<5)|(1<<3)); // CR1 | ||
150 | codec_write(0x02, (1<<2)); // CR2 | ||
151 | codec_write(0x03, 0); // CCR1 | ||
152 | codec_write(0x04, (2<<4)|(2<<0)); // CCR2 | ||
153 | codec_write(0x07, (3<<5)|(3<<0)); // CCR | ||
154 | |||
155 | |||
156 | codec_write(0x0f, 0x1f|(2<<6)); // CGR6 | ||
157 | codec_write(0x14, (1<<1)); // TR1 | ||
158 | codec_write(0x05, (1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); // PMR1 | ||
159 | sleep(HZ/100); | ||
160 | |||
161 | codec_write(0x06, (1<<3)|(1<<2)|(1<<0)); // PMR2 | ||
162 | |||
163 | |||
164 | codec_write(0x05, (1<<6)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); // PMR1 | ||
165 | codec_write(0x05, (1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); // PMR1 | ||
166 | |||
167 | |||
168 | // DACout mode | ||
169 | codec_write(0x01, (1<<7)|(1<<3)|(1<<5)|(1<<4)); // CR1 | ||
170 | codec_write(0x05, (1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); //PMR1 | ||
171 | // codec_write(0x06, (1<<3)|(1<<2)); // PMR2 | ||
172 | |||
173 | printf("codec init passed"); | ||
174 | |||
175 | codec_write(0x01, (1<<7)|(1<<3)); // CR1 | ||
176 | |||
177 | codec_write(0x0a, 0); // 0dB digital gain | ||
178 | codec_write(0x11, 15|(2<<6)); // | ||
179 | |||
36 | while(1) | 180 | while(1) |
37 | { | 181 | { |
38 | reset_screen(); | 182 | printf("HDMA_CCNT0: 0x%0x FIFOSTS: 0x%0x", HDMA_CCNT0, I2S_FIFOSTS); |
39 | printf("GPIOA: 0x%0x", GPIO_PADR); | ||
40 | printf("GPIOB: 0x%0x", GPIO_PBDR); | ||
41 | printf("GPIOC: 0x%0x", GPIO_PCDR); | ||
42 | printf("GPIOD: 0x%0x", GPIO_PDDR); | ||
43 | sleep(HZ/10); | ||
44 | } | 183 | } |
45 | } | 184 | } |