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Diffstat (limited to 'apps/plugins/mpegplayer/libmpeg2/motion_comp_arm_s.S')
-rw-r--r--apps/plugins/mpegplayer/libmpeg2/motion_comp_arm_s.S342
1 files changed, 0 insertions, 342 deletions
diff --git a/apps/plugins/mpegplayer/libmpeg2/motion_comp_arm_s.S b/apps/plugins/mpegplayer/libmpeg2/motion_comp_arm_s.S
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index 1ec1b0686e..0000000000
--- a/apps/plugins/mpegplayer/libmpeg2/motion_comp_arm_s.S
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@@ -1,342 +0,0 @@
1@ motion_comp_arm_s.S
2@ Copyright (C) 2004 AGAWA Koji <i (AT) atty (DOT) jp>
3@
4@ This file is part of mpeg2dec, a free MPEG-2 video stream decoder.
5@ See http://libmpeg2.sourceforge.net/ for updates.
6@
7@ mpeg2dec is free software; you can redistribute it and/or modify
8@ it under the terms of the GNU General Public License as published by
9@ the Free Software Foundation; either version 2 of the License, or
10@ (at your option) any later version.
11@
12@ mpeg2dec is distributed in the hope that it will be useful,
13@ but WITHOUT ANY WARRANTY; without even the implied warranty of
14@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15@ GNU General Public License for more details.
16@
17@ You should have received a copy of the GNU General Public License
18@ along with this program; if not, write to the Free Software
19@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20@
21@ $Id$
22
23#include "config.h" /* Rockbox: ARM architecture version */
24
25 .text
26
27@ ----------------------------------------------------------------
28 .align
29 .global MC_put_o_16
30MC_put_o_16:
31 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
32 @@ pld [r1]
33 stmfd sp!, {r4-r7, lr} @ R14 is also called LR
34 and r4, r1, #3
35 ldr pc, [pc, r4, lsl #2]
36 .word 0
37 .word MC_put_o_16_align0
38 .word MC_put_o_16_align1
39 .word MC_put_o_16_align2
40 .word MC_put_o_16_align3
41
42MC_put_o_16_align0:
43 ldmia r1, {r4-r7}
44 add r1, r1, r2
45 @@ pld [r1]
46 stmia r0, {r4-r7}
47 subs r3, r3, #1
48 add r0, r0, r2
49 bne MC_put_o_16_align0
50 ldmpc regs=r4-r7 @@ update PC with LR content.
51
52.macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
53 mov \R0, \R0, lsr #(\shift)
54 orr \R0, \R0, \R1, lsl #(32 - \shift)
55 mov \R1, \R1, lsr #(\shift)
56 orr \R1, \R1, \R2, lsl #(32 - \shift)
57 mov \R2, \R2, lsr #(\shift)
58 orr \R2, \R2, \R3, lsl #(32 - \shift)
59 mov \R3, \R3, lsr #(\shift)
60 orr \R3, \R3, \R4, lsl #(32 - \shift)
61 mov \R4, \R4, lsr #(\shift)
62.endm
63
64MC_put_o_16_align1:
65 and r1, r1, #0xFFFFFFFC
661: ldmia r1, {r4-r7, r12}
67 add r1, r1, r2
68 @@ pld [r1]
69 ADJ_ALIGN_QW 8, r4, r5, r6, r7, r12
70 stmia r0, {r4-r7}
71 subs r3, r3, #1
72 add r0, r0, r2
73 bne 1b
74 ldmpc regs=r4-r7 @@ update PC with LR content.
75
76MC_put_o_16_align2:
77 and r1, r1, #0xFFFFFFFC
781: ldmia r1, {r4-r7, r12}
79 add r1, r1, r2
80 @@ pld [r1]
81 ADJ_ALIGN_QW 16, r4, r5, r6, r7, r12
82 stmia r0, {r4-r7}
83 subs r3, r3, #1
84 add r0, r0, r2
85 bne 1b
86 ldmpc regs=r4-r7 @@ update PC with LR content.
87
88MC_put_o_16_align3:
89 and r1, r1, #0xFFFFFFFC
901: ldmia r1, {r4-r7, r12}
91 add r1, r1, r2
92 @@ pld [r1]
93 ADJ_ALIGN_QW 24, r4, r5, r6, r7, r12
94 stmia r0, {r4-r7}
95 subs r3, r3, #1
96 add r0, r0, r2
97 bne 1b
98 ldmpc regs=r4-r7 @@ update PC with LR content.
99
100@ ----------------------------------------------------------------
101 .align
102 .global MC_put_o_8
103MC_put_o_8:
104 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
105 @@ pld [r1]
106 stmfd sp!, {r4, r5, lr} @ R14 is also called LR
107 and r4, r1, #3
108 ldr pc, [pc, r4, lsl #2]
109 .word 0
110 .word MC_put_o_8_align0
111 .word MC_put_o_8_align1
112 .word MC_put_o_8_align2
113 .word MC_put_o_8_align3
114
115MC_put_o_8_align0:
116 ldmia r1, {r4, r5}
117 add r1, r1, r2
118 @@ pld [r1]
119 stmia r0, {r4, r5}
120 add r0, r0, r2
121 subs r3, r3, #1
122 bne MC_put_o_8_align0
123 ldmpc regs=r4-r5 @@ update PC with LR content.
124
125.macro ADJ_ALIGN_DW shift, R0, R1, R2
126 mov \R0, \R0, lsr #(\shift)
127 orr \R0, \R0, \R1, lsl #(32 - \shift)
128 mov \R1, \R1, lsr #(\shift)
129 orr \R1, \R1, \R2, lsl #(32 - \shift)
130 mov \R2, \R2, lsr #(\shift)
131.endm
132
133MC_put_o_8_align1:
134 and r1, r1, #0xFFFFFFFC
1351: ldmia r1, {r4, r5, r12}
136 add r1, r1, r2
137 @@ pld [r1]
138 ADJ_ALIGN_DW 8, r4, r5, r12
139 stmia r0, {r4, r5}
140 subs r3, r3, #1
141 add r0, r0, r2
142 bne 1b
143 ldmpc regs=r4-r5 @@ update PC with LR content.
144
145MC_put_o_8_align2:
146 and r1, r1, #0xFFFFFFFC
1471: ldmia r1, {r4, r5, r12}
148 add r1, r1, r2
149 @@ pld [r1]
150 ADJ_ALIGN_DW 16, r4, r5, r12
151 stmia r0, {r4, r5}
152 subs r3, r3, #1
153 add r0, r0, r2
154 bne 1b
155 ldmpc regs=r4-r5 @@ update PC with LR content.
156
157MC_put_o_8_align3:
158 and r1, r1, #0xFFFFFFFC
1591: ldmia r1, {r4, r5, r12}
160 add r1, r1, r2
161 @@ pld [r1]
162 ADJ_ALIGN_DW 24, r4, r5, r12
163 stmia r0, {r4, r5}
164 subs r3, r3, #1
165 add r0, r0, r2
166 bne 1b
167 ldmpc regs=r4-r5 @@ update PC with LR content.
168
169@ ----------------------------------------------------------------
170.macro AVG_PW rW1, rW2
171 mov \rW2, \rW2, lsl #24
172 orr \rW2, \rW2, \rW1, lsr #8
173 eor r9, \rW1, \rW2
174#if ARM_ARCH >= 6
175 uhadd8 \rW2, \rW1, \rW2
176#else
177 and \rW2, \rW1, \rW2
178 and r10, r9, r11
179 add \rW2, \rW2, r10, lsr #1
180#endif
181 and r9, r9, r12
182 add \rW2, \rW2, r9
183.endm
184
185#if ARM_ARCH >= 6
186#define HIGHEST_REG r9
187#else
188#define HIGHEST_REG r11
189#endif
190
191 .align
192 .global MC_put_x_16
193MC_put_x_16:
194 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
195 @@ pld [r1]
196 stmfd sp!, {r4-HIGHEST_REG, lr} @ R14 is also called LR
197 and r4, r1, #3
198 ldr r12, 2f
199#if ARM_ARCH < 6
200 mvn r11, r12
201#endif
202 ldr pc, [pc, r4, lsl #2]
2032: .word 0x01010101
204 .word MC_put_x_16_align0
205 .word MC_put_x_16_align1
206 .word MC_put_x_16_align2
207 .word MC_put_x_16_align3
208
209MC_put_x_16_align0:
210 ldmia r1, {r4-r8}
211 add r1, r1, r2
212 @@ pld [r1]
213 AVG_PW r7, r8
214 AVG_PW r6, r7
215 AVG_PW r5, r6
216 AVG_PW r4, r5
217 stmia r0, {r5-r8}
218 subs r3, r3, #1
219 add r0, r0, r2
220 bne MC_put_x_16_align0
221 ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
222
223MC_put_x_16_align1:
224 and r1, r1, #0xFFFFFFFC
2251: ldmia r1, {r4-r8}
226 add r1, r1, r2
227 @@ pld [r1]
228 ADJ_ALIGN_QW 8, r4, r5, r6, r7, r8
229 AVG_PW r7, r8
230 AVG_PW r6, r7
231 AVG_PW r5, r6
232 AVG_PW r4, r5
233 stmia r0, {r5-r8}
234 subs r3, r3, #1
235 add r0, r0, r2
236 bne 1b
237 ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
238
239MC_put_x_16_align2:
240 and r1, r1, #0xFFFFFFFC
2411: ldmia r1, {r4-r8}
242 add r1, r1, r2
243 @@ pld [r1]
244 ADJ_ALIGN_QW 16, r4, r5, r6, r7, r8
245 AVG_PW r7, r8
246 AVG_PW r6, r7
247 AVG_PW r5, r6
248 AVG_PW r4, r5
249 stmia r0, {r5-r8}
250 subs r3, r3, #1
251 add r0, r0, r2
252 bne 1b
253 ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
254
255MC_put_x_16_align3:
256 and r1, r1, #0xFFFFFFFC
2571: ldmia r1, {r4-r8}
258 add r1, r1, r2
259 @@ pld [r1]
260 ADJ_ALIGN_QW 24, r4, r5, r6, r7, r8
261 AVG_PW r7, r8
262 AVG_PW r6, r7
263 AVG_PW r5, r6
264 AVG_PW r4, r5
265 stmia r0, {r5-r8}
266 subs r3, r3, #1
267 add r0, r0, r2
268 bne 1b
269 ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
270
271@ ----------------------------------------------------------------
272 .align
273 .global MC_put_x_8
274MC_put_x_8:
275 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
276 @@ pld [r1]
277 stmfd sp!, {r6-HIGHEST_REG, lr} @ R14 is also called LR
278 and r6, r1, #3
279 ldr r12, 2f
280#if ARM_ARCH < 6
281 mvn r11, r12
282#endif
283 ldr pc, [pc, r6, lsl #2]
2842: .word 0x01010101
285 .word MC_put_x_8_align0
286 .word MC_put_x_8_align1
287 .word MC_put_x_8_align2
288 .word MC_put_x_8_align3
289
290MC_put_x_8_align0:
291 ldmia r1, {r6-r8}
292 add r1, r1, r2
293 @@ pld [r1]
294 AVG_PW r7, r8
295 AVG_PW r6, r7
296 stmia r0, {r7-r8}
297 subs r3, r3, #1
298 add r0, r0, r2
299 bne MC_put_x_8_align0
300 ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
301
302MC_put_x_8_align1:
303 and r1, r1, #0xFFFFFFFC
3041: ldmia r1, {r6-r8}
305 add r1, r1, r2
306 @@ pld [r1]
307 ADJ_ALIGN_DW 8, r6, r7, r8
308 AVG_PW r7, r8
309 AVG_PW r6, r7
310 stmia r0, {r7-r8}
311 subs r3, r3, #1
312 add r0, r0, r2
313 bne 1b
314 ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
315
316MC_put_x_8_align2:
317 and r1, r1, #0xFFFFFFFC
3181: ldmia r1, {r6-r8}
319 add r1, r1, r2
320 @@ pld [r1]
321 ADJ_ALIGN_DW 16, r6, r7, r8
322 AVG_PW r7, r8
323 AVG_PW r6, r7
324 stmia r0, {r7-r8}
325 subs r3, r3, #1
326 add r0, r0, r2
327 bne 1b
328 ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
329
330MC_put_x_8_align3:
331 and r1, r1, #0xFFFFFFFC
3321: ldmia r1, {r6-r8}
333 add r1, r1, r2
334 @@ pld [r1]
335 ADJ_ALIGN_DW 24, r6, r7, r8
336 AVG_PW r7, r8
337 AVG_PW r6, r7
338 stmia r0, {r7-r8}
339 subs r3, r3, #1
340 add r0, r0, r2
341 bne 1b
342 ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
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