diff options
-rw-r--r-- | firmware/system.c | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/firmware/system.c b/firmware/system.c index 03414924ca..341e2938fb 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -483,7 +483,7 @@ void set_cpu_frequency(long frequency) | |||
483 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 483 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass |
484 | frequency */ | 484 | frequency */ |
485 | PLLCR &= ~1; /* Bypass mode */ | 485 | PLLCR &= ~1; /* Bypass mode */ |
486 | PLLCR = 0x11853005; | 486 | PLLCR = 0x11c53005; |
487 | CSCR0 = 0x00000980; /* Flash: 2 wait state */ | 487 | CSCR0 = 0x00000980; /* Flash: 2 wait state */ |
488 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ | 488 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ |
489 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 489 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -491,15 +491,18 @@ void set_cpu_frequency(long frequency) | |||
491 | DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */ | 491 | DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */ |
492 | cpu_frequency = CPUFREQ_MAX; | 492 | cpu_frequency = CPUFREQ_MAX; |
493 | tick_start(1000/HZ); | 493 | tick_start(1000/HZ); |
494 | IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (5 << 10); /* CS2Pre,Post */ | 494 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
495 | IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (1 << 8); /* CS2wait */ | 495 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ |
496 | /* I2C Clock divisor = 1280 => 119.952 MHz / 1280 = 93,7 kHz */ | ||
497 | MFDR = 0x19; | ||
498 | MFDR2 = 0x19; | ||
496 | break; | 499 | break; |
497 | 500 | ||
498 | case CPUFREQ_NORMAL: | 501 | case CPUFREQ_NORMAL: |
499 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 502 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass |
500 | frequency */ | 503 | frequency */ |
501 | PLLCR &= ~1; /* Bypass mode */ | 504 | PLLCR &= ~1; /* Bypass mode */ |
502 | PLLCR = 0x10c86801; | 505 | PLLCR = 0x10c86001; |
503 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 506 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
504 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 507 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
505 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 508 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -507,19 +510,25 @@ void set_cpu_frequency(long frequency) | |||
507 | DCR = (DCR & ~0x000001ff) | 10; /* Refresh timer */ | 510 | DCR = (DCR & ~0x000001ff) | 10; /* Refresh timer */ |
508 | cpu_frequency = CPUFREQ_NORMAL; | 511 | cpu_frequency = CPUFREQ_NORMAL; |
509 | tick_start(1000/HZ); | 512 | tick_start(1000/HZ); |
510 | IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (5 << 10); /* CS2Pre,Post */ | 513 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
511 | IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (0 << 8); /* CS2wait */ | 514 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
515 | /* I2C Clock divisor = 480 => 47.9808 MHz / 480 = 99,9 kHz */ | ||
516 | MFDR = 0x13; | ||
517 | MFDR2 = 0x13; | ||
512 | break; | 518 | break; |
513 | default: | 519 | default: |
514 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 520 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass |
515 | frequency */ | 521 | frequency */ |
516 | PLLCR &= ~1; /* Bypass mode */ | 522 | PLLCR = 0x00400000; /* Bypass mode */ |
517 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 523 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
518 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 524 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
519 | cpu_frequency = CPU_FREQ; | 525 | cpu_frequency = CPU_FREQ; |
520 | tick_start(1000/HZ); | 526 | tick_start(1000/HZ); |
521 | IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (1 << 10); /* CS2Pre,Post */ | 527 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
522 | IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (0 << 8); /* CS2wait */ | 528 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
529 | /* I2C Clock divisor = 480 => 47.9808 MHz / 480 = 99,9 kHz */ | ||
530 | MFDR = 0x13; | ||
531 | MFDR2 = 0x13; | ||
523 | break; | 532 | break; |
524 | } | 533 | } |
525 | } | 534 | } |