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-rw-r--r--utils/regtools/desc/regs-jz4760b.xml832
1 files changed, 582 insertions, 250 deletions
diff --git a/utils/regtools/desc/regs-jz4760b.xml b/utils/regtools/desc/regs-jz4760b.xml
index 2ff16e7c2b..1d0df1bdd8 100644
--- a/utils/regtools/desc/regs-jz4760b.xml
+++ b/utils/regtools/desc/regs-jz4760b.xml
@@ -13,96 +13,267 @@
13 </node> 13 </node>
14 <node> 14 <node>
15 <name>CPM</name> 15 <name>CPM</name>
16 <title>Clock, Reset and Power Module</title>
16 <instance> 17 <instance>
17 <name>CPM</name> 18 <name>CPM</name>
18 <address>0xb0000000</address> 19 <address>0xb0000000</address>
19 </instance> 20 </instance>
20 <node> 21 <node>
21 <name>CTRL</name> 22 <name>SYSCLK</name>
22 <title>Clock control register</title> 23 <title>Clock control register</title>
23 <instance> 24 <instance>
24 <name>CTRL</name> 25 <name>SYSCLK</name>
25 <address>0x0</address> 26 <address>0x0</address>
26 </instance> 27 </instance>
27 <register> 28 <register>
28 <field> 29 <field>
29 <name>ECS</name> 30 <name>EXCLK_DIV</name>
31 <desc>Only applies to APB periperals: UART, I2S, I2C, SSI, SADC, OTG, etc</desc>
30 <position>31</position> 32 <position>31</position>
33 <enum>
34 <name>BY_1</name>
35 <value>0x0</value>
36 </enum>
37 <enum>
38 <name>BY_2</name>
39 <value>0x1</value>
40 </enum>
31 </field> 41 </field>
32 <field> 42 <field>
33 <name>MEM</name> 43 <name>MEM_TYPE</name>
34 <position>30</position> 44 <position>30</position>
45 <enum>
46 <name>MDDR_SDRAM</name>
47 <value>0x0</value>
48 </enum>
49 <enum>
50 <name>DDR_DD2</name>
51 <value>0x1</value>
52 </enum>
35 </field> 53 </field>
36 <field> 54 <field>
37 <name>SDIV</name> 55 <name>SCLK_DIV</name>
38 <position>24</position> 56 <position>24</position>
39 <width>4</width> 57 <width>4</width>
58 <enum>
59 <name>BY_1</name>
60 <value>0x0</value>
61 </enum>
62 <enum>
63 <name>BY_2</name>
64 <value>0x1</value>
65 </enum>
66 <enum>
67 <name>BY_3</name>
68 <value>0x2</value>
69 </enum>
70 <enum>
71 <name>BY_4</name>
72 <value>0x3</value>
73 </enum>
74 <enum>
75 <name>BY_6</name>
76 <value>0x4</value>
77 </enum>
78 <enum>
79 <name>BY_8</name>
80 <value>0x5</value>
81 </enum>
40 </field> 82 </field>
41 <field> 83 <field>
42 <name>CE</name> 84 <name>EN_CHANGE</name>
43 <position>22</position> 85 <position>22</position>
44 </field> 86 </field>
45 <field> 87 <field>
46 <name>PCS</name> 88 <name>PLL_DIV</name>
89 <desc>Only applies to MSC, I2S, LCD, UHC, OTG, SSI, PCM, GPU and GPS.</desc>
47 <position>21</position> 90 <position>21</position>
91 <enum>
92 <name>BY_2</name>
93 <value>0x0</value>
94 </enum>
95 <enum>
96 <name>BY_1</name>
97 <value>0x1</value>
98 </enum>
48 </field> 99 </field>
49 <field> 100 <field>
50 <name>H2DIV</name> 101 <name>H2CLK_DIV</name>
51 <position>16</position> 102 <position>16</position>
52 <width>4</width> 103 <width>4</width>
104 <enum>
105 <name>BY_1</name>
106 <value>0x0</value>
107 </enum>
108 <enum>
109 <name>BY_2</name>
110 <value>0x1</value>
111 </enum>
112 <enum>
113 <name>BY_3</name>
114 <value>0x2</value>
115 </enum>
116 <enum>
117 <name>BY_4</name>
118 <value>0x3</value>
119 </enum>
120 <enum>
121 <name>BY_6</name>
122 <value>0x4</value>
123 </enum>
124 <enum>
125 <name>BY_8</name>
126 <value>0x5</value>
127 </enum>
53 </field> 128 </field>
54 <field> 129 <field>
55 <name>MDIV</name> 130 <name>MCLK_DIV</name>
56 <position>12</position> 131 <position>12</position>
57 <width>4</width> 132 <width>4</width>
133 <enum>
134 <name>BY_1</name>
135 <value>0x0</value>
136 </enum>
137 <enum>
138 <name>BY_2</name>
139 <value>0x1</value>
140 </enum>
141 <enum>
142 <name>BY_3</name>
143 <value>0x2</value>
144 </enum>
145 <enum>
146 <name>BY_4</name>
147 <value>0x3</value>
148 </enum>
149 <enum>
150 <name>BY_6</name>
151 <value>0x4</value>
152 </enum>
153 <enum>
154 <name>BY_8</name>
155 <value>0x5</value>
156 </enum>
58 </field> 157 </field>
59 <field> 158 <field>
60 <name>PDIV</name> 159 <name>PCLK_DIV</name>
61 <position>8</position> 160 <position>8</position>
62 <width>4</width> 161 <width>4</width>
162 <enum>
163 <name>BY_1</name>
164 <value>0x0</value>
165 </enum>
166 <enum>
167 <name>BY_2</name>
168 <value>0x1</value>
169 </enum>
170 <enum>
171 <name>BY_3</name>
172 <value>0x2</value>
173 </enum>
174 <enum>
175 <name>BY_4</name>
176 <value>0x3</value>
177 </enum>
178 <enum>
179 <name>BY_6</name>
180 <value>0x4</value>
181 </enum>
182 <enum>
183 <name>BY_8</name>
184 <value>0x5</value>
185 </enum>
63 </field> 186 </field>
64 <field> 187 <field>
65 <name>HDIV</name> 188 <name>HCLK_DIV</name>
66 <position>4</position> 189 <position>4</position>
67 <width>4</width> 190 <width>4</width>
191 <enum>
192 <name>BY_1</name>
193 <value>0x0</value>
194 </enum>
195 <enum>
196 <name>BY_2</name>
197 <value>0x1</value>
198 </enum>
199 <enum>
200 <name>BY_3</name>
201 <value>0x2</value>
202 </enum>
203 <enum>
204 <name>BY_4</name>
205 <value>0x3</value>
206 </enum>
207 <enum>
208 <name>BY_6</name>
209 <value>0x4</value>
210 </enum>
211 <enum>
212 <name>BY_8</name>
213 <value>0x5</value>
214 </enum>
68 </field> 215 </field>
69 <field> 216 <field>
70 <name>CDIV</name> 217 <name>CCLK_DIV</name>
71 <position>0</position> 218 <position>0</position>
72 <width>4</width> 219 <width>4</width>
220 <enum>
221 <name>BY_1</name>
222 <value>0x0</value>
223 </enum>
224 <enum>
225 <name>BY_2</name>
226 <value>0x1</value>
227 </enum>
228 <enum>
229 <name>BY_3</name>
230 <value>0x2</value>
231 </enum>
232 <enum>
233 <name>BY_4</name>
234 <value>0x3</value>
235 </enum>
236 <enum>
237 <name>BY_6</name>
238 <value>0x4</value>
239 </enum>
240 <enum>
241 <name>BY_8</name>
242 <value>0x5</value>
243 </enum>
73 </field> 244 </field>
74 </register> 245 </register>
75 </node> 246 </node>
76 <node> 247 <node>
77 <name>LOW</name> 248 <name>LOWPWR</name>
78 <title>Low power control register</title> 249 <title>Low power control register</title>
79 <instance> 250 <instance>
80 <name>LOW</name> 251 <name>LOWPWR</name>
81 <address>0x4</address> 252 <address>0x4</address>
82 </instance> 253 </instance>
83 <register> 254 <register>
84 <field> 255 <field>
85 <name>PDAHB1</name> 256 <name>AHB1_PWD</name>
86 <position>30</position> 257 <position>30</position>
87 </field> 258 </field>
88 <field> 259 <field>
89 <name>VBATIR</name> 260 <name>VBAT_IR</name>
90 <position>29</position> 261 <position>29</position>
91 </field> 262 </field>
92 <field> 263 <field>
93 <name>PDGPS</name> 264 <name>GPS_PWD</name>
94 <position>28</position> 265 <position>28</position>
95 </field> 266 </field>
96 <field> 267 <field>
97 <name>PDAHB1S</name> 268 <name>AHB1S_PWD</name>
98 <position>26</position> 269 <position>26</position>
99 </field> 270 </field>
100 <field> 271 <field>
101 <name>PDGPSS</name> 272 <name>GPSS_PWD</name>
102 <position>24</position> 273 <position>24</position>
103 </field> 274 </field>
104 <field> 275 <field>
105 <name>PST</name> 276 <name>PWR_STABILITY_TIME</name>
106 <position>8</position> 277 <position>8</position>
107 <width>12</width> 278 <width>12</width>
108 </field> 279 </field>
@@ -116,7 +287,7 @@
116 <position>2</position> 287 <position>2</position>
117 </field> 288 </field>
118 <field> 289 <field>
119 <name>LPM</name> 290 <name>SLEEP_MODE</name>
120 <position>0</position> 291 <position>0</position>
121 <width>2</width> 292 <width>2</width>
122 <enum> 293 <enum>
@@ -134,46 +305,65 @@
134 <name>RESET</name> 305 <name>RESET</name>
135 <title>Reset status register</title> 306 <title>Reset status register</title>
136 <instance> 307 <instance>
137 <name>RESET</name> 308 <name>RESETSTS</name>
138 <address>0x8</address> 309 <address>0x8</address>
139 </instance> 310 </instance>
140 <register> 311 <register>
141 <field> 312 <field>
142 <name>P0R</name> 313 <name>PWRUP_STS</name>
143 <position>2</position> 314 <position>2</position>
144 </field> 315 </field>
145 <field> 316 <field>
146 <name>WR</name> 317 <name>WATCHDOG_STS</name>
147 <position>1</position> 318 <position>1</position>
148 </field> 319 </field>
149 <field> 320 <field>
150 <name>PR</name> 321 <name>PWRON_STS</name>
151 <position>0</position> 322 <position>0</position>
152 </field> 323 </field>
153 </register> 324 </register>
154 </node> 325 </node>
155 <node> 326 <node>
156 <name>PLL0</name> 327 <name>PLLCTRL0</name>
157 <title>PLL control register 0</title> 328 <title>PLL control register 0</title>
158 <instance> 329 <instance>
159 <name>PL</name> 330 <name>PLLCTRL0</name>
160 <address>0x10</address> 331 <address>0x10</address>
161 </instance> 332 </instance>
162 <register> 333 <register>
163 <field> 334 <field>
164 <name>PLLM</name> 335 <name>FEED_DIV</name>
336 <desc>PLLM</desc>
165 <position>24</position> 337 <position>24</position>
166 <width>7</width> 338 <width>7</width>
167 </field> 339 </field>
168 <field> 340 <field>
169 <name>PLLN</name> 341 <name>IN_DIV</name>
342 <desc>PLLN</desc>
170 <position>18</position> 343 <position>18</position>
171 <width>4</width> 344 <width>4</width>
172 </field> 345 </field>
173 <field> 346 <field>
174 <name>PLLOD</name> 347 <name>OUT_DIV</name>
348 <desc>PLLOD</desc>
175 <position>16</position> 349 <position>16</position>
176 <width>2</width> 350 <width>2</width>
351 <enum>
352 <name>BY_1</name>
353 <value>0x0</value>
354 </enum>
355 <enum>
356 <name>BY_2</name>
357 <value>0x1</value>
358 </enum>
359 <enum>
360 <name>BY_4</name>
361 <value>0x2</value>
362 </enum>
363 <enum>
364 <name>BY_8</name>
365 <value>0x3</value>
366 </enum>
177 </field> 367 </field>
178 <field> 368 <field>
179 <name>LOCK</name> 369 <name>LOCK</name>
@@ -181,23 +371,23 @@
181 <position>15</position> 371 <position>15</position>
182 </field> 372 </field>
183 <field> 373 <field>
184 <name>ENLOCK</name> 374 <name>EN_LOCK</name>
185 <position>14</position> 375 <position>14</position>
186 </field> 376 </field>
187 <field> 377 <field>
188 <name>PLLS</name> 378 <name>STABLE</name>
189 <position>10</position> 379 <position>10</position>
190 </field> 380 </field>
191 <field> 381 <field>
192 <name>PLLBP</name> 382 <name>BYPASS</name>
193 <position>9</position> 383 <position>9</position>
194 </field> 384 </field>
195 <field> 385 <field>
196 <name>PLLEN</name> 386 <name>ENABLE</name>
197 <position>8</position> 387 <position>8</position>
198 </field> 388 </field>
199 <field> 389 <field>
200 <name>PLLST</name> 390 <name>STABILIZE_TIME</name>
201 <position>0</position> 391 <position>0</position>
202 <width>8</width> 392 <width>8</width>
203 </field> 393 </field>
@@ -212,48 +402,72 @@
212 </instance> 402 </instance>
213 <register> 403 <register>
214 <field> 404 <field>
215 <name>PLLOFF</name> 405 <name>OFF_STS</name>
216 <position>31</position> 406 <position>31</position>
217 </field> 407 </field>
218 <field> 408 <field>
219 <name>PLLBP</name> 409 <name>BYPASS_STS</name>
220 <position>30</position> 410 <position>30</position>
221 </field> 411 </field>
222 <field> 412 <field>
223 <name>PLLON</name> 413 <name>ON_STS</name>
224 <position>29</position> 414 <position>29</position>
225 </field> 415 </field>
226 <field> 416 <field>
227 <name>PS</name> 417 <name>ENABLE_STS</name>
228 <position>28</position> 418 <position>28</position>
229 </field> 419 </field>
230 <field> 420 <field>
231 <name>FS</name> 421 <name>FREQ_STS</name>
232 <position>27</position> 422 <position>27</position>
233 </field> 423 </field>
234 <field> 424 <field>
235 <name>CS</name> 425 <name>SRC_STS</name>
236 <position>26</position> 426 <position>26</position>
237 </field> 427 </field>
238 <field> 428 <field>
239 <name>SM</name> 429 <name>SYS_CHANGE_MODE</name>
240 <position>2</position> 430 <position>2</position>
431 <enum>
432 <name>HW</name>
433 <value>0x0</value>
434 </enum>
435 <enum>
436 <name>STOP</name>
437 <value>0x1</value>
438 </enum>
241 </field> 439 </field>
242 <field> 440 <field>
243 <name>PM</name> 441 <name>SRC_SWITCH_MODE</name>
244 <position>1</position> 442 <position>1</position>
443 <enum>
444 <name>SLOW</name>
445 <value>0x0</value>
446 </enum>
447 <enum>
448 <name>FAST</name>
449 <value>0x1</value>
450 </enum>
245 </field> 451 </field>
246 <field> 452 <field>
247 <name>FM</name> 453 <name>FREQ_CHANGE_MODE</name>
248 <position>0</position> 454 <position>0</position>
455 <enum>
456 <name>SLOW</name>
457 <value>0x0</value>
458 </enum>
459 <enum>
460 <name>FAST</name>
461 <value>0x1</value>
462 </enum>
249 </field> 463 </field>
250 </register> 464 </register>
251 </node> 465 </node>
252 <node> 466 <node>
253 <name>GATE0</name> 467 <name>CLKGATE0</name>
254 <title>Clock gate register 0</title> 468 <title>Clock gate register 0</title>
255 <instance> 469 <instance>
256 <name>GATE0</name> 470 <name>CLKGATE0</name>
257 <address>0x20</address> 471 <address>0x20</address>
258 </instance> 472 </instance>
259 <register> 473 <register>
@@ -388,51 +602,58 @@
388 </register> 602 </register>
389 </node> 603 </node>
390 <node> 604 <node>
391 <name>OSC</name> 605 <name>OSCPWR</name>
392 <title>Oscillator and power control register</title> 606 <title>Oscillator and power control register</title>
393 <instance> 607 <instance>
394 <name>OSC</name> 608 <name>OSCPWR</name>
395 <address>0x24</address> 609 <address>0x24</address>
396 </instance> 610 </instance>
397 <register> 611 <register>
398 <field> 612 <field>
399 <name>O1ST</name> 613 <name>STABILIZE_TIME</name>
400 <position>8</position> 614 <position>8</position>
401 <width>8</width> 615 <width>8</width>
402 </field> 616 </field>
403 <field> 617 <field>
404 <name>OTGPHY_ENABLE</name> 618 <name>OTG_SUSPEND</name>
405 <desc>SPENDN bit</desc>
406 <position>7</position> 619 <position>7</position>
407 </field> 620 </field>
408 <field> 621 <field>
409 <name>GPSEN</name> 622 <name>GPS_ENABLE</name>
410 <position>6</position> 623 <position>6</position>
411 </field> 624 </field>
412 <field> 625 <field>
413 <name>UHCPHY_DISABLE</name> 626 <name>UHC_SUSPEND</name>
414 <desc>SPENDH bit</desc> 627 <desc>SPENDH bit</desc>
415 <position>5</position> 628 <position>5</position>
416 </field> 629 </field>
417 <field> 630 <field>
418 <name>O1SE</name> 631 <name>OSC_SLEEP</name>
419 <position>4</position> 632 <position>4</position>
420 </field> 633 </field>
421 <field> 634 <field>
422 <name>PD</name> 635 <name>P0_SLEEP</name>
423 <position>3</position> 636 <position>3</position>
424 </field> 637 </field>
425 <field> 638 <field>
426 <name>ERCS</name> 639 <name>SRC_SEL</name>
427 <position>2</position> 640 <position>2</position>
641 <enum>
642 <name>EXCLK_DIV_512</name>
643 <value>0x0</value>
644 </enum>
645 <enum>
646 <name>RTCLK</name>
647 <value>0x1</value>
648 </enum>
428 </field> 649 </field>
429 </register> 650 </register>
430 </node> 651 </node>
431 <node> 652 <node>
432 <name>GATE1</name> 653 <name>CLKGATE1</name>
433 <title>Clock gate register 1</title> 654 <title>Clock gate register 1</title>
434 <instance> 655 <instance>
435 <name>GATE1</name> 656 <name>CLKGATE1</name>
436 <address>0x28</address> 657 <address>0x28</address>
437 </instance> 658 </instance>
438 <register> 659 <register>
@@ -487,43 +708,67 @@
487 </register> 708 </register>
488 </node> 709 </node>
489 <node> 710 <node>
490 <name>PLL1</name> 711 <name>PLLCTRL1</name>
491 <title>PLL control register 1</title> 712 <title>PLL control register 1</title>
492 <instance> 713 <instance>
493 <name>PLL1</name> 714 <name>PLLCTRL1</name>
494 <address>0x30</address> 715 <address>0x30</address>
495 </instance> 716 </instance>
496 <register> 717 <register>
497 <field> 718 <field>
498 <name>PLL1M</name> 719 <name>FEED_DIV</name>
499 <position>24</position> 720 <position>24</position>
500 <width>7</width> 721 <width>7</width>
501 </field> 722 </field>
502 <field> 723 <field>
503 <name>PLL1N</name> 724 <name>IN_DIV</name>
504 <position>18</position> 725 <position>18</position>
505 <width>4</width> 726 <width>4</width>
506 </field> 727 </field>
507 <field> 728 <field>
508 <name>PLL1OD</name> 729 <name>OUT_DIV</name>
509 <position>16</position> 730 <position>16</position>
510 <width>2</width> 731 <width>2</width>
732 <enum>
733 <name>BY_1</name>
734 <value>0x0</value>
735 </enum>
736 <enum>
737 <name>BY_2</name>
738 <value>0x1</value>
739 </enum>
740 <enum>
741 <name>BY_4</name>
742 <value>0x2</value>
743 </enum>
744 <enum>
745 <name>BY_8</name>
746 <value>0x3</value>
747 </enum>
511 </field> 748 </field>
512 <field> 749 <field>
513 <name>P1SCS</name> 750 <name>SRC_SEL</name>
514 <position>15</position> 751 <position>15</position>
752 <enum>
753 <name>EXCLK</name>
754 <value>0x0</value>
755 </enum>
756 <enum>
757 <name>PLL0</name>
758 <value>0x1</value>
759 </enum>
515 </field> 760 </field>
516 <field> 761 <field>
517 <name>P1SDIV</name> 762 <name>PLL0_DIV</name>
518 <position>9</position> 763 <position>9</position>
519 <width>6</width> 764 <width>6</width>
520 </field> 765 </field>
521 <field> 766 <field>
522 <name>PLL1EN</name> 767 <name>ENABLE</name>
523 <position>7</position> 768 <position>7</position>
524 </field> 769 </field>
525 <field> 770 <field>
526 <name>PLL1S</name> 771 <name>STABLE</name>
527 <position>6</position> 772 <position>6</position>
528 </field> 773 </field>
529 <field> 774 <field>
@@ -532,11 +777,11 @@
532 <position>2</position> 777 <position>2</position>
533 </field> 778 </field>
534 <field> 779 <field>
535 <name>PLL1OFF</name> 780 <name>OFF</name>
536 <position>1</position> 781 <position>1</position>
537 </field> 782 </field>
538 <field> 783 <field>
539 <name>PLL1ON</name> 784 <name>ON</name>
540 <position>0</position> 785 <position>0</position>
541 </field> 786 </field>
542 </register> 787 </register>
@@ -560,10 +805,10 @@
560 <register/> 805 <register/>
561 </node> 806 </node>
562 <node> 807 <node>
563 <name>USBPARAM</name> 808 <name>USBCTRL</name>
564 <title>OTG parameter control register</title> 809 <title>OTG parameter control register</title>
565 <instance> 810 <instance>
566 <name>USBPARAM</name> 811 <name>USBCTRL</name>
567 <address>0x3c</address> 812 <address>0x3c</address>
568 </instance> 813 </instance>
569 <register> 814 <register>
@@ -686,139 +931,205 @@
686 <register/> 931 <register/>
687 </node> 932 </node>
688 <node> 933 <node>
689 <name>USB</name> 934 <name>USBCLK</name>
690 <title>OTG PHY clock divider register</title> 935 <title>OTG PHY clock divider register</title>
691 <instance> 936 <instance>
692 <name>USB</name> 937 <name>USBCLK</name>
693 <address>0x50</address> 938 <address>0x50</address>
694 </instance> 939 </instance>
695 <register> 940 <register>
696 <field> 941 <field>
697 <name>UCS</name> 942 <name>SRC_SEL</name>
698 <position>31</position> 943 <position>31</position>
944 <enum>
945 <name>EXCLK</name>
946 <value>0x0</value>
947 </enum>
948 <enum>
949 <name>PLL</name>
950 <value>0x1</value>
951 </enum>
699 </field> 952 </field>
700 <field> 953 <field>
701 <name>UPCS</name> 954 <name>PLL_SEL</name>
702 <position>30</position> 955 <position>30</position>
956 <enum>
957 <name>PLL0</name>
958 <value>0x0</value>
959 </enum>
960 <enum>
961 <name>PLL1</name>
962 <value>0x1</value>
963 </enum>
703 </field> 964 </field>
704 <field> 965 <field>
705 <name>OTGDIV</name> 966 <name>DIV</name>
706 <desc>USBCDR bit</desc>
707 <position>0</position> 967 <position>0</position>
708 <width>6</width> 968 <width>6</width>
709 </field> 969 </field>
710 </register> 970 </register>
711 </node> 971 </node>
712 <node> 972 <node>
713 <name>I2S</name> 973 <name>I2SCLK</name>
714 <title>I2S device clock divider register</title> 974 <title>I2S device clock divider register</title>
715 <instance> 975 <instance>
716 <name>I2S</name> 976 <name>I2SCLK</name>
717 <address>0x60</address> 977 <address>0x60</address>
718 </instance> 978 </instance>
719 <register> 979 <register>
720 <field> 980 <field>
721 <name>I2CS</name> 981 <name>SRC_SEL</name>
722 <position>31</position> 982 <position>31</position>
983 <enum>
984 <name>EXCLK</name>
985 <value>0x0</value>
986 </enum>
987 <enum>
988 <name>PLL</name>
989 <value>0x1</value>
990 </enum>
723 </field> 991 </field>
724 <field> 992 <field>
725 <name>I2PCS</name> 993 <name>PLL_SEL</name>
726 <position>30</position> 994 <position>30</position>
995 <enum>
996 <name>PLL0</name>
997 <value>0x0</value>
998 </enum>
999 <enum>
1000 <name>PLL1</name>
1001 <value>0x1</value>
1002 </enum>
727 </field> 1003 </field>
728 <field> 1004 <field>
729 <name>I2SDIV</name> 1005 <name>DIV</name>
730 <desc>I2SCDR bit</desc>
731 <position>0</position> 1006 <position>0</position>
732 <width>9</width> 1007 <width>9</width>
733 </field> 1008 </field>
734 </register> 1009 </register>
735 </node> 1010 </node>
736 <node> 1011 <node>
737 <name>LCD</name> 1012 <name>LCDCLK</name>
738 <title>LCD pix clock divider register</title> 1013 <title>LCD pix clock divider register</title>
739 <instance> 1014 <instance>
740 <name>LCD</name> 1015 <name>LCDCLK</name>
741 <address>0x64</address> 1016 <address>0x64</address>
742 </instance> 1017 </instance>
743 <register> 1018 <register>
744 <field> 1019 <field>
745 <name>LTCS</name> 1020 <name>SRC_SEL</name>
746 <position>30</position> 1021 <position>30</position>
1022 <enum>
1023 <name>EXCLK</name>
1024 <value>0x0</value>
1025 </enum>
1026 <enum>
1027 <name>PLL</name>
1028 <value>0x1</value>
1029 </enum>
747 </field> 1030 </field>
748 <field> 1031 <field>
749 <name>LPCS</name> 1032 <name>PLL_SEL</name>
750 <position>29</position> 1033 <position>29</position>
1034 <enum>
1035 <name>PLL0</name>
1036 <value>0x0</value>
1037 </enum>
1038 <enum>
1039 <name>PLL1</name>
1040 <value>0x1</value>
1041 </enum>
751 </field> 1042 </field>
752 <field> 1043 <field>
753 <name>PIXDIV</name> 1044 <name>DIV</name>
754 <desc>LPCDR bit</desc>
755 <position>0</position> 1045 <position>0</position>
756 <width>11</width> 1046 <width>11</width>
757 </field> 1047 </field>
758 </register> 1048 </register>
759 </node> 1049 </node>
760 <node> 1050 <node>
761 <name>MSC</name> 1051 <name>MSCCLK</name>
762 <title>MSC clock divider register</title> 1052 <title>MSC clock divider register</title>
763 <instance> 1053 <instance>
764 <name>MSC</name> 1054 <name>MSCCLK</name>
765 <address>0x68</address> 1055 <address>0x68</address>
766 </instance> 1056 </instance>
767 <register> 1057 <register>
768 <field> 1058 <field>
769 <name>MCS</name> 1059 <name>SRC_SEL</name>
770 <position>31</position> 1060 <position>31</position>
1061 <enum>
1062 <name>EXCLK</name>
1063 <value>0x0</value>
1064 </enum>
1065 <enum>
1066 <name>PLL</name>
1067 <value>0x1</value>
1068 </enum>
771 </field> 1069 </field>
772 <field> 1070 <field>
773 <name>MSCDIV</name> 1071 <name>DIV</name>
774 <desc>MSCCDR bit</desc>
775 <position>0</position> 1072 <position>0</position>
776 <width>6</width> 1073 <width>6</width>
777 </field> 1074 </field>
778 </register> 1075 </register>
779 </node> 1076 </node>
780 <node> 1077 <node>
781 <name>UHC</name> 1078 <name>UHCCLK</name>
782 <title>UHC device clock divider register</title> 1079 <title>UHC device clock divider register</title>
783 <instance> 1080 <instance>
784 <name>UHC</name> 1081 <name>UHCCLK</name>
785 <address>0x6c</address> 1082 <address>0x6c</address>
786 </instance> 1083 </instance>
787 <register> 1084 <register>
788 <field> 1085 <field>
789 <name>UHPCS</name> 1086 <name>PLL_SEL</name>
790 <position>31</position> 1087 <position>31</position>
1088 <enum>
1089 <name>PLL0</name>
1090 <value>0x0</value>
1091 </enum>
1092 <enum>
1093 <name>PLL1</name>
1094 <value>0x1</value>
1095 </enum>
791 </field> 1096 </field>
792 <field> 1097 <field>
793 <name>UHCDIV</name> 1098 <name>DIV</name>
794 <desc>UHCCDR bit</desc>
795 <position>0</position> 1099 <position>0</position>
796 <width>4</width> 1100 <width>4</width>
797 </field> 1101 </field>
798 </register> 1102 </register>
799 </node> 1103 </node>
800 <node> 1104 <node>
801 <name>SSI</name> 1105 <name>SSICLK</name>
802 <title>SSI clock divider register</title> 1106 <title>SSI clock divider register</title>
803 <instance> 1107 <instance>
804 <name>SSI</name> 1108 <name>SSICLK</name>
805 <address>0x74</address> 1109 <address>0x74</address>
806 </instance> 1110 </instance>
807 <register> 1111 <register>
808 <field> 1112 <field>
809 <name>SCS</name> 1113 <name>SRC_SEL</name>
810 <position>31</position> 1114 <position>31</position>
1115 <enum>
1116 <name>EXCLK</name>
1117 <value>0x0</value>
1118 </enum>
1119 <enum>
1120 <name>PLL</name>
1121 <value>0x1</value>
1122 </enum>
811 </field> 1123 </field>
812 <field> 1124 <field>
813 <name>SSIDIV</name> 1125 <name>DIV</name>
814 <desc>SSICDR bit</desc>
815 <position>0</position> 1126 <position>0</position>
816 <width>6</width> 1127 <width>6</width>
817 </field> 1128 </field>
818 </register> 1129 </register>
819 </node> 1130 </node>
820 <node> 1131 <node>
821 <name>CIM</name> 1132 <name>CIMCLK</name>
822 <title>CIM mclk clock divider register</title> 1133 <title>CIM mclk clock divider register</title>
823 <instance> 1134 <instance>
824 <name>CIM</name> 1135 <name>CIM</name>
@@ -826,15 +1137,14 @@
826 </instance> 1137 </instance>
827 <register> 1138 <register>
828 <field> 1139 <field>
829 <name>CIMDIV</name> 1140 <name>DIV</name>
830 <desc>CIMCDR bit</desc>
831 <position>0</position> 1141 <position>0</position>
832 <width>8</width> 1142 <width>8</width>
833 </field> 1143 </field>
834 </register> 1144 </register>
835 </node> 1145 </node>
836 <node> 1146 <node>
837 <name>GPS</name> 1147 <name>GPSCLK</name>
838 <title>GPS clock divider register</title> 1148 <title>GPS clock divider register</title>
839 <instance> 1149 <instance>
840 <name>GPS</name> 1150 <name>GPS</name>
@@ -842,35 +1152,58 @@
842 </instance> 1152 </instance>
843 <register> 1153 <register>
844 <field> 1154 <field>
845 <name>GPCS</name> 1155 <name>PLL_SEL</name>
846 <position>31</position> 1156 <position>31</position>
1157 <enum>
1158 <name>PLL0</name>
1159 <value>0x0</value>
1160 </enum>
1161 <enum>
1162 <name>PLL1</name>
1163 <value>0x1</value>
1164 </enum>
847 </field> 1165 </field>
848 <field> 1166 <field>
849 <name>GPSDIV</name> 1167 <name>DIV</name>
850 <desc>GPSCDR bit</desc>
851 <position>0</position> 1168 <position>0</position>
852 <width>4</width> 1169 <width>4</width>
853 </field> 1170 </field>
854 </register> 1171 </register>
855 </node> 1172 </node>
856 <node> 1173 <node>
857 <name>PCM</name> 1174 <name>PCMCLK</name>
858 <title>PCM device clock divider register</title> 1175 <title>PCM device clock divider register</title>
859 <instance> 1176 <instance>
860 <name>PCM</name> 1177 <name>PCMCLK</name>
861 <address>0x84</address> 1178 <address>0x84</address>
862 </instance> 1179 </instance>
863 <register> 1180 <register>
864 <field> 1181 <field>
865 <name>PCMS</name> 1182 <name>SRC_SEL</name>
866 <position>31</position> 1183 <position>31</position>
1184 <enum>
1185 <name>EXCLK</name>
1186 <value>0x0</value>
1187 </enum>
1188 <enum>
1189 <name>PLL</name>
1190 <value>0x1</value>
1191 </enum>
867 </field> 1192 </field>
868 <field> 1193 <field>
869 <name>PCMPCS</name> 1194 <name>PLL_SEL</name>
870 <position>30</position> 1195 <position>30</position>
1196 <enum>
1197 <name>PLL0</name>
1198 <value>0x0</value>
1199 </enum>
1200 <enum>
1201 <name>PLL1</name>
1202 <value>0x1</value>
1203 </enum>
871 </field> 1204 </field>
872 <field> 1205 <field>
873 <name>PCMDIV</name> 1206 <name>DIV</name>
874 <desc>PCMCDR bit</desc> 1207 <desc>PCMCDR bit</desc>
875 <position>0</position> 1208 <position>0</position>
876 <width>9</width> 1209 <width>9</width>
@@ -878,19 +1211,26 @@
878 </register> 1211 </register>
879 </node> 1212 </node>
880 <node> 1213 <node>
881 <name>GPU</name> 1214 <name>GPUCLK</name>
882 <instance> 1215 <instance>
883 <name>GPU</name> 1216 <name>GPUCLK</name>
884 <address>0x88</address> 1217 <address>0x88</address>
885 </instance> 1218 </instance>
886 <register> 1219 <register>
887 <field> 1220 <field>
888 <name>GPCS</name> 1221 <name>PLL_SEL</name>
889 <position>31</position> 1222 <position>31</position>
1223 <enum>
1224 <name>PLL0</name>
1225 <value>0x0</value>
1226 </enum>
1227 <enum>
1228 <name>PLL1</name>
1229 <value>0x1</value>
1230 </enum>
890 </field> 1231 </field>
891 <field> 1232 <field>
892 <name>GPUDIV</name> 1233 <name>DIV</name>
893 <desc>GPUCDR bit</desc>
894 <position>0</position> 1234 <position>0</position>
895 <width>3</width> 1235 <width>3</width>
896 </field> 1236 </field>
@@ -937,9 +1277,9 @@
937 <address>0xb0001000</address> 1277 <address>0xb0001000</address>
938 </instance> 1278 </instance>
939 <node> 1279 <node>
940 <name>ISR</name> 1280 <name>STATUS</name>
941 <instance> 1281 <instance>
942 <name>ISR</name> 1282 <name>STATUS</name>
943 <range> 1283 <range>
944 <first>0</first> 1284 <first>0</first>
945 <count>2</count> 1285 <count>2</count>
@@ -949,45 +1289,30 @@
949 <register/> 1289 <register/>
950 </node> 1290 </node>
951 <node> 1291 <node>
952 <name>IMR</name> 1292 <name>MASK</name>
953 <instance> 1293 <instance>
954 <name>IMR</name> 1294 <name>MASK</name>
955 <range> 1295 <range>
956 <first>0</first> 1296 <first>0</first>
957 <count>2</count> 1297 <count>2</count>
958 <formula variable="n">0x04 + (n) * 0x20</formula> 1298 <formula variable="n">0x04 + (n) * 0x20</formula>
959 </range> 1299 </range>
960 </instance> 1300 </instance>
961 <register/> 1301 <register>
962 </node> 1302 <variant>
963 <node> 1303 <type>set</type>
964 <name>IMSR</name> 1304 <offset>4</offset>
965 <instance> 1305 </variant>
966 <name>IMSR</name> 1306 <variant>
967 <range> 1307 <type>clr</type>
968 <first>0</first> 1308 <offset>8</offset>
969 <count>2</count> 1309 </variant>
970 <formula variable="n">0x08 + (n) * 0x20</formula> 1310 </register>
971 </range>
972 </instance>
973 <register/>
974 </node>
975 <node>
976 <name>IMCR</name>
977 <instance>
978 <name>IMCR</name>
979 <range>
980 <first>0</first>
981 <count>2</count>
982 <formula variable="n">0x0c + (n) * 0x20</formula>
983 </range>
984 </instance>
985 <register/>
986 </node> 1311 </node>
987 <node> 1312 <node>
988 <name>IPR</name> 1313 <name>PENDING</name>
989 <instance> 1314 <instance>
990 <name>IPR</name> 1315 <name>PENDING</name>
991 <range> 1316 <range>
992 <first>0</first> 1317 <first>0</first>
993 <count>2</count> 1318 <count>2</count>
@@ -1041,12 +1366,20 @@
1041 <register> 1366 <register>
1042 <width>16</width> 1367 <width>16</width>
1043 <field> 1368 <field>
1044 <name>CNT_MD</name> 1369 <name>IGNORE_COMPARE</name>
1045 <position>15</position> 1370 <position>15</position>
1046 </field> 1371 </field>
1047 <field> 1372 <field>
1048 <name>SD</name> 1373 <name>SHUTDOWN</name>
1049 <position>9</position> 1374 <position>9</position>
1375 <enum>
1376 <name>GRACEFUL</name>
1377 <value>0x0</value>
1378 </enum>
1379 <enum>
1380 <name>ABRUPT</name>
1381 <value>0x1</value>
1382 </enum>
1050 </field> 1383 </field>
1051 <field> 1384 <field>
1052 <name>PRESCALE</name> 1385 <name>PRESCALE</name>
@@ -1117,11 +1450,11 @@
1117 <register> 1450 <register>
1118 <width>16</width> 1451 <width>16</width>
1119 <field> 1452 <field>
1120 <name>OSTEN</name> 1453 <name>OST</name>
1121 <position>15</position> 1454 <position>15</position>
1122 </field> 1455 </field>
1123 <field> 1456 <field>
1124 <name>TCEN</name> 1457 <name>TIMER</name>
1125 <position>0</position> 1458 <position>0</position>
1126 <width>8</width> 1459 <width>8</width>
1127 </field> 1460 </field>
@@ -1144,15 +1477,15 @@
1144 </instance> 1477 </instance>
1145 <register> 1478 <register>
1146 <field> 1479 <field>
1147 <name>WDT_STOP</name> 1480 <name>WDT</name>
1148 <position>16</position> 1481 <position>16</position>
1149 </field> 1482 </field>
1150 <field> 1483 <field>
1151 <name>OST_STOP</name> 1484 <name>OST</name>
1152 <position>15</position> 1485 <position>15</position>
1153 </field> 1486 </field>
1154 <field> 1487 <field>
1155 <name>TIMER_STOP</name> 1488 <name>TIMER</name>
1156 <position>0</position> 1489 <position>0</position>
1157 <width>8</width> 1490 <width>8</width>
1158 </field> 1491 </field>
@@ -1175,16 +1508,16 @@
1175 </instance> 1508 </instance>
1176 <register> 1509 <register>
1177 <field> 1510 <field>
1178 <name>HFLAG</name> 1511 <name>HALF</name>
1179 <position>16</position> 1512 <position>16</position>
1180 <width>8</width> 1513 <width>8</width>
1181 </field> 1514 </field>
1182 <field> 1515 <field>
1183 <name>OSTFLAG</name> 1516 <name>OST</name>
1184 <position>15</position> 1517 <position>15</position>
1185 </field> 1518 </field>
1186 <field> 1519 <field>
1187 <name>FFLAG</name> 1520 <name>FULL</name>
1188 <position>0</position> 1521 <position>0</position>
1189 <width>8</width> 1522 <width>8</width>
1190 </field> 1523 </field>
@@ -1207,16 +1540,16 @@
1207 </instance> 1540 </instance>
1208 <register> 1541 <register>
1209 <field> 1542 <field>
1210 <name>HMASK</name> 1543 <name>HALF</name>
1211 <position>16</position> 1544 <position>16</position>
1212 <width>8</width> 1545 <width>8</width>
1213 </field> 1546 </field>
1214 <field> 1547 <field>
1215 <name>OSTMASK</name> 1548 <name>OST</name>
1216 <position>15</position> 1549 <position>15</position>
1217 </field> 1550 </field>
1218 <field> 1551 <field>
1219 <name>FMASK</name> 1552 <name>FULL</name>
1220 <position>0</position> 1553 <position>0</position>
1221 <width>8</width> 1554 <width>8</width>
1222 </field> 1555 </field>
@@ -1244,7 +1577,7 @@
1244 <register> 1577 <register>
1245 <width>16</width> 1578 <width>16</width>
1246 <field> 1579 <field>
1247 <name>TDFR</name> 1580 <name>COUNT</name>
1248 <position>0</position> 1581 <position>0</position>
1249 <width>16</width> 1582 <width>16</width>
1250 </field> 1583 </field>
@@ -1264,7 +1597,7 @@
1264 <register> 1597 <register>
1265 <width>16</width> 1598 <width>16</width>
1266 <field> 1599 <field>
1267 <name>TDHR</name> 1600 <name>COUNT</name>
1268 <position>0</position> 1601 <position>0</position>
1269 <width>16</width> 1602 <width>16</width>
1270 </field> 1603 </field>
@@ -1284,7 +1617,7 @@
1284 <register> 1617 <register>
1285 <width>16</width> 1618 <width>16</width>
1286 <field> 1619 <field>
1287 <name>TCNT</name> 1620 <name>COUNT</name>
1288 <position>0</position> 1621 <position>0</position>
1289 <width>16</width> 1622 <width>16</width>
1290 </field> 1623 </field>
@@ -1304,15 +1637,23 @@
1304 <register> 1637 <register>
1305 <width>16</width> 1638 <width>16</width>
1306 <field> 1639 <field>
1307 <name>CLRZ</name> 1640 <name>CLEAR_TO_ZERO</name>
1308 <position>10</position> 1641 <position>10</position>
1309 </field> 1642 </field>
1310 <field> 1643 <field>
1311 <name>SD_ABRUPT</name> 1644 <name>SHUTDOWN</name>
1312 <position>9</position> 1645 <position>9</position>
1646 <enum>
1647 <name>GRACEFUL</name>
1648 <value>0x0</value>
1649 </enum>
1650 <enum>
1651 <name>ABRUPT</name>
1652 <value>0x1</value>
1653 </enum>
1313 </field> 1654 </field>
1314 <field> 1655 <field>
1315 <name>INITL_HIGH</name> 1656 <name>PMW_INIT_LVL</name>
1316 <position>8</position> 1657 <position>8</position>
1317 </field> 1658 </field>
1318 <field> 1659 <field>
@@ -1758,7 +2099,7 @@
1758 </register> 2099 </register>
1759 </node> 2100 </node>
1760 <node> 2101 <node>
1761 <name>FLGC</name> 2102 <name>FLAG_CLEAR</name>
1762 <instance> 2103 <instance>
1763 <name>FLGC</name> 2104 <name>FLGC</name>
1764 <range> 2105 <range>
@@ -1812,10 +2153,10 @@
1812 </register> 2153 </register>
1813 </node> 2154 </node>
1814 <node> 2155 <node>
1815 <name>FUN</name> 2156 <name>FUNCTION</name>
1816 <title>Function</title> 2157 <title>Function</title>
1817 <instance> 2158 <instance>
1818 <name>FUN</name> 2159 <name>FUNCTION</name>
1819 <range> 2160 <range>
1820 <first>0</first> 2161 <first>0</first>
1821 <count>6</count> 2162 <count>6</count>
@@ -1834,10 +2175,10 @@
1834 </register> 2175 </register>
1835 </node> 2176 </node>
1836 <node> 2177 <node>
1837 <name>SEL</name> 2178 <name>SELECT</name>
1838 <title>Select</title> 2179 <title>Select</title>
1839 <instance> 2180 <instance>
1840 <name>SEL</name> 2181 <name>SELECT</name>
1841 <range> 2182 <range>
1842 <first>0</first> 2183 <first>0</first>
1843 <count>6</count> 2184 <count>6</count>
@@ -1878,7 +2219,7 @@
1878 </register> 2219 </register>
1879 </node> 2220 </node>
1880 <node> 2221 <node>
1881 <name>TRG</name> 2222 <name>TRIGGER</name>
1882 <title>Trigger</title> 2223 <title>Trigger</title>
1883 <instance> 2224 <instance>
1884 <name>TRG</name> 2225 <name>TRG</name>
@@ -1900,7 +2241,7 @@
1900 </register> 2241 </register>
1901 </node> 2242 </node>
1902 <node> 2243 <node>
1903 <name>FLG</name> 2244 <name>FLAG</name>
1904 <title>Flag</title> 2245 <title>Flag</title>
1905 <instance> 2246 <instance>
1906 <name>FLG</name> 2247 <name>FLG</name>
@@ -4918,10 +5259,10 @@
4918 <address>0xb0070000</address> 5259 <address>0xb0070000</address>
4919 </instance> 5260 </instance>
4920 <node> 5261 <node>
4921 <name>ADENA</name> 5262 <name>ENABLE</name>
4922 <title>ADC Enable Register</title> 5263 <title>ADC Enable Register</title>
4923 <instance> 5264 <instance>
4924 <name>ADENA</name> 5265 <name>ENABLE</name>
4925 <address>0x0</address> 5266 <address>0x0</address>
4926 </instance> 5267 </instance>
4927 <register> 5268 <register>
@@ -4931,33 +5272,33 @@
4931 <position>7</position> 5272 <position>7</position>
4932 </field> 5273 </field>
4933 <field> 5274 <field>
4934 <name>SLP_MD</name> 5275 <name>SLEEP</name>
4935 <position>6</position> 5276 <position>6</position>
4936 </field> 5277 </field>
4937 <field> 5278 <field>
4938 <name>TCHEN</name> 5279 <name>TOUCH_EN</name>
4939 <position>2</position> 5280 <position>2</position>
4940 </field> 5281 </field>
4941 <field> 5282 <field>
4942 <name>VBATEN</name> 5283 <name>VBAT_EN</name>
4943 <position>1</position> 5284 <position>1</position>
4944 </field> 5285 </field>
4945 <field> 5286 <field>
4946 <name>AUXEN</name> 5287 <name>AUX_EN</name>
4947 <position>0</position> 5288 <position>0</position>
4948 </field> 5289 </field>
4949 </register> 5290 </register>
4950 </node> 5291 </node>
4951 <node> 5292 <node>
4952 <name>ADCFG</name> 5293 <name>CFG</name>
4953 <title>ADC Configure Register</title> 5294 <title>ADC Configure Register</title>
4954 <instance> 5295 <instance>
4955 <name>ADCFG</name> 5296 <name>CFG</name>
4956 <address>0x4</address> 5297 <address>0x4</address>
4957 </instance> 5298 </instance>
4958 <register> 5299 <register>
4959 <field> 5300 <field>
4960 <name>SPZZ</name> 5301 <name>SP_ZZ</name>
4961 <position>31</position> 5302 <position>31</position>
4962 </field> 5303 </field>
4963 <field> 5304 <field>
@@ -4982,7 +5323,7 @@
4982 </enum> 5323 </enum>
4983 </field> 5324 </field>
4984 <field> 5325 <field>
4985 <name>SNUM</name> 5326 <name>SAMPLE_COUNT</name>
4986 <position>10</position> 5327 <position>10</position>
4987 <width>3</width> 5328 <width>3</width>
4988 </field> 5329 </field>
@@ -4990,120 +5331,132 @@
4990 <name>CMD</name> 5331 <name>CMD</name>
4991 <position>0</position> 5332 <position>0</position>
4992 <width>2</width> 5333 <width>2</width>
5334 <enum>
5335 <name>AUX</name>
5336 <value>0x0</value>
5337 </enum>
5338 <enum>
5339 <name>AUX1</name>
5340 <value>0x1</value>
5341 </enum>
5342 <enum>
5343 <name>AUX2_VBAT</name>
5344 <value>0x2</value>
5345 </enum>
4993 </field> 5346 </field>
4994 </register> 5347 </register>
4995 </node> 5348 </node>
4996 <node> 5349 <node>
4997 <name>ADCTRL</name> 5350 <name>CTRL</name>
4998 <title>ADC Control Register</title> 5351 <title>ADC Control Register</title>
4999 <instance> 5352 <instance>
5000 <name>ADCTRL</name> 5353 <name>CTRL</name>
5001 <address>0x8</address> 5354 <address>0x8</address>
5002 </instance> 5355 </instance>
5003 <register> 5356 <register>
5004 <width>8</width> 5357 <width>8</width>
5005 <field> 5358 <field>
5006 <name>SLPENDM</name> 5359 <name>SLEEP_PEN_DOWN_MASK</name>
5007 <position>5</position> 5360 <position>5</position>
5008 </field> 5361 </field>
5009 <field> 5362 <field>
5010 <name>PENDM</name> 5363 <name>PEN_DOWN_MASK</name>
5011 <position>4</position> 5364 <position>4</position>
5012 </field> 5365 </field>
5013 <field> 5366 <field>
5014 <name>PENUM</name> 5367 <name>PEN_UP_MASK</name>
5015 <position>3</position> 5368 <position>3</position>
5016 </field> 5369 </field>
5017 <field> 5370 <field>
5018 <name>DTCHM</name> 5371 <name>TOUCH_MASK</name>
5019 <position>2</position> 5372 <position>2</position>
5020 </field> 5373 </field>
5021 <field> 5374 <field>
5022 <name>VRDYM</name> 5375 <name>VBAT_MASK</name>
5023 <position>1</position> 5376 <position>1</position>
5024 </field> 5377 </field>
5025 <field> 5378 <field>
5026 <name>ARDYM</name> 5379 <name>AUX_MASK</name>
5027 <position>0</position> 5380 <position>0</position>
5028 </field> 5381 </field>
5029 </register> 5382 </register>
5030 </node> 5383 </node>
5031 <node> 5384 <node>
5032 <name>ADSTATE</name> 5385 <name>STATUS</name>
5033 <title>ADC Status Register</title> 5386 <title>ADC Status Register</title>
5034 <instance> 5387 <instance>
5035 <name>ADSTATE</name> 5388 <name>STATUS</name>
5036 <address>0xc</address> 5389 <address>0xc</address>
5037 </instance> 5390 </instance>
5038 <register> 5391 <register>
5039 <width>8</width> 5392 <width>8</width>
5040 <field> 5393 <field>
5041 <name>SLP_RDY</name> 5394 <name>SLEEP_RDY</name>
5042 <position>7</position> 5395 <position>7</position>
5043 </field> 5396 </field>
5044 <field> 5397 <field>
5045 <name>SLPEND</name> 5398 <name>SLEEP_PEN_DOWN</name>
5046 <position>5</position> 5399 <position>5</position>
5047 </field> 5400 </field>
5048 <field> 5401 <field>
5049 <name>PEND</name> 5402 <name>PEN_DOWN</name>
5050 <position>4</position> 5403 <position>4</position>
5051 </field> 5404 </field>
5052 <field> 5405 <field>
5053 <name>PENU</name> 5406 <name>PEN_UP</name>
5054 <position>3</position> 5407 <position>3</position>
5055 </field> 5408 </field>
5056 <field> 5409 <field>
5057 <name>DTCH</name> 5410 <name>TOUCH</name>
5058 <position>2</position> 5411 <position>2</position>
5059 </field> 5412 </field>
5060 <field> 5413 <field>
5061 <name>VRDY</name> 5414 <name>VBAT</name>
5062 <position>1</position> 5415 <position>1</position>
5063 </field> 5416 </field>
5064 <field> 5417 <field>
5065 <name>ARDY</name> 5418 <name>AUX</name>
5066 <position>0</position> 5419 <position>0</position>
5067 </field> 5420 </field>
5068 </register> 5421 </register>
5069 </node> 5422 </node>
5070 <node> 5423 <node>
5071 <name>ADSAME</name> 5424 <name>SAMEPOINT</name>
5072 <title>ADC Same Point Time Register</title> 5425 <title>ADC Same Point Time Register</title>
5073 <instance> 5426 <instance>
5074 <name>ADSAME</name> 5427 <name>SAME_POINT</name>
5075 <address>0x10</address> 5428 <address>0x10</address>
5076 </instance> 5429 </instance>
5077 <register> 5430 <register>
5078 <width>16</width> 5431 <width>16</width>
5079 <field> 5432 <field>
5080 <name>SCNT</name> 5433 <name>DELAY_US</name>
5081 <position>0</position> 5434 <position>0</position>
5082 <width>16</width> 5435 <width>16</width>
5083 </field> 5436 </field>
5084 </register> 5437 </register>
5085 </node> 5438 </node>
5086 <node> 5439 <node>
5087 <name>ADWAIT</name> 5440 <name>PENWAIT</name>
5088 <title>ADC Wait Pen Down Time Register</title> 5441 <title>ADC Wait Pen Down Time Register</title>
5089 <instance> 5442 <instance>
5090 <name>ADWAIT</name> 5443 <name>PEN_WAIT</name>
5091 <address>0x14</address> 5444 <address>0x14</address>
5092 </instance> 5445 </instance>
5093 <register> 5446 <register>
5094 <width>16</width> 5447 <width>16</width>
5095 <field> 5448 <field>
5096 <name>WCNT</name> 5449 <name>DELAY_MS</name>
5097 <position>0</position> 5450 <position>0</position>
5098 <width>16</width> 5451 <width>16</width>
5099 </field> 5452 </field>
5100 </register> 5453 </register>
5101 </node> 5454 </node>
5102 <node> 5455 <node>
5103 <name>ADTCH</name> 5456 <name>TOUCH</name>
5104 <title>ADC Touch Screen Data Register</title> 5457 <title>ADC Touch Screen Data Register</title>
5105 <instance> 5458 <instance>
5106 <name>ADTCH</name> 5459 <name>TOUCH</name>
5107 <address>0x18</address> 5460 <address>0x18</address>
5108 </instance> 5461 </instance>
5109 <register> 5462 <register>
@@ -5128,23 +5481,23 @@
5128 </register> 5481 </register>
5129 </node> 5482 </node>
5130 <node> 5483 <node>
5131 <name>ADVDAT</name> 5484 <name>VBAT</name>
5132 <title>ADC VBAT Date Register</title> 5485 <title>ADC VBAT Date Register</title>
5133 <instance> 5486 <instance>
5134 <name>ADVDAT</name> 5487 <name>VBAT</name>
5135 <address>0x1c</address> 5488 <address>0x1c</address>
5136 </instance> 5489 </instance>
5137 <register> 5490 <register>
5138 <width>16</width> 5491 <width>16</width>
5139 <field> 5492 <field>
5140 <name>VDATA</name> 5493 <name>DATA</name>
5141 <position>0</position> 5494 <position>0</position>
5142 <width>12</width> 5495 <width>12</width>
5143 </field> 5496 </field>
5144 </register> 5497 </register>
5145 </node> 5498 </node>
5146 <node> 5499 <node>
5147 <name>ADADAT</name> 5500 <name>AUX</name>
5148 <title>ADC AUX Data Register</title> 5501 <title>ADC AUX Data Register</title>
5149 <instance> 5502 <instance>
5150 <name>ADADAT</name> 5503 <name>ADADAT</name>
@@ -5153,52 +5506,52 @@
5153 <register> 5506 <register>
5154 <width>16</width> 5507 <width>16</width>
5155 <field> 5508 <field>
5156 <name>ADATA</name> 5509 <name>DATA</name>
5157 <position>0</position> 5510 <position>0</position>
5158 <width>12</width> 5511 <width>12</width>
5159 </field> 5512 </field>
5160 </register> 5513 </register>
5161 </node> 5514 </node>
5162 <node> 5515 <node>
5163 <name>ADFLT</name> 5516 <name>FILTER</name>
5164 <title>ADC Filter Register</title> 5517 <title>ADC Filter Register</title>
5165 <instance> 5518 <instance>
5166 <name>ADFLT</name> 5519 <name>FILTER</name>
5167 <address>0x24</address> 5520 <address>0x24</address>
5168 </instance> 5521 </instance>
5169 <register> 5522 <register>
5170 <width>16</width> 5523 <width>16</width>
5171 <field> 5524 <field>
5172 <name>FLT_EN</name> 5525 <name>ENABLE</name>
5173 <position>15</position> 5526 <position>15</position>
5174 </field> 5527 </field>
5175 <field> 5528 <field>
5176 <name>FLT_D</name> 5529 <name>DATA</name>
5177 <position>0</position> 5530 <position>0</position>
5178 <width>12</width> 5531 <width>12</width>
5179 </field> 5532 </field>
5180 </register> 5533 </register>
5181 </node> 5534 </node>
5182 <node> 5535 <node>
5183 <name>ADCLK</name> 5536 <name>CLK</name>
5184 <title>ADC Clock Divide Register</title> 5537 <title>ADC Clock Divide Register</title>
5185 <instance> 5538 <instance>
5186 <name>ADCLK</name> 5539 <name>CLK</name>
5187 <address>0x28</address> 5540 <address>0x28</address>
5188 </instance> 5541 </instance>
5189 <register> 5542 <register>
5190 <field> 5543 <field>
5191 <name>CLKDIV_MS</name> 5544 <name>MS_DIV</name>
5192 <position>16</position> 5545 <position>16</position>
5193 <width>16</width> 5546 <width>16</width>
5194 </field> 5547 </field>
5195 <field> 5548 <field>
5196 <name>CLKDIV_US</name> 5549 <name>US_DIV</name>
5197 <position>8</position> 5550 <position>8</position>
5198 <width>8</width> 5551 <width>8</width>
5199 </field> 5552 </field>
5200 <field> 5553 <field>
5201 <name>CLKDIV</name> 5554 <name>ADC_DIV</name>
5202 <position>0</position> 5555 <position>0</position>
5203 <width>8</width> 5556 <width>8</width>
5204 </field> 5557 </field>
@@ -9980,7 +10333,7 @@
9980 </instance> 10333 </instance>
9981 <register> 10334 <register>
9982 <field> 10335 <field>
9983 <name>DWIDTH</name> 10336 <name>DATA_WIDTH</name>
9984 <position>10</position> 10337 <position>10</position>
9985 <width>3</width> 10338 <width>3</width>
9986 <enum> 10339 <enum>
@@ -10013,7 +10366,7 @@
10013 </enum> 10366 </enum>
10014 </field> 10367 </field>
10015 <field> 10368 <field>
10016 <name>CWIDTH</name> 10369 <name>CMD_WIDTH</name>
10017 <position>8</position> 10370 <position>8</position>
10018 <width>2</width> 10371 <width>2</width>
10019 <enum> 10372 <enum>
@@ -11441,27 +11794,6 @@
11441 </instance> 11794 </instance>
11442 </node> 11795 </node>
11443 <node> 11796 <node>
11444 <name>TCSM0</name>
11445 <instance>
11446 <name>TCSM0</name>
11447 <address>0xb32b0000</address>
11448 </instance>
11449 </node>
11450 <node>
11451 <name>TCSM1</name>
11452 <instance>
11453 <name>TCSM1</name>
11454 <address>0xb32c0000</address>
11455 </instance>
11456 </node>
11457 <node>
11458 <name>SRAM</name>
11459 <instance>
11460 <name>SRAM</name>
11461 <address>0xb32d0000</address>
11462 </instance>
11463 </node>
11464 <node>
11465 <name>HARB2</name> 11797 <name>HARB2</name>
11466 <title>AHB2 BUS Devices Base</title> 11798 <title>AHB2 BUS Devices Base</title>
11467 <instance> 11799 <instance>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-26 23:19:16 +0000