diff options
-rw-r--r-- | firmware/export/as3525.h | 1 | ||||
-rw-r--r-- | firmware/export/usb-s3c6400x.h | 453 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.c | 22 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 398 | ||||
-rw-r--r-- | firmware/target/arm/usb-s3c6400x.c | 44 |
5 files changed, 346 insertions, 572 deletions
diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index bad88a20e3..0d3923ce75 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h | |||
@@ -61,6 +61,7 @@ | |||
61 | 61 | ||
62 | /* AHB */ | 62 | /* AHB */ |
63 | #define USB_BASE 0xC6000000 | 63 | #define USB_BASE 0xC6000000 |
64 | #define OTGBASE USB_BASE | ||
64 | #define VIC_BASE 0xC6010000 | 65 | #define VIC_BASE 0xC6010000 |
65 | #define DMAC_BASE 0xC6020000 | 66 | #define DMAC_BASE 0xC6020000 |
66 | #define MPMC_BASE 0xC6030000 | 67 | #define MPMC_BASE 0xC6030000 |
diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index eeac9d038e..e8fb4b10a4 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h | |||
@@ -22,6 +22,22 @@ | |||
22 | #define USB_S3C6400X_H | 22 | #define USB_S3C6400X_H |
23 | 23 | ||
24 | 24 | ||
25 | /* All multi-bit fields in the driver use the following convention. | ||
26 | * If the register name is NAME, then there is one define NAME_bitp | ||
27 | * which holds the bit position and one define NAME_bits which holds | ||
28 | * a mask of the bits within the register (after shift). | ||
29 | * These macros allow easy access and construction of such fields */ | ||
30 | /* Usage: | ||
31 | * - extract(reg_name,field_name) | ||
32 | * extract a field of the register | ||
33 | * - bitm(reg_name,field_name) | ||
34 | * build a bitmask for the field | ||
35 | */ | ||
36 | #define extract(reg_name, field_name) \ | ||
37 | ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits) | ||
38 | |||
39 | #define bitm(reg_name, field_name) \ | ||
40 | (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp) | ||
25 | 41 | ||
26 | 42 | ||
27 | /*** OTG PHY CONTROL REGISTERS ***/ | 43 | /*** OTG PHY CONTROL REGISTERS ***/ |
@@ -34,35 +50,117 @@ | |||
34 | 50 | ||
35 | /*** OTG LINK CORE REGISTERS ***/ | 51 | /*** OTG LINK CORE REGISTERS ***/ |
36 | /* Core Global Registers */ | 52 | /* Core Global Registers */ |
53 | |||
54 | /** OTG Control and Status Register */ | ||
37 | #define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000))) | 55 | #define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000))) |
56 | |||
57 | /** OTG Interrupt Register */ | ||
38 | #define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004))) | 58 | #define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004))) |
59 | |||
60 | /** Core AHB Configuration Register */ | ||
39 | #define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008))) | 61 | #define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008))) |
62 | #define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ | ||
63 | #define GAHBCFG_hburstlen_bitp 1 | ||
64 | #define GAHBCFG_hburstlen_bits 0xf | ||
65 | #define GAHBCFG_INT_DMA_BURST_SINGLE 0 | ||
66 | #define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ | ||
67 | #define GAHBCFG_INT_DMA_BURST_INCR4 3 | ||
68 | #define GAHBCFG_INT_DMA_BURST_INCR8 5 | ||
69 | #define GAHBCFG_INT_DMA_BURST_INCR16 7 | ||
70 | #define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ | ||
71 | |||
72 | /** Core USB Configuration Register */ | ||
40 | #define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C))) | 73 | #define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C))) |
74 | #define GUSBCFG_toutcal_bitp 0 | ||
75 | #define GUSBCFG_toutcal_bits 0x7 | ||
76 | #define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ | ||
77 | #define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ | ||
78 | #define GUSBCFG_fsintf (1 << 5) | ||
79 | #define GUSBCFG_physel (1 << 6) | ||
80 | #define GUSBCFG_ddrsel (1 << 7) | ||
81 | #define GUSBCFG_srpcap (1 << 8) | ||
82 | #define GUSBCFG_hnpcapp (1 << 9) | ||
83 | #define GUSBCFG_usbtrdtim_bitp 10 | ||
84 | #define GUSBCFG_usbtrdtim_bits 0xf | ||
85 | #define GUSBCFG_nptxfrwnden (1 << 14) | ||
86 | #define GUSBCFG_phylpwrclksel (1 << 15) | ||
87 | #define GUSBCFG_otgutmifssel (1 << 16) | ||
88 | #define GUSBCFG_ulpi_fsls (1 << 17) | ||
89 | #define GUSBCFG_ulpi_auto_res (1 << 18) | ||
90 | #define GUSBCFG_ulpi_clk_sus_m (1 << 19) | ||
91 | #define GUSBCFG_ulpi_ext_vbus_drv (1 << 20) | ||
92 | #define GUSBCFG_ulpi_int_vbus_indicator (1 << 21) | ||
93 | #define GUSBCFG_term_sel_dl_pulse (1 << 22) | ||
94 | #define GUSBCFG_force_host_mode (1 << 29) | ||
95 | #define GUSBCFG_force_device_mode (1 << 30) | ||
96 | #define GUSBCFG_corrupt_tx_packet (1 << 31) | ||
97 | |||
98 | |||
99 | /** Core Reset Register */ | ||
41 | #define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010))) | 100 | #define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010))) |
101 | #define GRSTCTL_csftrst (1 << 0) /** Core soft reset */ | ||
102 | #define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ | ||
103 | #define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ | ||
104 | #define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
105 | #define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
106 | #define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */ | ||
107 | #define GRSTCTL_txfnum_bits 0x1f | ||
108 | #define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ | ||
109 | |||
110 | /** Core Interrupt Register */ | ||
42 | #define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014))) | 111 | #define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014))) |
112 | /* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */ | ||
113 | #define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */ | ||
114 | |||
115 | /** Core Interrupt Mask Register */ | ||
43 | #define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018))) | 116 | #define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018))) |
117 | #define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ | ||
118 | #define GINTMSK_otgintr (1 << 2) | ||
119 | #define GINTMSK_sofintr (1 << 3) | ||
120 | #define GINTMSK_rxstsqlvl (1 << 4) | ||
121 | #define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ | ||
122 | #define GINTMSK_ginnakeff (1 << 6) | ||
123 | #define GINTMSK_goutnakeff (1 << 7) | ||
124 | #define GINTMSK_i2cintr (1 << 9) | ||
125 | #define GINTMSK_erlysuspend (1 << 10) | ||
126 | #define GINTMSK_usbsuspend (1 << 11) /** USB suspend */ | ||
127 | #define GINTMSK_usbreset (1 << 12) /** USB reset */ | ||
128 | #define GINTMSK_enumdone (1 << 13) /** Enumeration done */ | ||
129 | #define GINTMSK_isooutdrop (1 << 14) | ||
130 | #define GINTMSK_eopframe (1 << 15) | ||
131 | #define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ | ||
132 | #define GINTMSK_inepintr (1 << 18) /** in pending ? */ | ||
133 | #define GINTMSK_outepintr (1 << 19) /** out pending ? */ | ||
134 | #define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ | ||
135 | #define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ | ||
136 | #define GINTMSK_portintr (1 << 24) /** Port status change ? */ | ||
137 | #define GINTMSK_hcintr (1 << 25) | ||
138 | #define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ | ||
139 | #define GINTMSK_conidstschng (1 << 28) | ||
140 | #define GINTMSK_disconnect (1 << 29) /** Disconnect */ | ||
141 | #define GINTMSK_sessreqintr (1 << 30) /** Session request */ | ||
142 | #define GINTMSK_wkupintr (1 << 31) /** Wake up */ | ||
143 | |||
144 | /** Receive Status Debug Read Register (Read Only) */ | ||
44 | #define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C))) | 145 | #define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C))) |
146 | |||
147 | /** Receive Status Read /Pop Register (Read Only) */ | ||
45 | #define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020))) | 148 | #define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020))) |
149 | |||
150 | /** Receive FIFO Size Register */ | ||
46 | #define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024))) | 151 | #define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024))) |
152 | |||
153 | /** Periodic Transmit FIFO Size Register */ | ||
47 | #define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028))) | 154 | #define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028))) |
155 | #define MAKE_FIFOSIZE_DATA(depth) ((depth) | ((depth) << 16)) | ||
156 | |||
157 | /** Non-Periodic Transmit FIFO/Queue Status Register */ | ||
48 | #define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C))) | 158 | #define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C))) |
159 | |||
160 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ | ||
161 | /* 1<=ep<=15, don't use ep=0 !!! */ | ||
49 | #define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100))) | 162 | #define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100))) |
50 | #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x)))) | 163 | #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x)))) |
51 | #define DPTXFSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x104))) | ||
52 | #define DPTXFSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x108))) | ||
53 | #define DPTXFSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x10C))) | ||
54 | #define DPTXFSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x110))) | ||
55 | #define DPTXFSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x114))) | ||
56 | #define DPTXFSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x118))) | ||
57 | #define DPTXFSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x11C))) | ||
58 | #define DPTXFSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x120))) | ||
59 | #define DPTXFSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x124))) | ||
60 | #define DPTXFSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x128))) | ||
61 | #define DPTXFSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x12C))) | ||
62 | #define DPTXFSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x130))) | ||
63 | #define DPTXFSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x134))) | ||
64 | #define DPTXFSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x138))) | ||
65 | #define DPTXFSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x13C))) | ||
66 | 164 | ||
67 | /*** HOST MODE REGISTERS ***/ | 165 | /*** HOST MODE REGISTERS ***/ |
68 | /* Host Global Registers */ | 166 | /* Host Global Registers */ |
@@ -182,162 +280,217 @@ | |||
182 | 280 | ||
183 | /*** DEVICE MODE REGISTERS ***/ | 281 | /*** DEVICE MODE REGISTERS ***/ |
184 | /* Device Global Registers */ | 282 | /* Device Global Registers */ |
283 | |||
284 | /** Device Configuration Register */ | ||
185 | #define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800))) | 285 | #define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800))) |
286 | #define DCFG_devspd_bitp 0 /** Device Speed */ | ||
287 | #define DCFG_devspd_bits 0x3 | ||
288 | #define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ | ||
289 | #define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ | ||
290 | #define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ | ||
291 | #define DCFG_devadr_bitp 4 /** Device Address */ | ||
292 | #define DCFG_devadr_bits 0x7f | ||
293 | #define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */ | ||
294 | #define DCFG_perfrint_bits 0x3 | ||
295 | #define DCFG_FRAME_INTERVAL_80 0 | ||
296 | #define DCFG_FRAME_INTERVAL_85 1 | ||
297 | #define DCFG_FRAME_INTERVAL_90 2 | ||
298 | #define DCFG_FRAME_INTERVAL_95 3 | ||
299 | |||
300 | /** Device Control Register */ | ||
186 | #define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804))) | 301 | #define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804))) |
302 | #define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ | ||
303 | #define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ | ||
304 | #define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ | ||
305 | #define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ | ||
306 | #define DCTL_tstctl_bitp 4 /** Test Control */ | ||
307 | #define DCTL_tstctl_bits 0x7 | ||
308 | #define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ | ||
309 | #define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ | ||
310 | #define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ | ||
311 | #define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ | ||
312 | #define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ | ||
313 | |||
314 | /** Device Status Register */ | ||
187 | #define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808))) | 315 | #define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808))) |
316 | #define DSTS_suspsts (1 << 0) /** Suspend status */ | ||
317 | #define DSTS_enumspd_bitp 1 /** Enumerated speed */ | ||
318 | #define DSTS_enumspd_bits 0x3 | ||
319 | #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 | ||
320 | #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 | ||
321 | #define DSTS_ENUMSPD_LS_PHY_6MHZ 2 | ||
322 | #define DSTS_ENUMSPD_FS_PHY_48MHZ 3 | ||
323 | #define DSTS_errticerr (1 << 3) /** Erratic errors ? */ | ||
324 | #define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */ | ||
325 | #define DSTS_soffn_bits 0x3fff | ||
326 | |||
327 | /** Device IN Endpoint Common Interrupt Mask Register */ | ||
188 | #define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810))) | 328 | #define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810))) |
329 | /* the following apply to DIEPMSK and DIEPINT */ | ||
330 | #define DIEPINT_xfercompl (1 << 0) /** Transfer complete */ | ||
331 | #define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | ||
332 | #define DIEPINT_ahberr (1 << 2) /** AHB error */ | ||
333 | #define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */ | ||
334 | #define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */ | ||
335 | #define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */ | ||
336 | #define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */ | ||
337 | #define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ | ||
338 | #define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ | ||
339 | |||
340 | /** Device OUT Endpoint Common Interrupt Mask Register */ | ||
189 | #define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814))) | 341 | #define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814))) |
342 | /* the following apply to DOEPMSK and DOEPINT */ | ||
343 | #define DOEPINT_xfercompl (1 << 0) /** Transfer complete */ | ||
344 | #define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | ||
345 | #define DOEPINT_ahberr (1 << 2) /** AHB error */ | ||
346 | #define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ | ||
347 | |||
348 | /** Device All Endpoints Interrupt Register */ | ||
190 | #define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818))) | 349 | #define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818))) |
350 | /* valid for DAINT and DAINTMSK, for 0<=ep<=15 */ | ||
351 | #define DAINT_IN_EP(i) (1 << (i)) | ||
352 | #define DAINT_OUT_EP(i) (1 << ((i) + 16)) | ||
353 | |||
354 | /** Device Endpoints Interrupt Mask Register */ | ||
191 | #define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C))) | 355 | #define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C))) |
356 | |||
357 | /** Device IN Token Sequence Learning Queue Read Register 1 */ | ||
192 | #define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820))) | 358 | #define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820))) |
359 | |||
360 | /** Device IN Token Sequence Learning Queue Register 2 */ | ||
193 | #define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824))) | 361 | #define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824))) |
362 | |||
363 | /* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h. | ||
364 | * the previous registers exists but has a different name :( */ | ||
365 | /** Device VBUS discharge register*/ | ||
194 | #define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828))) | 366 | #define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828))) |
367 | |||
368 | /** Device VBUS pulse register */ | ||
195 | #define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C))) | 369 | #define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C))) |
370 | |||
371 | // FIXME : 2 names for the same reg? | ||
372 | /** Device IN Token Queue Read Register 3 (RO) */ | ||
373 | /** Device Thresholding control register */ | ||
196 | #define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830))) | 374 | #define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830))) |
375 | #define DTHRCTL (*((uint32_t volatile*)(OTGBASE + 0x830))) | ||
376 | #define DTHRCTL_non_iso_thr_en (1 << 0) | ||
377 | #define DTHRCTL_iso_thr_en (1 << 1) | ||
378 | #define DTHRCTL_tx_thr_len_bitp 2 | ||
379 | #define DTHRCTL_tx_thr_len_bits 0x1FF | ||
380 | #define DTHRCTL_rx_thr_en (1 << 16) | ||
381 | #define DTHRCTL_rx_thr_len_bitp 17 | ||
382 | #define DTHRCTL_rx_thr_len_bits 0x1FF | ||
383 | |||
384 | /** Device IN Token Queue Read Register 4 (RO) */ | ||
197 | #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834))) | 385 | #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834))) |
198 | 386 | ||
199 | /* Device Logical IN Endpoint-Specific Registers */ | 387 | /* Device Logical IN Endpoint-Specific Registers */ |
200 | #define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x)))) | 388 | #define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x)))) |
201 | #define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x)))) | ||
202 | #define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x)))) | ||
203 | #define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x)))) | ||
204 | #define DIEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0x900))) | ||
205 | #define DIEPINT0 (*((uint32_t volatile*)(OTGBASE + 0x908))) | ||
206 | #define DIEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x910))) | ||
207 | #define DIEPDMA0 (*((const void* volatile*)(OTGBASE + 0x914))) | ||
208 | #define DIEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0x920))) | ||
209 | #define DIEPINT1 (*((uint32_t volatile*)(OTGBASE + 0x928))) | ||
210 | #define DIEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x930))) | ||
211 | #define DIEPDMA1 (*((const void* volatile*)(OTGBASE + 0x934))) | ||
212 | #define DIEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0x940))) | ||
213 | #define DIEPINT2 (*((uint32_t volatile*)(OTGBASE + 0x948))) | ||
214 | #define DIEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x950))) | ||
215 | #define DIEPDMA2 (*((const void* volatile*)(OTGBASE + 0x954))) | ||
216 | #define DIEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0x960))) | ||
217 | #define DIEPINT3 (*((uint32_t volatile*)(OTGBASE + 0x968))) | ||
218 | #define DIEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x970))) | ||
219 | #define DIEPDMA3 (*((const void* volatile*)(OTGBASE + 0x974))) | ||
220 | #define DIEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0x980))) | ||
221 | #define DIEPINT4 (*((uint32_t volatile*)(OTGBASE + 0x988))) | ||
222 | #define DIEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x990))) | ||
223 | #define DIEPDMA4 (*((const void* volatile*)(OTGBASE + 0x994))) | ||
224 | #define DIEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0x9A0))) | ||
225 | #define DIEPINT5 (*((uint32_t volatile*)(OTGBASE + 0x9A8))) | ||
226 | #define DIEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x9B0))) | ||
227 | #define DIEPDMA5 (*((const void* volatile*)(OTGBASE + 0x9B4))) | ||
228 | #define DIEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0x9C0))) | ||
229 | #define DIEPINT6 (*((uint32_t volatile*)(OTGBASE + 0x9C8))) | ||
230 | #define DIEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x9D0))) | ||
231 | #define DIEPDMA6 (*((const void* volatile*)(OTGBASE + 0x9D4))) | ||
232 | #define DIEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0x9E0))) | ||
233 | #define DIEPINT7 (*((uint32_t volatile*)(OTGBASE + 0x9E8))) | ||
234 | #define DIEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x9F0))) | ||
235 | #define DIEPDMA7 (*((const void* volatile*)(OTGBASE + 0x9F4))) | ||
236 | #define DIEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xA00))) | ||
237 | #define DIEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xA08))) | ||
238 | #define DIEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xA10))) | ||
239 | #define DIEPDMA8 (*((const void* volatile*)(OTGBASE + 0xA14))) | ||
240 | #define DIEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xA20))) | ||
241 | #define DIEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xA28))) | ||
242 | #define DIEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xA30))) | ||
243 | #define DIEPDMA9 (*((const void* volatile*)(OTGBASE + 0xA34))) | ||
244 | #define DIEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xA40))) | ||
245 | #define DIEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xA48))) | ||
246 | #define DIEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xA50))) | ||
247 | #define DIEPDMA10 (*((const void* volatile*)(OTGBASE + 0xA54))) | ||
248 | #define DIEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xA60))) | ||
249 | #define DIEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xA68))) | ||
250 | #define DIEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xA70))) | ||
251 | #define DIEPDMA11 (*((const void* volatile*)(OTGBASE + 0xA74))) | ||
252 | #define DIEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xA80))) | ||
253 | #define DIEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xA88))) | ||
254 | #define DIEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xA90))) | ||
255 | #define DIEPDMA12 (*((const void* volatile*)(OTGBASE + 0xA94))) | ||
256 | #define DIEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xAA0))) | ||
257 | #define DIEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xAA8))) | ||
258 | #define DIEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xAB0))) | ||
259 | #define DIEPDMA13 (*((const void* volatile*)(OTGBASE + 0xAB4))) | ||
260 | #define DIEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xAC0))) | ||
261 | #define DIEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xAC8))) | ||
262 | #define DIEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xAD0))) | ||
263 | #define DIEPDMA14 (*((const void* volatile*)(OTGBASE + 0xAD4))) | ||
264 | #define DIEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xAE0))) | ||
265 | #define DIEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xAE8))) | ||
266 | #define DIEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xAF0))) | ||
267 | #define DIEPDMA15 (*((const void* volatile*)(OTGBASE + 0xAF4))) | ||
268 | |||
269 | /* Device Logical OUT Endpoint-Specific Registers */ | 389 | /* Device Logical OUT Endpoint-Specific Registers */ |
270 | #define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x)))) | 390 | #define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x)))) |
271 | #define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x)))) | 391 | /** Maximum Packet Size |
392 | * IN/OUT EPn | ||
393 | * IN/OUT EP0 - 2 bits | ||
394 | * 2'b00: 64 Bytes | ||
395 | * 2'b01: 32 | ||
396 | * 2'b10: 16 | ||
397 | * 2'b11: 8 */ | ||
398 | #define DEPCTL_mps_bitp 0 | ||
399 | #define DEPCTL_mps_bits 0x7ff | ||
400 | #define DEPCTL_MPS_64 0 | ||
401 | #define DEPCTL_MPS_32 1 | ||
402 | #define DEPCTL_MPS_16 2 | ||
403 | #define DEPCTL_MPS_8 3 | ||
404 | /** Next Endpoint | ||
405 | * IN EPn/IN EP0 | ||
406 | * OUT EPn/OUT EP0 - reserved */ | ||
407 | #define DEPCTL_nextep_bitp 11 | ||
408 | #define DEPCTL_nextep_bits 0xf | ||
409 | #define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ | ||
410 | /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) | ||
411 | * This field contains the PID of the packet going to | ||
412 | * be received or transmitted on this endpoint. The | ||
413 | * application should program the PID of the first | ||
414 | * packet going to be received or transmitted on this | ||
415 | * endpoint , after the endpoint is | ||
416 | * activated. Application use the SetD1PID and | ||
417 | * SetD0PID fields of this register to program either | ||
418 | * D0 or D1 PID. | ||
419 | * | ||
420 | * The encoding for this field is | ||
421 | * - 0: D0 | ||
422 | * - 1: D1 | ||
423 | */ | ||
424 | #define DEPCTL_dpid (1 << 16) | ||
425 | #define DEPCTL_naksts (1 << 17) /** NAK Status */ | ||
426 | /** Endpoint Type | ||
427 | * 2'b00: Control | ||
428 | * 2'b01: Isochronous | ||
429 | * 2'b10: Bulk | ||
430 | * 2'b11: Interrupt */ | ||
431 | #define DEPCTL_eptype_bitp 18 | ||
432 | #define DEPCTL_eptype_bits 0x3 | ||
433 | /** Snoop Mode | ||
434 | * OUT EPn/OUT EP0 | ||
435 | * IN EPn/IN EP0 - reserved */ | ||
436 | #define DEPCTL_snp (1 << 20) | ||
437 | #define DEPCTL_stall (1 << 21) /** Stall Handshake */ | ||
438 | /** Tx Fifo Number | ||
439 | * IN EPn/IN EP0 | ||
440 | * OUT EPn/OUT EP0 - reserved */ | ||
441 | #define DEPCTL_txfnum_bitp 22 | ||
442 | #define DEPCTL_txfnum_bits 0xf | ||
443 | #define DEPCTL_cnak (1 << 26) /** Clear NAK */ | ||
444 | #define DEPCTL_snak (1 << 27) /** Set NAK */ | ||
445 | /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) | ||
446 | * Writing to this field sets the Endpoint DPID (DPID) | ||
447 | * field in this register to DATA0. Set Even | ||
448 | * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) | ||
449 | * Writing to this field sets the Even/Odd | ||
450 | * (micro)frame (EO_FrNum) field to even (micro) | ||
451 | * frame. | ||
452 | */ | ||
453 | #define DEPCTL_setd0pid (1 << 28) | ||
454 | /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) | ||
455 | * Writing to this field sets the Endpoint DPID (DPID) | ||
456 | * field in this register to DATA1 Set Odd | ||
457 | * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) | ||
458 | * Writing to this field sets the Even/Odd | ||
459 | * (micro)frame (EO_FrNum) field to odd (micro) frame. | ||
460 | */ | ||
461 | #define DEPCTL_setd1pid (1 << 29) | ||
462 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ | ||
463 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ | ||
464 | |||
465 | /** Device IN Endpoint (ep) Transfer Size Register */ | ||
466 | #define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x)))) | ||
467 | /** Device OUT Endpoint (ep) Transfer Size Register */ | ||
272 | #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x)))) | 468 | #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x)))) |
273 | #define DOEPDMA(x) (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x)))) | 469 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ |
274 | #define DOEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0xB00))) | 470 | #define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */ |
275 | #define DOEPINT0 (*((uint32_t volatile*)(OTGBASE + 0xB08))) | 471 | #define DEPTSIZ_xfersize_bits 0x7ffff |
276 | #define DOEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0xB10))) | 472 | #define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */ |
277 | #define DOEPDMA0 (*((void* volatile*)(OTGBASE + 0xB14))) | 473 | #define DEPTSIZ_pkcnt_bits 0x3ff |
278 | #define DOEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0xB20))) | 474 | #define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */ |
279 | #define DOEPINT1 (*((uint32_t volatile*)(OTGBASE + 0xB28))) | 475 | #define DEPTSIZ_mc_bits 0x3 |
280 | #define DOEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0xB30))) | 476 | /* idem but for i=0 */ |
281 | #define DOEPDMA1 (*((void* volatile*)(OTGBASE + 0xB34))) | 477 | #define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */ |
282 | #define DOEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0xB40))) | 478 | #define DEPTSIZ0_xfersize_bits 0x7f |
283 | #define DOEPINT2 (*((uint32_t volatile*)(OTGBASE + 0xB48))) | 479 | #define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */ |
284 | #define DOEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0xB50))) | 480 | #define DEPTSIZ0_pkcnt_bits 0x3 |
285 | #define DOEPDMA2 (*((void* volatile*)(OTGBASE + 0xB54))) | 481 | #define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ |
286 | #define DOEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0xB60))) | 482 | #define DEPTSIZ0_supcnt_bits 0x3 |
287 | #define DOEPINT3 (*((uint32_t volatile*)(OTGBASE + 0xB68))) | 483 | |
288 | #define DOEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0xB70))) | 484 | |
289 | #define DOEPDMA3 (*((void* volatile*)(OTGBASE + 0xB74))) | 485 | /** Device Endpoint (ep) Control Register */ |
290 | #define DOEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0xB80))) | 486 | #define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x)))) |
291 | #define DOEPINT4 (*((uint32_t volatile*)(OTGBASE + 0xB88))) | 487 | #define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x)))) |
292 | #define DOEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0xB90))) | 488 | |
293 | #define DOEPDMA4 (*((void* volatile*)(OTGBASE + 0xB94))) | 489 | /** Device Endpoint (ep) DMA Address Register */ |
294 | #define DOEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0xBA0))) | 490 | #define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x)))) |
295 | #define DOEPINT5 (*((uint32_t volatile*)(OTGBASE + 0xBA8))) | 491 | #define DOEPDMA(x) (*((const void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x)))) |
296 | #define DOEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0xBB0))) | ||
297 | #define DOEPDMA5 (*((void* volatile*)(OTGBASE + 0xBB4))) | ||
298 | #define DOEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0xBC0))) | ||
299 | #define DOEPINT6 (*((uint32_t volatile*)(OTGBASE + 0xBC8))) | ||
300 | #define DOEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0xBD0))) | ||
301 | #define DOEPDMA6 (*((void* volatile*)(OTGBASE + 0xBD4))) | ||
302 | #define DOEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0xBE0))) | ||
303 | #define DOEPINT7 (*((uint32_t volatile*)(OTGBASE + 0xBE8))) | ||
304 | #define DOEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0xBF0))) | ||
305 | #define DOEPDMA7 (*((void* volatile*)(OTGBASE + 0xBF4))) | ||
306 | #define DOEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xC00))) | ||
307 | #define DOEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xC08))) | ||
308 | #define DOEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xC10))) | ||
309 | #define DOEPDMA8 (*((void* volatile*)(OTGBASE + 0xC14))) | ||
310 | #define DOEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xC20))) | ||
311 | #define DOEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xC28))) | ||
312 | #define DOEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xC30))) | ||
313 | #define DOEPDMA9 (*((void* volatile*)(OTGBASE + 0xC34))) | ||
314 | #define DOEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xC40))) | ||
315 | #define DOEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xC48))) | ||
316 | #define DOEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xC50))) | ||
317 | #define DOEPDMA10 (*((void* volatile*)(OTGBASE + 0xC54))) | ||
318 | #define DOEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xC60))) | ||
319 | #define DOEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xC68))) | ||
320 | #define DOEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xC70))) | ||
321 | #define DOEPDMA11 (*((void* volatile*)(OTGBASE + 0xC74))) | ||
322 | #define DOEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xC80))) | ||
323 | #define DOEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xC88))) | ||
324 | #define DOEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xC90))) | ||
325 | #define DOEPDMA12 (*((void* volatile*)(OTGBASE + 0xC94))) | ||
326 | #define DOEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xCA0))) | ||
327 | #define DOEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xCA8))) | ||
328 | #define DOEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xCB0))) | ||
329 | #define DOEPDMA13 (*((void* volatile*)(OTGBASE + 0xCB4))) | ||
330 | #define DOEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xCC0))) | ||
331 | #define DOEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xCC8))) | ||
332 | #define DOEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xCD0))) | ||
333 | #define DOEPDMA14 (*((void* volatile*)(OTGBASE + 0xCD4))) | ||
334 | #define DOEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xCE0))) | ||
335 | #define DOEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xCE8))) | ||
336 | #define DOEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xCF0))) | ||
337 | #define DOEPDMA15 (*((void* volatile*)(OTGBASE + 0xCF4))) | ||
338 | 492 | ||
339 | /* Power and Clock Gating Register */ | 493 | /* Power and Clock Gating Register */ |
340 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) | 494 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) |
341 | 495 | ||
342 | |||
343 | #endif /* USB_S3C6400X_H */ | 496 | #endif /* USB_S3C6400X_H */ |
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index 9954484f01..1897bced64 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c | |||
@@ -36,6 +36,14 @@ | |||
36 | #include "usb-drv-as3525v2.h" | 36 | #include "usb-drv-as3525v2.h" |
37 | #include "usb_core.h" | 37 | #include "usb_core.h" |
38 | 38 | ||
39 | /* Number of IN/OUT endpoints */ | ||
40 | #define NUM_IN_EP 3 | ||
41 | #define NUM_OUT_EP 2 | ||
42 | |||
43 | /* List of IN enpoints */ | ||
44 | #define IN_EP_LIST 0, 3, 5 | ||
45 | #define OUT_EP_LIST 2, 4 | ||
46 | |||
39 | static const uint8_t in_ep_list[NUM_IN_EP + 1] = {0, IN_EP_LIST}; | 47 | static const uint8_t in_ep_list[NUM_IN_EP + 1] = {0, IN_EP_LIST}; |
40 | static const uint8_t out_ep_list[NUM_OUT_EP + 1] = {0, OUT_EP_LIST}; | 48 | static const uint8_t out_ep_list[NUM_OUT_EP + 1] = {0, OUT_EP_LIST}; |
41 | 49 | ||
@@ -216,7 +224,7 @@ static void prepare_setup_ep0(void) | |||
216 | { | 224 | { |
217 | logf("usb-drv: prepare EP0"); | 225 | logf("usb-drv: prepare EP0"); |
218 | /* setup DMA */ | 226 | /* setup DMA */ |
219 | DOEPDMA(0) = (unsigned long)AS3525_PHYSICAL_ADDR(&_ep0_setup_pkt); | 227 | DOEPDMA(0) = (void*)AS3525_PHYSICAL_ADDR(&_ep0_setup_pkt); |
220 | 228 | ||
221 | /* Setup EP0 OUT with the following parameters: | 229 | /* Setup EP0 OUT with the following parameters: |
222 | * packet count = 1 | 230 | * packet count = 1 |
@@ -408,7 +416,7 @@ static void core_dev_init(void) | |||
408 | 416 | ||
409 | /* Setup FIFOs */ | 417 | /* Setup FIFOs */ |
410 | GRXFSIZ = 512; | 418 | GRXFSIZ = 512; |
411 | GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512, 512); | 419 | GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512); |
412 | 420 | ||
413 | /* Setup interrupt masks for endpoints */ | 421 | /* Setup interrupt masks for endpoints */ |
414 | /* Setup interrupt masks */ | 422 | /* Setup interrupt masks */ |
@@ -766,9 +774,9 @@ static int usb_drv_transfer(int ep, void *ptr, int len, bool dir_in, bool blocki | |||
766 | /* disable interrupts to avoid any race */ | 774 | /* disable interrupts to avoid any race */ |
767 | int oldlevel = disable_irq_save(); | 775 | int oldlevel = disable_irq_save(); |
768 | 776 | ||
769 | volatile unsigned long *epctl = dir_in ? &DIEPCTL(ep) : &DOEPCTL(ep); | 777 | volatile uint32_t *epctl = dir_in ? &DIEPCTL(ep) : &DOEPCTL(ep); |
770 | volatile unsigned long *eptsiz = dir_in ? &DIEPTSIZ(ep) : &DOEPTSIZ(ep); | 778 | volatile uint32_t *eptsiz = dir_in ? &DIEPTSIZ(ep) : &DOEPTSIZ(ep); |
771 | volatile unsigned long *epdma = dir_in ? &DIEPDMA(ep) : &DOEPDMA(ep); | 779 | const void * volatile * epdma = dir_in ? &DIEPDMA(ep) : &DOEPDMA(ep); |
772 | struct usb_endpoint *endpoint = &endpoints[ep][dir_in]; | 780 | struct usb_endpoint *endpoint = &endpoints[ep][dir_in]; |
773 | #define DEPCTL *epctl | 781 | #define DEPCTL *epctl |
774 | #define DEPTSIZ *eptsiz | 782 | #define DEPTSIZ *eptsiz |
@@ -790,12 +798,12 @@ static int usb_drv_transfer(int ep, void *ptr, int len, bool dir_in, bool blocki | |||
790 | 798 | ||
791 | if(len == 0) | 799 | if(len == 0) |
792 | { | 800 | { |
793 | DEPDMA = 0x10000000; | 801 | DEPDMA = (void*)0x10000000; |
794 | DEPTSIZ = 1 << DEPTSIZ_pkcnt_bitp; | 802 | DEPTSIZ = 1 << DEPTSIZ_pkcnt_bitp; |
795 | } | 803 | } |
796 | else | 804 | else |
797 | { | 805 | { |
798 | DEPDMA = (unsigned long)AS3525_PHYSICAL_ADDR(ptr); | 806 | DEPDMA = (void*)AS3525_PHYSICAL_ADDR(ptr); |
799 | DEPTSIZ = (nb_packets << DEPTSIZ_pkcnt_bitp) | len; | 807 | DEPTSIZ = (nb_packets << DEPTSIZ_pkcnt_bitp) | len; |
800 | if(dir_in) | 808 | if(dir_in) |
801 | clean_dcache_range(ptr, len); | 809 | clean_dcache_range(ptr, len); |
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 8a7fee15f0..7f45f52014 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -22,149 +22,12 @@ | |||
22 | #define __USB_DRV_AS3525v2_H__ | 22 | #define __USB_DRV_AS3525v2_H__ |
23 | 23 | ||
24 | #include "as3525v2.h" | 24 | #include "as3525v2.h" |
25 | 25 | #include "usb-s3c6400x.h" | |
26 | /* All multi-bit fields in the driver use the following convention. | ||
27 | * If the register name is NAME, then there is one define NAME_bitp | ||
28 | * which holds the bit position and one define NAME_bits which holds | ||
29 | * a mask of the bits within the register (after shift). | ||
30 | * These macros allow easy access and construction of such fields */ | ||
31 | /* Usage: | ||
32 | * - extract(reg_name,field_name) | ||
33 | * extract a field of the register | ||
34 | * - bitm(reg_name,field_name) | ||
35 | * build a bitmask for the field | ||
36 | */ | ||
37 | #define extract(reg_name, field_name) \ | ||
38 | ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits) | ||
39 | |||
40 | #define bitm(reg_name, field_name) \ | ||
41 | (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp) | ||
42 | |||
43 | #define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */ | ||
44 | 26 | ||
45 | /** | 27 | /** |
46 | * Core Global Registers | 28 | * Registers not present in usb-s3c6400 |
47 | */ | 29 | */ |
48 | #define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset)) | 30 | #define BASE_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset)) |
49 | |||
50 | /** OTG Control and Status Register */ | ||
51 | #define GOTGCTL BASE_REG(0x000) | ||
52 | |||
53 | /** OTG Interrupt Register */ | ||
54 | #define GOTGINT BASE_REG(0x004) | ||
55 | |||
56 | /** Core AHB Configuration Register */ | ||
57 | #define GAHBCFG BASE_REG(0x008) | ||
58 | #define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ | ||
59 | #define GAHBCFG_hburstlen_bitp 1 | ||
60 | #define GAHBCFG_hburstlen_bits 0xf | ||
61 | #define GAHBCFG_INT_DMA_BURST_SINGLE 0 | ||
62 | #define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ | ||
63 | #define GAHBCFG_INT_DMA_BURST_INCR4 3 | ||
64 | #define GAHBCFG_INT_DMA_BURST_INCR8 5 | ||
65 | #define GAHBCFG_INT_DMA_BURST_INCR16 7 | ||
66 | #define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ | ||
67 | |||
68 | /** Core USB Configuration Register */ | ||
69 | #define GUSBCFG BASE_REG(0x00C) | ||
70 | #define GUSBCFG_toutcal_bitp 0 | ||
71 | #define GUSBCFG_toutcal_bits 0x7 | ||
72 | #define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ | ||
73 | #define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ | ||
74 | #define GUSBCFG_fsintf (1 << 5) | ||
75 | #define GUSBCFG_physel (1 << 6) | ||
76 | #define GUSBCFG_ddrsel (1 << 7) | ||
77 | #define GUSBCFG_srpcap (1 << 8) | ||
78 | #define GUSBCFG_hnpcapp (1 << 9) | ||
79 | #define GUSBCFG_usbtrdtim_bitp 10 | ||
80 | #define GUSBCFG_usbtrdtim_bits 0xf | ||
81 | #define GUSBCFG_nptxfrwnden (1 << 14) | ||
82 | #define GUSBCFG_phylpwrclksel (1 << 15) | ||
83 | #define GUSBCFG_otgutmifssel (1 << 16) | ||
84 | #define GUSBCFG_ulpi_fsls (1 << 17) | ||
85 | #define GUSBCFG_ulpi_auto_res (1 << 18) | ||
86 | #define GUSBCFG_ulpi_clk_sus_m (1 << 19) | ||
87 | #define GUSBCFG_ulpi_ext_vbus_drv (1 << 20) | ||
88 | #define GUSBCFG_ulpi_int_vbus_indicator (1 << 21) | ||
89 | #define GUSBCFG_term_sel_dl_pulse (1 << 22) | ||
90 | #define GUSBCFG_force_host_mode (1 << 29) | ||
91 | #define GUSBCFG_force_device_mode (1 << 30) | ||
92 | #define GUSBCFG_corrupt_tx_packet (1 << 31) | ||
93 | |||
94 | /** Core Reset Register */ | ||
95 | #define GRSTCTL BASE_REG(0x010) | ||
96 | #define GRSTCTL_csftrst (1 << 0) /** Core soft reset */ | ||
97 | #define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ | ||
98 | #define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ | ||
99 | #define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
100 | #define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
101 | #define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */ | ||
102 | #define GRSTCTL_txfnum_bits 0x1f | ||
103 | #define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ | ||
104 | |||
105 | /** Core Interrupt Register */ | ||
106 | #define GINTSTS BASE_REG(0x014) | ||
107 | /* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */ | ||
108 | #define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */ | ||
109 | |||
110 | /** Core Interrupt Mask Register */ | ||
111 | #define GINTMSK BASE_REG(0x018) | ||
112 | #define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ | ||
113 | #define GINTMSK_otgintr (1 << 2) | ||
114 | #define GINTMSK_sofintr (1 << 3) | ||
115 | #define GINTMSK_rxstsqlvl (1 << 4) | ||
116 | #define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ | ||
117 | #define GINTMSK_ginnakeff (1 << 6) | ||
118 | #define GINTMSK_goutnakeff (1 << 7) | ||
119 | #define GINTMSK_i2cintr (1 << 9) | ||
120 | #define GINTMSK_erlysuspend (1 << 10) | ||
121 | #define GINTMSK_usbsuspend (1 << 11) /** USB suspend */ | ||
122 | #define GINTMSK_usbreset (1 << 12) /** USB reset */ | ||
123 | #define GINTMSK_enumdone (1 << 13) /** Enumeration done */ | ||
124 | #define GINTMSK_isooutdrop (1 << 14) | ||
125 | #define GINTMSK_eopframe (1 << 15) | ||
126 | #define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ | ||
127 | #define GINTMSK_inepintr (1 << 18) /** in pending ? */ | ||
128 | #define GINTMSK_outepintr (1 << 19) /** out pending ? */ | ||
129 | #define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ | ||
130 | #define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ | ||
131 | #define GINTMSK_portintr (1 << 24) /** Port status change ? */ | ||
132 | #define GINTMSK_hcintr (1 << 25) | ||
133 | #define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ | ||
134 | #define GINTMSK_conidstschng (1 << 28) | ||
135 | #define GINTMSK_disconnect (1 << 29) /** Disconnect */ | ||
136 | #define GINTMSK_sessreqintr (1 << 30) /** Session request */ | ||
137 | #define GINTMSK_wkupintr (1 << 31) /** Wake up */ | ||
138 | |||
139 | /** Receive Status Debug Read Register (Read Only) */ | ||
140 | #define GRXSTSR BASE_REG(0x01C) | ||
141 | |||
142 | /** Receive Status Read /Pop Register (Read Only) */ | ||
143 | #define GRXSTSP BASE_REG(0x020) | ||
144 | |||
145 | /** Receive FIFO Size Register */ | ||
146 | #define GRXFSIZ BASE_REG(0x024) | ||
147 | |||
148 | /** Periodic Transmit FIFO Size Register */ | ||
149 | #define GNPTXFSIZ BASE_REG(0x028) | ||
150 | |||
151 | /** Non-Periodic Transmit FIFO/Queue Status Register */ | ||
152 | #define GNPTXSTS BASE_REG(0x02C) | ||
153 | |||
154 | /** I2C Access Register */ | ||
155 | #define GI2CCTL BASE_REG(0x030) | ||
156 | |||
157 | /** PHY Vendor Control Register */ | ||
158 | #define GPVNDCTL BASE_REG(0x034) | ||
159 | |||
160 | /** General Purpose Input/Output Register */ | ||
161 | #define GGPIO BASE_REG(0x038) | ||
162 | |||
163 | /** User ID Register */ | ||
164 | #define GUID BASE_REG(0x03C) | ||
165 | |||
166 | /** Synopsys ID Register */ | ||
167 | #define GSNPSID BASE_REG(0x040) | ||
168 | 31 | ||
169 | /** User HW Config1 Register */ | 32 | /** User HW Config1 Register */ |
170 | #define GHWCFG1 BASE_REG(0x044) | 33 | #define GHWCFG1 BASE_REG(0x044) |
@@ -203,261 +66,10 @@ | |||
203 | #define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ | 66 | #define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ |
204 | #define GHWCFG4_num_in_ep_bits 0xf | 67 | #define GHWCFG4_num_in_ep_bits 0xf |
205 | 68 | ||
206 | /* 1<=ep<=15, don't use ep=0 !!! */ | ||
207 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ | ||
208 | #define DIEPTXFSIZ(ep) BASE_REG(0x100 + 4 * (ep)) | ||
209 | |||
210 | /** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/ | ||
211 | #define MAKE_FIFOSIZE_DATA(startadr, depth) \ | ||
212 | (((startadr) & 0xffff) | ((depth) << 16)) | ||
213 | /** Retrieve fifo size for such registers */ | ||
214 | #define GET_FIFOSIZE_DEPTH(data) \ | ||
215 | ((data) >> 16) | ||
216 | /** Retrieve fifo start address for such registers */ | ||
217 | #define GET_FIFOSIZE_START_ADR(data) \ | ||
218 | ((data) & 0xffff) | ||
219 | |||
220 | /** | ||
221 | * Device Registers Base Addresses | ||
222 | */ | ||
223 | #define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset)) | ||
224 | |||
225 | /** Device Configuration Register */ | ||
226 | #define DCFG DEV_REG(0x00) | ||
227 | #define DCFG_devspd_bitp 0 /** Device Speed */ | ||
228 | #define DCFG_devspd_bits 0x3 | ||
229 | #define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ | ||
230 | #define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ | ||
231 | #define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ | ||
232 | #define DCFG_devadr_bitp 4 /** Device Address */ | ||
233 | #define DCFG_devadr_bits 0x7f | ||
234 | #define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */ | ||
235 | #define DCFG_perfrint_bits 0x3 | ||
236 | #define DCFG_FRAME_INTERVAL_80 0 | ||
237 | #define DCFG_FRAME_INTERVAL_85 1 | ||
238 | #define DCFG_FRAME_INTERVAL_90 2 | ||
239 | #define DCFG_FRAME_INTERVAL_95 3 | ||
240 | |||
241 | /** Device Control Register */ | ||
242 | #define DCTL DEV_REG(0x04) | ||
243 | #define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ | ||
244 | #define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ | ||
245 | #define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ | ||
246 | #define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ | ||
247 | #define DCTL_tstctl_bitp 4 /** Test Control */ | ||
248 | #define DCTL_tstctl_bits 0x7 | ||
249 | #define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ | ||
250 | #define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ | ||
251 | #define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ | ||
252 | #define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ | ||
253 | #define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ | ||
254 | |||
255 | /** Device Status Register */ | ||
256 | #define DSTS DEV_REG(0x08) | ||
257 | #define DSTS_suspsts (1 << 0) /** Suspend status */ | ||
258 | #define DSTS_enumspd_bitp 1 /** Enumerated speed */ | ||
259 | #define DSTS_enumspd_bits 0x3 | ||
260 | #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 | ||
261 | #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 | ||
262 | #define DSTS_ENUMSPD_LS_PHY_6MHZ 2 | ||
263 | #define DSTS_ENUMSPD_FS_PHY_48MHZ 3 | ||
264 | #define DSTS_errticerr (1 << 3) /** Erratic errors ? */ | ||
265 | #define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */ | ||
266 | #define DSTS_soffn_bits 0x3fff | ||
267 | |||
268 | /** Device IN Endpoint Common Interrupt Mask Register */ | ||
269 | #define DIEPMSK DEV_REG(0x10) | ||
270 | /* the following apply to DIEPMSK and DIEPINT */ | ||
271 | #define DIEPINT_xfercompl (1 << 0) /** Transfer complete */ | ||
272 | #define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | ||
273 | #define DIEPINT_ahberr (1 << 2) /** AHB error */ | ||
274 | #define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */ | ||
275 | #define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */ | ||
276 | #define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */ | ||
277 | #define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */ | ||
278 | #define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ | ||
279 | #define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ | ||
280 | |||
281 | /** Device OUT Endpoint Common Interrupt Mask Register */ | ||
282 | #define DOEPMSK DEV_REG(0x14) | ||
283 | /* the following apply to DOEPMSK and DOEPINT */ | ||
284 | #define DOEPINT_xfercompl (1 << 0) /** Transfer complete */ | ||
285 | #define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | ||
286 | #define DOEPINT_ahberr (1 << 2) /** AHB error */ | ||
287 | #define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ | ||
288 | |||
289 | /** Device All Endpoints Interrupt Register */ | ||
290 | #define DAINT DEV_REG(0x18) | ||
291 | /* valid for DAINT and DAINTMSK, for 0<=ep<=15 */ | ||
292 | #define DAINT_IN_EP(i) (1 << (i)) | ||
293 | #define DAINT_OUT_EP(i) (1 << ((i) + 16)) | ||
294 | |||
295 | /** Device Endpoints Interrupt Mask Register */ | ||
296 | #define DAINTMSK DEV_REG(0x1C) | ||
297 | |||
298 | /** Device IN Token Sequence Learning Queue Read Register 1 */ | ||
299 | #define DTKNQR1 DEV_REG(0x20) | ||
300 | |||
301 | /** Device IN Token Sequence Learning Queue Register 2 */ | ||
302 | #define DTKNQR2 DEV_REG(0x24) | ||
303 | |||
304 | /** Device IN Token Queue Pop register */ | ||
305 | #define DTKNQP DEV_REG(0x28) | ||
306 | |||
307 | /* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h. | ||
308 | * the previous registers exists but has a different name :( */ | ||
309 | /** Device VBUS discharge register*/ | ||
310 | #define DVBUSDIS DEV_REG(0x28) | ||
311 | |||
312 | /** Device VBUS pulse register */ | ||
313 | #define DVBUSPULSE DEV_REG(0x2C) | ||
314 | |||
315 | /** Device IN Token Queue Read Register 3 (RO) */ | ||
316 | #define DTKNQR3 DEV_REG(0x30) | ||
317 | |||
318 | /** Device Thresholding control register */ | ||
319 | #define DTHRCTL DEV_REG(0x30) | ||
320 | #define DTHRCTL_non_iso_thr_en (1 << 0) | ||
321 | #define DTHRCTL_iso_thr_en (1 << 1) | ||
322 | #define DTHRCTL_tx_thr_len_bitp 2 | ||
323 | #define DTHRCTL_tx_thr_len_bits 0x1FF | ||
324 | #define DTHRCTL_rx_thr_en (1 << 16) | ||
325 | #define DTHRCTL_rx_thr_len_bitp 17 | ||
326 | #define DTHRCTL_rx_thr_len_bits 0x1FF | ||
327 | |||
328 | /** Device IN Token Queue Read Register 4 (RO) */ | ||
329 | #define DTKNQR4 DEV_REG(0x34) | ||
330 | |||
331 | /** Device IN EPs empty Inr. Mask Register */ | ||
332 | #define FFEMPTYMSK DEV_REG(0x34) | ||
333 | |||
334 | #define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */ | ||
335 | |||
336 | /** Device IN Endpoint (ep) Control Register */ | ||
337 | #define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20) | ||
338 | /** Device OUT Endpoint (ep) Control Register */ | ||
339 | #define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20) | ||
340 | |||
341 | /** Maximum Packet Size | ||
342 | * IN/OUT EPn | ||
343 | * IN/OUT EP0 - 2 bits | ||
344 | * 2'b00: 64 Bytes | ||
345 | * 2'b01: 32 | ||
346 | * 2'b10: 16 | ||
347 | * 2'b11: 8 */ | ||
348 | #define DEPCTL_mps_bitp 0 | ||
349 | #define DEPCTL_mps_bits 0x7ff | ||
350 | #define DEPCTL_MPS_64 0 | ||
351 | #define DEPCTL_MPS_32 1 | ||
352 | #define DEPCTL_MPS_16 2 | ||
353 | #define DEPCTL_MPS_8 3 | ||
354 | /** Next Endpoint | ||
355 | * IN EPn/IN EP0 | ||
356 | * OUT EPn/OUT EP0 - reserved */ | ||
357 | #define DEPCTL_nextep_bitp 11 | ||
358 | #define DEPCTL_nextep_bits 0xf | ||
359 | #define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ | ||
360 | /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) | ||
361 | * This field contains the PID of the packet going to | ||
362 | * be received or transmitted on this endpoint. The | ||
363 | * application should program the PID of the first | ||
364 | * packet going to be received or transmitted on this | ||
365 | * endpoint , after the endpoint is | ||
366 | * activated. Application use the SetD1PID and | ||
367 | * SetD0PID fields of this register to program either | ||
368 | * D0 or D1 PID. | ||
369 | * | ||
370 | * The encoding for this field is | ||
371 | * - 0: D0 | ||
372 | * - 1: D1 | ||
373 | */ | ||
374 | #define DEPCTL_dpid (1 << 16) | ||
375 | #define DEPCTL_naksts (1 << 17) /** NAK Status */ | ||
376 | /** Endpoint Type | ||
377 | * 2'b00: Control | ||
378 | * 2'b01: Isochronous | ||
379 | * 2'b10: Bulk | ||
380 | * 2'b11: Interrupt */ | ||
381 | #define DEPCTL_eptype_bitp 18 | ||
382 | #define DEPCTL_eptype_bits 0x3 | ||
383 | /** Snoop Mode | ||
384 | * OUT EPn/OUT EP0 | ||
385 | * IN EPn/IN EP0 - reserved */ | ||
386 | #define DEPCTL_snp (1 << 20) | ||
387 | #define DEPCTL_stall (1 << 21) /** Stall Handshake */ | ||
388 | /** Tx Fifo Number | ||
389 | * IN EPn/IN EP0 | ||
390 | * OUT EPn/OUT EP0 - reserved */ | ||
391 | #define DEPCTL_txfnum_bitp 22 | ||
392 | #define DEPCTL_txfnum_bits 0xf | ||
393 | |||
394 | #define DEPCTL_cnak (1 << 26) /** Clear NAK */ | ||
395 | #define DEPCTL_snak (1 << 27) /** Set NAK */ | ||
396 | /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) | ||
397 | * Writing to this field sets the Endpoint DPID (DPID) | ||
398 | * field in this register to DATA0. Set Even | ||
399 | * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) | ||
400 | * Writing to this field sets the Even/Odd | ||
401 | * (micro)frame (EO_FrNum) field to even (micro) | ||
402 | * frame. | ||
403 | */ | ||
404 | #define DEPCTL_setd0pid (1 << 28) | ||
405 | /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) | ||
406 | * Writing to this field sets the Endpoint DPID (DPID) | ||
407 | * field in this register to DATA1 Set Odd | ||
408 | * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) | ||
409 | * Writing to this field sets the Even/Odd | ||
410 | * (micro)frame (EO_FrNum) field to odd (micro) frame. | ||
411 | */ | ||
412 | #define DEPCTL_setd1pid (1 << 29) | ||
413 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ | ||
414 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ | ||
415 | |||
416 | /** Device IN Endpoint (ep) Transfer Size Register */ | ||
417 | #define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10) | ||
418 | /** Device OUT Endpoint (ep) Transfer Size Register */ | ||
419 | #define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10) | ||
420 | |||
421 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ | ||
422 | #define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */ | ||
423 | #define DEPTSIZ_xfersize_bits 0x7ffff | ||
424 | #define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */ | ||
425 | #define DEPTSIZ_pkcnt_bits 0x3ff | ||
426 | #define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */ | ||
427 | #define DEPTSIZ_mc_bits 0x3 | ||
428 | |||
429 | /* idem but for i=0 */ | ||
430 | #define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */ | ||
431 | #define DEPTSIZ0_xfersize_bits 0x7f | ||
432 | #define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */ | ||
433 | #define DEPTSIZ0_pkcnt_bits 0x3 | ||
434 | #define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ | ||
435 | #define DEPTSIZ0_supcnt_bits 0x3 | ||
436 | |||
437 | /** Device IN Endpoint (ep) Interrupt Register */ | ||
438 | #define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8) | ||
439 | /** Device IN Endpoint (ep) DMA Address Register */ | ||
440 | #define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14) | ||
441 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ | 69 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ |
442 | #define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) | 70 | #define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x)))) |
443 | 71 | ||
444 | /** Device OUT Endpoint (ep) Frame number Register */ | 72 | /** Device OUT Endpoint (ep) Frame number Register */ |
445 | #define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4) | 73 | #define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x)))) |
446 | /** Device Endpoint (ep) Interrupt Register */ | ||
447 | #define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8) | ||
448 | /** Device Endpoint (ep) DMA Address Register */ | ||
449 | #define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14) | ||
450 | |||
451 | /** | ||
452 | * Parameters | ||
453 | */ | ||
454 | |||
455 | /* Number of IN/OUT endpoints */ | ||
456 | #define NUM_IN_EP 3 | ||
457 | #define NUM_OUT_EP 2 | ||
458 | |||
459 | /* List of IN enpoints */ | ||
460 | #define IN_EP_LIST 1, 3, 5 | ||
461 | #define OUT_EP_LIST 2, 4 | ||
462 | 74 | ||
463 | #endif /* __USB_DRV_AS3525v2_H__ */ | 75 | #endif /* __USB_DRV_AS3525v2_H__ */ |
diff --git a/firmware/target/arm/usb-s3c6400x.c b/firmware/target/arm/usb-s3c6400x.c index 4476549aa7..4bae6f10f3 100644 --- a/firmware/target/arm/usb-s3c6400x.c +++ b/firmware/target/arm/usb-s3c6400x.c | |||
@@ -78,32 +78,32 @@ static void reset_endpoints(int reinit) | |||
78 | endpoints[i].done = true; | 78 | endpoints[i].done = true; |
79 | semaphore_release(&endpoints[i].complete); | 79 | semaphore_release(&endpoints[i].complete); |
80 | } | 80 | } |
81 | DIEPCTL0 = 0x8800; /* EP0 IN ACTIVE NEXT=1 */ | 81 | DIEPCTL(0) = 0x8800; /* EP0 IN ACTIVE NEXT=1 */ |
82 | DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */ | 82 | DOEPCTL(0) = 0x8000; /* EP0 OUT ACTIVE */ |
83 | DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size: | 83 | DOEPTSIZ(0) = 0x20080040; /* EP0 OUT Transfer Size: |
84 | 64 Bytes, 1 Packet, 1 Setup Packet */ | 84 | 64 Bytes, 1 Packet, 1 Setup Packet */ |
85 | DOEPDMA0 = &ctrlreq; | 85 | DOEPDMA(0) = &ctrlreq; |
86 | DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ | 86 | DOEPCTL(0) |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ |
87 | if (reinit) | 87 | if (reinit) |
88 | { | 88 | { |
89 | /* The size is getting set to zero, because we don't know | 89 | /* The size is getting set to zero, because we don't know |
90 | whether we are Full Speed or High Speed at this stage */ | 90 | whether we are Full Speed or High Speed at this stage */ |
91 | /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */ | 91 | /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */ |
92 | DIEPCTL1 = 0x10001800; | 92 | DIEPCTL(1) = 0x10001800; |
93 | /* EP2 OUT INACTIVE DATA0 SIZE=0 */ | 93 | /* EP2 OUT INACTIVE DATA0 SIZE=0 */ |
94 | DOEPCTL2 = 0x10000000; | 94 | DOEPCTL(2) = 0x10000000; |
95 | /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */ | 95 | /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */ |
96 | DIEPCTL3 = 0x10000000; | 96 | DIEPCTL(3) = 0x10000000; |
97 | /* EP4 OUT INACTIVE DATA0 SIZE=0 */ | 97 | /* EP4 OUT INACTIVE DATA0 SIZE=0 */ |
98 | DOEPCTL4 = 0x10000000; | 98 | DOEPCTL(4) = 0x10000000; |
99 | } | 99 | } |
100 | else | 100 | else |
101 | { | 101 | { |
102 | /* INACTIVE DATA0 */ | 102 | /* INACTIVE DATA0 */ |
103 | DIEPCTL1 = (DIEPCTL1 & ~0x00008000) | 0x10000000; | 103 | DIEPCTL(1) = (DIEPCTL(1) & ~0x00008000) | 0x10000000; |
104 | DOEPCTL2 = (DOEPCTL2 & ~0x00008000) | 0x10000000; | 104 | DOEPCTL(2) = (DOEPCTL(2) & ~0x00008000) | 0x10000000; |
105 | DIEPCTL3 = (DIEPCTL3 & ~0x00008000) | 0x10000000; | 105 | DIEPCTL(3) = (DIEPCTL(3) & ~0x00008000) | 0x10000000; |
106 | DOEPCTL4 = (DOEPCTL4 & ~0x00008000) | 0x10000000; | 106 | DOEPCTL(4) = (DOEPCTL(4) & ~0x00008000) | 0x10000000; |
107 | } | 107 | } |
108 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */ | 108 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */ |
109 | } | 109 | } |
@@ -161,8 +161,8 @@ static void usb_reset(void) | |||
161 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */ | 161 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */ |
162 | while (!(GRSTCTL & 0x80000000)); /* Wait for OTG AHB master idle */ | 162 | while (!(GRSTCTL & 0x80000000)); /* Wait for OTG AHB master idle */ |
163 | 163 | ||
164 | GRXFSIZ = 0x00000200; /* RX FIFO: 512 bytes */ | 164 | GRXFSIZ = 512; /* RX FIFO: 512 bytes */ |
165 | GNPTXFSIZ = 0x02000200; /* Non-periodic TX FIFO: 512 bytes */ | 165 | GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512); /* Non-periodic TX FIFO: 512 bytes */ |
166 | GAHBCFG = SYNOPSYSOTG_AHBCFG; | 166 | GAHBCFG = SYNOPSYSOTG_AHBCFG; |
167 | GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ | 167 | GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ |
168 | 168 | ||
@@ -193,10 +193,10 @@ void INT_USB_FUNC(void) | |||
193 | { | 193 | { |
194 | /* Set up the maximum packet sizes accordingly */ | 194 | /* Set up the maximum packet sizes accordingly */ |
195 | uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64; | 195 | uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64; |
196 | DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket; | 196 | DIEPCTL(1) = (DIEPCTL(1) & ~0x000003FF) | maxpacket; |
197 | DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket; | 197 | DOEPCTL(2) = (DOEPCTL(2) & ~0x000003FF) | maxpacket; |
198 | DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket; | 198 | DIEPCTL(3) = (DIEPCTL(3) & ~0x000003FF) | maxpacket; |
199 | DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket; | 199 | DOEPCTL(4) = (DOEPCTL(4) & ~0x000003FF) | maxpacket; |
200 | } | 200 | } |
201 | 201 | ||
202 | if (ints & 0x40000) /* IN EP event */ | 202 | if (ints & 0x40000) /* IN EP event */ |
@@ -269,9 +269,9 @@ void INT_USB_FUNC(void) | |||
269 | /* Make sure EP0 OUT is set up to accept the next request */ | 269 | /* Make sure EP0 OUT is set up to accept the next request */ |
270 | if (!i) | 270 | if (!i) |
271 | { | 271 | { |
272 | DOEPTSIZ0 = 0x20080040; | 272 | DOEPTSIZ(0) = 0x20080040; |
273 | DOEPDMA0 = &ctrlreq; | 273 | DOEPDMA(0) = &ctrlreq; |
274 | DOEPCTL0 |= 0x84000000; | 274 | DOEPCTL(0) |= 0x84000000; |
275 | } | 275 | } |
276 | DOEPINT(i) = epints; | 276 | DOEPINT(i) = epints; |
277 | } | 277 | } |