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-rw-r--r--firmware/SOURCES2
-rw-r--r--firmware/target/arm/mmu-arm.S139
-rw-r--r--firmware/target/arm/mmu-armv6.S154
3 files changed, 157 insertions, 138 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 3d9539d17d..e31231c9ec 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -831,7 +831,7 @@ target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
831#ifdef GIGABEAT_S 831#ifdef GIGABEAT_S
832#ifndef SIMULATOR 832#ifndef SIMULATOR
833target/arm/lcd-as-memframe.S 833target/arm/lcd-as-memframe.S
834target/arm/mmu-arm.S 834target/arm/mmu-armv6.S
835target/arm/imx31/ccm-imx31.c 835target/arm/imx31/ccm-imx31.c
836target/arm/imx31/debug-imx31.c 836target/arm/imx31/debug-imx31.c
837target/arm/imx31/rolo_restart.S 837target/arm/imx31/rolo_restart.S
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S
index d83188b528..00e4c2b6ef 100644
--- a/firmware/target/arm/mmu-arm.S
+++ b/firmware/target/arm/mmu-arm.S
@@ -21,140 +21,8 @@
21#include "config.h" 21#include "config.h"
22#include "cpu.h" 22#include "cpu.h"
23 23
24#if CONFIG_CPU == IMX31L 24/* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */
25/* TTB routines not used */ 25/* WARNING : assume size of a data cache line == 32 bytes */
26
27/** Cache coherency **/
28
29/*
30 * Invalidate DCache for this range
31 * will do write back
32 * void invalidate_dcache_range(const void *base, unsigned int size)
33 */
34 .section .text, "ax", %progbits
35 .align 2
36 .global invalidate_dcache_range
37 .type invalidate_dcache_range, %function
38 @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
39invalidate_dcache_range:
40 add r1, r0, r1 @ size -> end
41 cmp r1, r0 @ end <= start?
42 subhi r1, r1, #1 @ round it down
43 movhi r2, #0 @
44 mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
45 mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
46 bx lr @
47 .size invalidate_dcache_range, .-invalidate_dcache_range
48
49/*
50 * clean DCache for this range
51 * forces DCache writeback for the specified range
52 * void clean_dcache_range(const void *base, unsigned int size);
53 */
54 .section .text, "ax", %progbits
55 .align 2
56 .global clean_dcache_range
57 .type clean_dcache_range, %function
58 @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
59clean_dcache_range:
60 add r1, r0, r1 @ size -> end
61 cmp r1, r0 @ end <= start?
62 subhi r1, r1, #1 @ round it down
63 movhi r2, #0 @
64 mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
65 mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
66 bx lr @
67 .size clean_dcache_range, .-clean_dcache_range
68
69/*
70 * Dump DCache for this range
71 * will *NOT* do write back except for buffer edges not on a line boundary
72 * void dump_dcache_range(const void *base, unsigned int size);
73 */
74 .section .text, "ax", %progbits
75 .align 2
76 .global dump_dcache_range
77 .type dump_dcache_range, %function
78 @ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ
79 @ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored
80 dump_dcache_range:
81 add r1, r0, r1 @ size -> end
82 cmp r1, r0 @ end <= start?
83 bxls lr @
84 tst r0, #31 @ Check first line for bits set
85 bicne r0, r0, #31 @ Clear low five bits (down)
86 mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
87 @ if not cache aligned
88 addne r0, r0, #32 @ Move to the next cache line
89 @
90 tst r1, #31 @ Check last line for bits set
91 bicne r1, r1, #31 @ Clear low five bits (down)
92 mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
93 @ if not cache aligned
94 sub r1, r1, #32 @ Move to the previous cache line
95 cmp r1, r0 @ end < start now?
96 mcrrhs p15, 0, r1, r0, c6 @ Invalidate DCache range
97 mov r0, #0 @
98 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
99 bx lr @
100 .size dump_dcache_range, .-dump_dcache_range
101
102
103/*
104 * Cleans entire DCache
105 * void clean_dcache(void);
106 */
107 .section .text, "ax", %progbits
108 .align 2
109 .global clean_dcache
110 .type clean_dcache, %function
111 .global cpucache_flush @ Alias
112clean_dcache:
113cpucache_flush:
114 mov r0, #0 @
115 mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
116 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
117 bx lr @
118 .size clean_dcache, .-clean_dcache
119
120/*
121 * Invalidate entire DCache
122 * will do writeback
123 * void invalidate_dcache(void);
124 */
125 .section .text, "ax", %progbits
126 .align 2
127 .global invalidate_dcache
128 .type invalidate_dcache, %function
129invalidate_dcache:
130 mov r0, #0 @
131 mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
132 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
133 bx lr @
134 .size invalidate_dcache, .-invalidate_dcache
135
136/*
137 * Invalidate entire ICache and DCache
138 * will do writeback
139 * void invalidate_idcache(void);
140 */
141 .section .text, "ax", %progbits
142 .align 2
143 .global invalidate_idcache
144 .type invalidate_idcache, %function
145 .global cpucache_invalidate @ Alias
146invalidate_idcache:
147cpucache_invalidate:
148 mov r0, #0 @
149 mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
150 mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire ICache
151 @ Also flushes the branch target cache
152 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
153 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
154 bx lr @
155 .size invalidate_idcache, .-invalidate_idcache
156
157#else /* !IMX31L */
158 26
159/** MMU setup **/ 27/** MMU setup **/
160 28
@@ -483,6 +351,3 @@ cpucache_invalidate:
483 mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call) 351 mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call)
484 mov pc, r1 @ 352 mov pc, r1 @
485 .size invalidate_idcache, .-invalidate_idcache 353 .size invalidate_idcache, .-invalidate_idcache
486
487#endif /* !IMX31L */
488
diff --git a/firmware/target/arm/mmu-armv6.S b/firmware/target/arm/mmu-armv6.S
new file mode 100644
index 0000000000..bb504f4884
--- /dev/null
+++ b/firmware/target/arm/mmu-armv6.S
@@ -0,0 +1,154 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006,2007 by Greg White
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include "config.h"
22#include "cpu.h"
23
24/* TTB routines not used */
25
26/** Cache coherency **/
27
28/*
29 * Invalidate DCache for this range
30 * will do write back
31 * void invalidate_dcache_range(const void *base, unsigned int size)
32 */
33 .section .text, "ax", %progbits
34 .align 2
35 .global invalidate_dcache_range
36 .type invalidate_dcache_range, %function
37 @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
38invalidate_dcache_range:
39 add r1, r0, r1 @ size -> end
40 cmp r1, r0 @ end <= start?
41 subhi r1, r1, #1 @ round it down
42 movhi r2, #0 @
43 mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
44 mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
45 bx lr @
46 .size invalidate_dcache_range, .-invalidate_dcache_range
47
48/*
49 * clean DCache for this range
50 * forces DCache writeback for the specified range
51 * void clean_dcache_range(const void *base, unsigned int size);
52 */
53 .section .text, "ax", %progbits
54 .align 2
55 .global clean_dcache_range
56 .type clean_dcache_range, %function
57 @ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
58clean_dcache_range:
59 add r1, r0, r1 @ size -> end
60 cmp r1, r0 @ end <= start?
61 subhi r1, r1, #1 @ round it down
62 movhi r2, #0 @
63 mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
64 mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
65 bx lr @
66 .size clean_dcache_range, .-clean_dcache_range
67
68/*
69 * Dump DCache for this range
70 * will *NOT* do write back except for buffer edges not on a line boundary
71 * void dump_dcache_range(const void *base, unsigned int size);
72 */
73 .section .text, "ax", %progbits
74 .align 2
75 .global dump_dcache_range
76 .type dump_dcache_range, %function
77 @ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ
78 @ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored
79 dump_dcache_range:
80 add r1, r0, r1 @ size -> end
81 cmp r1, r0 @ end <= start?
82 bxls lr @
83 tst r0, #31 @ Check first line for bits set
84 bicne r0, r0, #31 @ Clear low five bits (down)
85 mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
86 @ if not cache aligned
87 addne r0, r0, #32 @ Move to the next cache line
88 @
89 tst r1, #31 @ Check last line for bits set
90 bicne r1, r1, #31 @ Clear low five bits (down)
91 mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
92 @ if not cache aligned
93 sub r1, r1, #32 @ Move to the previous cache line
94 cmp r1, r0 @ end < start now?
95 mcrrhs p15, 0, r1, r0, c6 @ Invalidate DCache range
96 mov r0, #0 @
97 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
98 bx lr @
99 .size dump_dcache_range, .-dump_dcache_range
100
101
102/*
103 * Cleans entire DCache
104 * void clean_dcache(void);
105 */
106 .section .text, "ax", %progbits
107 .align 2
108 .global clean_dcache
109 .type clean_dcache, %function
110 .global cpucache_flush @ Alias
111clean_dcache:
112cpucache_flush:
113 mov r0, #0 @
114 mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
115 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
116 bx lr @
117 .size clean_dcache, .-clean_dcache
118
119/*
120 * Invalidate entire DCache
121 * will do writeback
122 * void invalidate_dcache(void);
123 */
124 .section .text, "ax", %progbits
125 .align 2
126 .global invalidate_dcache
127 .type invalidate_dcache, %function
128invalidate_dcache:
129 mov r0, #0 @
130 mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
131 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
132 bx lr @
133 .size invalidate_dcache, .-invalidate_dcache
134
135/*
136 * Invalidate entire ICache and DCache
137 * will do writeback
138 * void invalidate_idcache(void);
139 */
140 .section .text, "ax", %progbits
141 .align 2
142 .global invalidate_idcache
143 .type invalidate_idcache, %function
144 .global cpucache_invalidate @ Alias
145invalidate_idcache:
146cpucache_invalidate:
147 mov r0, #0 @
148 mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
149 mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire ICache
150 @ Also flushes the branch target cache
151 mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
152 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
153 bx lr @
154 .size invalidate_idcache, .-invalidate_idcache
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