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-rw-r--r--firmware/target/arm/s5l8700/usb-nano2g-6g.c37
-rw-r--r--firmware/target/arm/usb-s3c6400x.c44
2 files changed, 40 insertions, 41 deletions
diff --git a/firmware/target/arm/s5l8700/usb-nano2g-6g.c b/firmware/target/arm/s5l8700/usb-nano2g-6g.c
index 7f5d38a5ae..b070f2be3b 100644
--- a/firmware/target/arm/s5l8700/usb-nano2g-6g.c
+++ b/firmware/target/arm/s5l8700/usb-nano2g-6g.c
@@ -21,9 +21,12 @@
21 21
22#include "config.h" 22#include "config.h"
23#include "usb.h" 23#include "usb.h"
24#include "usb-s3c6400x.h"
25#include "cpu.h"
24 26
25#ifdef HAVE_USBSTACK 27#ifdef HAVE_USBSTACK
26#include "usb_core.h" 28#include "usb_core.h"
29#include "usb_drv.h"
27#include "power.h" 30#include "power.h"
28 31
29void usb_enable(bool on) 32void usb_enable(bool on)
@@ -38,6 +41,24 @@ int usb_detect(void)
38 return USB_INSERTED; 41 return USB_INSERTED;
39 return USB_EXTRACTED; 42 return USB_EXTRACTED;
40} 43}
44
45void usb_init_device(void)
46{
47 /* Power up the core clocks to allow writing
48 to some registers needed to power it down */
49 PCGCCTL = 0;
50#if CONFIG_CPU==S5L8701
51 PWRCON &= ~0x4000;
52 PWRCONEXT &= ~0x800;
53 INTMSK |= INTMSK_USB_OTG;
54#elif CONFIG_CPU==S5L8702
55 PWRCON(0) &= ~0x4;
56 PWRCON(1) &= ~0x8;
57 VIC0INTENABLE |= 1 << 19;
58#endif
59
60 usb_drv_exit();
61}
41#else 62#else
42void usb_enable(bool on) 63void usb_enable(bool on)
43{ 64{
@@ -48,4 +69,20 @@ int usb_detect(void)
48{ 69{
49 return USB_EXTRACTED; 70 return USB_EXTRACTED;
50} 71}
72
73void usb_init_device(void)
74{
75 DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
76
77 ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */
78 PCGCCTL = 1; /* Shut down PHY clock */
79 OPHYPWR = 0xF; /* PHY: Power down */
80
81#if CONFIG_CPU==S5L8701
82 PWRCON |= 0x4000;
83 PWRCONEXT |= 0x800;
84#elif CONFIG_CPU==S5L8702
85 PWRCON(0) |= 0x4;
86 PWRCON(1) |= 0x8;
87#endif
51#endif 88#endif
diff --git a/firmware/target/arm/usb-s3c6400x.c b/firmware/target/arm/usb-s3c6400x.c
index cf346f1de1..09b133d1a1 100644
--- a/firmware/target/arm/usb-s3c6400x.c
+++ b/firmware/target/arm/usb-s3c6400x.c
@@ -31,7 +31,6 @@
31 31
32#include "usb-s3c6400x.h" 32#include "usb-s3c6400x.h"
33 33
34#ifdef HAVE_USBSTACK
35#include "usb_ch9.h" 34#include "usb_ch9.h"
36#include "usb_core.h" 35#include "usb_core.h"
37#include <inttypes.h> 36#include <inttypes.h>
@@ -334,6 +333,9 @@ void usb_drv_stall(int endpoint, bool stall, bool in)
334 333
335void usb_drv_init(void) 334void usb_drv_init(void)
336{ 335{
336 for (unsigned i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
337 semaphore_init(&endpoints[i].complete, 1, 0);
338
337 /* Enable USB clock */ 339 /* Enable USB clock */
338#if CONFIG_CPU==S5L8701 340#if CONFIG_CPU==S5L8701
339 PWRCON &= ~0x4000; 341 PWRCON &= ~0x4000;
@@ -369,47 +371,7 @@ void usb_drv_exit(void)
369#endif 371#endif
370} 372}
371 373
372void usb_init_device(void)
373{
374 for (unsigned i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
375 semaphore_init(&endpoints[i].complete, 1, 0);
376
377 /* Power up the core clocks to allow writing
378 to some registers needed to power it down */
379 PCGCCTL = 0;
380#if CONFIG_CPU==S5L8701
381 PWRCON &= ~0x4000;
382 PWRCONEXT &= ~0x800;
383 INTMSK |= INTMSK_USB_OTG;
384#elif CONFIG_CPU==S5L8702
385 PWRCON(0) &= ~0x4;
386 PWRCON(1) &= ~0x8;
387 VIC0INTENABLE |= 1 << 19;
388#endif
389
390 usb_drv_exit();
391}
392
393void usb_attach(void) 374void usb_attach(void)
394{ 375{
395 usb_enable(true); 376 usb_enable(true);
396} 377}
397
398#else
399void usb_init_device(void)
400{
401 DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
402
403 ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */
404 PCGCCTL = 1; /* Shut down PHY clock */
405 OPHYPWR = 0xF; /* PHY: Power down */
406
407#if CONFIG_CPU==S5L8701
408 PWRCON |= 0x4000;
409 PWRCONEXT |= 0x800;
410#elif CONFIG_CPU==S5L8702
411 PWRCON(0) |= 0x4;
412 PWRCON(1) |= 0x8;
413#endif
414}
415#endif