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-rw-r--r--firmware/export/mcf5250.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/firmware/export/mcf5250.h b/firmware/export/mcf5250.h
index f47e61d89c..a5d3ae8e35 100644
--- a/firmware/export/mcf5250.h
+++ b/firmware/export/mcf5250.h
@@ -36,17 +36,6 @@
36#undef IPERRORADR 36#undef IPERRORADR
37 37
38/* here we define some new stuff */ 38/* here we define some new stuff */
39#define IPR (*(volatile unsigned long *)(MBAR + 0x040)) /* interrupt oending register */
40#define IMR (*(volatile unsigned long *)(MBAR + 0x044)) /* Interrupt Mask Register */
41
42#define ICR1 (*(volatile unsigned long *)(MBAR + 0x04d)) /* Primary interrupt control reg: timer 0 */
43#define ICR2 (*(volatile unsigned long *)(MBAR + 0x04e)) /* Primary interrupt control reg: timer 1 */
44#define ICR3 (*(volatile unsigned long *)(MBAR + 0x04f)) /* Primary interrupt control reg: i2c0 */
45#define ICR5 (*(volatile unsigned long *)(MBAR + 0x051)) /* Primary interrupt control reg: uart1 */
46#define ICR6 (*(volatile unsigned long *)(MBAR + 0x052)) /* Primary interrupt control reg: dma0 */
47#define ICR7 (*(volatile unsigned long *)(MBAR + 0x053)) /* Primary interrupt control reg: dam1 */
48#define ICR9 (*(volatile unsigned long *)(MBAR + 0x055)) /* Primary interrupt control reg: dam3 */
49#define ICR10 (*(volatile unsigned long *)(MBAR + 0x056)) /* Primary interrupt control reg: qspi */
50 39
51#define CSAR4 (*(volatile unsigned long *)(MBAR + 0x0b0)) /* Chip Select Address Register Bank 4 */ 40#define CSAR4 (*(volatile unsigned long *)(MBAR + 0x0b0)) /* Chip Select Address Register Bank 4 */
52#define CSMR4 (*(volatile unsigned long *)(MBAR + 0x0b4)) /* Chip Select Mask Register Bank 4 */ 41#define CSMR4 (*(volatile unsigned long *)(MBAR + 0x0b4)) /* Chip Select Mask Register Bank 4 */