diff options
| -rw-r--r-- | firmware/target/arm/as3525/ascodec-as3525.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/ascodec-as3525.c b/firmware/target/arm/as3525/ascodec-as3525.c index 43a982f454..b9790217aa 100644 --- a/firmware/target/arm/as3525/ascodec-as3525.c +++ b/firmware/target/arm/as3525/ascodec-as3525.c | |||
| @@ -27,7 +27,14 @@ | |||
| 27 | 27 | ||
| 28 | I2C register description: | 28 | I2C register description: |
| 29 | * I2C2_CNTRL needs to be set to 0x51 for transfers to work at all. | 29 | * I2C2_CNTRL needs to be set to 0x51 for transfers to work at all. |
| 30 | bit 1 indicates direction of transfer (0 = write, 1 = read) | 30 | bit 0: ? possibly related to using ACKs during transfers |
| 31 | bit 1: direction of transfer (0 = write, 1 = read) | ||
| 32 | bit 2: use 2-byte slave address | ||
| 33 | * I2C2_IMR, I2C2_RIS, I2C2_MIS, I2C2_INT_CLR interrupt bits: | ||
| 34 | bit 2: byte read interrupt | ||
| 35 | bit 3: byte write interrupt | ||
| 36 | bit 4: ? possibly some kind of error status | ||
| 37 | bit 7: ACK error | ||
| 31 | * I2C2_SR (status register) indicates in bit 0 if a transfer is busy. | 38 | * I2C2_SR (status register) indicates in bit 0 if a transfer is busy. |
| 32 | * I2C2_SLAD0 contains the i2c slave address to read from / write to. | 39 | * I2C2_SLAD0 contains the i2c slave address to read from / write to. |
| 33 | * I2C2_CPSR0/1 is the divider from the peripheral clock to the i2c clock. | 40 | * I2C2_CPSR0/1 is the divider from the peripheral clock to the i2c clock. |