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-rw-r--r--firmware/target/arm/as3525/sd-as3525v2.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c
index 059687acce..0a5df23e28 100644
--- a/firmware/target/arm/as3525/sd-as3525v2.c
+++ b/firmware/target/arm/as3525/sd-as3525v2.c
@@ -628,41 +628,41 @@ static void init_controller(void)
628 int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1; 628 int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
629 int card_mask = (1 << hcon_numcards) - 1; 629 int card_mask = (1 << hcon_numcards) - 1;
630 630
631 MCI_PWREN &= ~card_mask; /* power off all cards */ 631 MCI_PWREN &= ~card_mask; /* power off all cards */
632 632
633 MCI_CLKSRC = 0x00; /* All CLK_SRC_CRD set to 0*/ 633 MCI_CLKSRC = 0x00; /* All CLK_SRC_CRD set to 0*/
634 MCI_CLKDIV = 0x00; /* CLK_DIV_0 : bits 7:0 */ 634 MCI_CLKDIV = 0x00; /* CLK_DIV_0 : bits 7:0 */
635 635
636 MCI_PWREN |= card_mask; /* power up cards */ 636 MCI_PWREN |= card_mask; /* power up cards */
637 mci_delay(); 637 mci_delay();
638 638
639 MCI_CTRL |= CTRL_RESET; 639 MCI_CTRL |= CTRL_RESET;
640 while(MCI_CTRL & CTRL_RESET) 640 while(MCI_CTRL & CTRL_RESET)
641 ; 641 ;
642 642
643 MCI_RAW_STATUS = 0xffffffff; 643 MCI_RAW_STATUS = 0xffffffff; /* Clear all MCI Interrupts */
644 644
645 MCI_TMOUT = 0xffffffff; /* data b31:8, response b7:0 */ 645 MCI_TMOUT = 0xffffffff; /* data b31:8, response b7:0 */
646 646
647 MCI_CTYPE = 0x0; /* all cards 1 bit bus for now */ 647 MCI_CTYPE = 0x0; /* all cards 1 bit bus for now */
648 648
649 MCI_CLKENA = card_mask; 649 MCI_CLKENA = card_mask; /* Enables card clocks */
650 650
651 MCI_ARGUMENT = 0; 651 MCI_ARGUMENT = 0;
652 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT; 652 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
653 while(MCI_COMMAND & CMD_DONE_BIT) 653 while(MCI_COMMAND & CMD_DONE_BIT)
654 ; 654 ;
655 655
656 MCI_DEBNCE = 0xfffff; /* default value */ 656 MCI_DEBNCE = 0xfffff; /* default value */
657 657
658 /* Rx watermark = 63(sd reads) Tx watermark = 128 (sd writes) */ 658 /* Rx watermark = 63(sd reads) Tx watermark = 128 (sd writes) */
659 MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080; 659 MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
660 660
661 GPIOB_DIR |= (1<<5); /* Set pin B5 to output */
662
661 /* Mask all MCI Interrupts initially */ 663 /* Mask all MCI Interrupts initially */
662 MCI_MASK = 0; 664 MCI_MASK = 0;
663 665
664 GPIOB_DIR |= (1<<5); /* Pin B5 output */
665
666 MCI_CTRL |= INT_ENABLE; 666 MCI_CTRL |= INT_ENABLE;
667} 667}
668 668