diff options
-rw-r--r-- | firmware/SOURCES | 10 | ||||
-rw-r--r-- | firmware/app.lds | 10 | ||||
-rw-r--r-- | firmware/boot.lds | 10 | ||||
-rw-r--r-- | firmware/rom.lds | 11 | ||||
-rw-r--r-- | firmware/target/arm/crt0-pp.S | 375 | ||||
-rw-r--r-- | firmware/target/arm/crt0.S | 232 | ||||
-rw-r--r-- | firmware/target/coldfire/crt0.S | 260 | ||||
-rw-r--r-- | firmware/target/sh/crt0.S | 214 |
8 files changed, 1116 insertions, 6 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 07b8355662..9001535150 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -178,7 +178,17 @@ kernel.c | |||
178 | rolo.c | 178 | rolo.c |
179 | thread.c | 179 | thread.c |
180 | timer.c | 180 | timer.c |
181 | #ifdef CPU_PP | ||
182 | target/arm/crt0-pp.S | ||
183 | #elif defined(CPU_ARM) | ||
184 | target/arm/crt0.S | ||
185 | #elif defined(CPU_COLDFIRE) | ||
186 | target/coldfire/crt0.S | ||
187 | #elif CONFIG_CPU == SH7034 | ||
188 | target/sh/crt0.S | ||
189 | #else | ||
181 | crt0.S | 190 | crt0.S |
191 | #endif | ||
182 | drivers/lcd.S | 192 | drivers/lcd.S |
183 | #endif | 193 | #endif |
184 | mp3_playback.c | 194 | mp3_playback.c |
diff --git a/firmware/app.lds b/firmware/app.lds index 3ceb8543a9..173573b602 100644 --- a/firmware/app.lds +++ b/firmware/app.lds | |||
@@ -3,17 +3,21 @@ | |||
3 | ENTRY(start) | 3 | ENTRY(start) |
4 | #ifdef CPU_COLDFIRE | 4 | #ifdef CPU_COLDFIRE |
5 | OUTPUT_FORMAT(elf32-m68k) | 5 | OUTPUT_FORMAT(elf32-m68k) |
6 | INPUT(crt0.o) | 6 | INPUT(target/coldfire/crt0.o) |
7 | #elif CONFIG_CPU == TCC730 | 7 | #elif CONFIG_CPU == TCC730 |
8 | OUTPUT_FORMAT(elf32-calmrisc16) | 8 | OUTPUT_FORMAT(elf32-calmrisc16) |
9 | INPUT(crt0.o) | 9 | INPUT(crt0.o) |
10 | #elif defined(CPU_ARM) | 10 | #elif defined(CPU_ARM) |
11 | OUTPUT_FORMAT(elf32-littlearm) | 11 | OUTPUT_FORMAT(elf32-littlearm) |
12 | OUTPUT_ARCH(arm) | 12 | OUTPUT_ARCH(arm) |
13 | INPUT(crt0.o) | 13 | #ifdef CPU_PP |
14 | INPUT(target/arm/crt0-pp.o) | ||
15 | #elif defined(CPU_ARM) | ||
16 | INPUT(target/arm/crt0.o) | ||
17 | #endif | ||
14 | #else | 18 | #else |
15 | OUTPUT_FORMAT(elf32-sh) | 19 | OUTPUT_FORMAT(elf32-sh) |
16 | INPUT(crt0.o) | 20 | INPUT(target/sh/crt0.o) |
17 | #endif | 21 | #endif |
18 | 22 | ||
19 | #if CONFIG_CPU == TCC730 | 23 | #if CONFIG_CPU == TCC730 |
diff --git a/firmware/boot.lds b/firmware/boot.lds index 56383d7723..f361e45e9e 100644 --- a/firmware/boot.lds +++ b/firmware/boot.lds | |||
@@ -3,18 +3,22 @@ | |||
3 | ENTRY(start) | 3 | ENTRY(start) |
4 | #ifdef CPU_COLDFIRE | 4 | #ifdef CPU_COLDFIRE |
5 | OUTPUT_FORMAT(elf32-m68k) | 5 | OUTPUT_FORMAT(elf32-m68k) |
6 | INPUT(crt0.o) | 6 | INPUT(target/coldfire/crt0.o) |
7 | #elif defined (CPU_ARM) | 7 | #elif defined (CPU_ARM) |
8 | OUTPUT_FORMAT(elf32-littlearm) | 8 | OUTPUT_FORMAT(elf32-littlearm) |
9 | OUTPUT_ARCH(arm) | 9 | OUTPUT_ARCH(arm) |
10 | #ifndef IPOD_ARCH | 10 | #ifndef IPOD_ARCH |
11 | /* the ipods can't have the crt0.o mentioned here, but the others can't do | 11 | /* the ipods can't have the crt0.o mentioned here, but the others can't do |
12 | without it! */ | 12 | without it! */ |
13 | INPUT(crt0.o) | 13 | #ifdef CPU_PP |
14 | INPUT(target/arm/crt0-pp.o) | ||
15 | #else | ||
16 | INPUT(target/arm/crt0.o) | ||
17 | #endif | ||
14 | #endif | 18 | #endif |
15 | #else | 19 | #else |
16 | OUTPUT_FORMAT(elf32-sh) | 20 | OUTPUT_FORMAT(elf32-sh) |
17 | INPUT(crt0.o) | 21 | INPUT(target/sh/crt0.o) |
18 | #endif | 22 | #endif |
19 | 23 | ||
20 | #define DRAMSIZE (MEMORYSIZE * 0x100000) | 24 | #define DRAMSIZE (MEMORYSIZE * 0x100000) |
diff --git a/firmware/rom.lds b/firmware/rom.lds index 7e178ae2b2..29e72d70c0 100644 --- a/firmware/rom.lds +++ b/firmware/rom.lds | |||
@@ -6,7 +6,18 @@ OUTPUT_FORMAT(elf32-m68k) | |||
6 | #else | 6 | #else |
7 | OUTPUT_FORMAT(elf32-sh) | 7 | OUTPUT_FORMAT(elf32-sh) |
8 | #endif | 8 | #endif |
9 | #ifdef CPU_COLDFIRE | ||
10 | INPUT(target/coldfire/crt0.o) | ||
11 | #elif defined(CPU_PP) | ||
12 | INPUT(target/arm/crt0-pp.o) | ||
13 | #elif defined(CPU_ARM) | ||
14 | INPUT(target/arm/crt0.o) | ||
15 | #elif CONFIG_CPU == SH7034 | ||
16 | INPUT(target/sh/crt0.o) | ||
17 | #else | ||
9 | INPUT(crt0.o) | 18 | INPUT(crt0.o) |
19 | #endif | ||
20 | |||
10 | 21 | ||
11 | #if MEMORYSIZE >= 32 | 22 | #if MEMORYSIZE >= 32 |
12 | #define PLUGINSIZE 0xC0000 | 23 | #define PLUGINSIZE 0xC0000 |
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S new file mode 100644 index 0000000000..d847d9d943 --- /dev/null +++ b/firmware/target/arm/crt0-pp.S | |||
@@ -0,0 +1,375 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | |||
22 | .section .init.text,"ax",%progbits | ||
23 | |||
24 | .global start | ||
25 | start: | ||
26 | |||
27 | /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux | ||
28 | * loader | ||
29 | * | ||
30 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
31 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
32 | * | ||
33 | */ | ||
34 | #if CONFIG_CPU == PP5002 | ||
35 | .equ PROC_ID, 0xc4000000 | ||
36 | .equ COP_CTRL, 0xcf004058 | ||
37 | .equ COP_STATUS, 0xcf004050 | ||
38 | .equ IIS_CONFIG, 0xc0002500 | ||
39 | .equ SLEEP, 0xca | ||
40 | .equ WAKE, 0xce | ||
41 | .equ SLEEPING, 0x4000 | ||
42 | #else | ||
43 | .equ PROC_ID, 0x60000000 | ||
44 | .equ COP_CTRL, 0x60007004 | ||
45 | .equ COP_STATUS, 0x60007004 | ||
46 | .equ IIS_CONFIG, 0x70002800 | ||
47 | .equ SLEEP, 0x80000000 | ||
48 | .equ WAKE, 0x0 | ||
49 | .equ SLEEPING, 0x80000000 | ||
50 | #endif | ||
51 | |||
52 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
53 | |||
54 | #ifndef BOOTLOADER | ||
55 | b pad_skip | ||
56 | .space 50*4 /* (more than enough) space for exception vectors */ | ||
57 | pad_skip: | ||
58 | /* We need to remap memory from wherever SDRAM is mapped natively, to | ||
59 | base address 0, so we can put our exception vectors there. We don't | ||
60 | want to do this remapping while executing from SDRAM, so we copy the | ||
61 | remapping code to IRAM, then execute from there. Hence, the following | ||
62 | code is compiled for address 0, but is currently executing at either | ||
63 | 0x28000000 or 0x10000000, depending on chipset version. Do not use any | ||
64 | absolute addresses until remapping has been done. */ | ||
65 | ldr r1, =0x40000000 | ||
66 | ldr r2, =remap_start | ||
67 | ldr r3, =remap_end | ||
68 | |||
69 | and r5, pc, #0xff000000 /* adjust for execute address */ | ||
70 | orr r2, r2, r5 | ||
71 | orr r3, r3, r5 | ||
72 | |||
73 | /* copy the code to 0x40000000 */ | ||
74 | 1: | ||
75 | ldr r4, [r2], #4 | ||
76 | str r4, [r1], #4 | ||
77 | cmp r2, r3 | ||
78 | ble 1b | ||
79 | |||
80 | ldr r3, =0x3f84 /* r3 and r1 values here are magic, don't touch */ | ||
81 | orr r3, r3, r5 /* adjust for execute address */ | ||
82 | ldr r2, =0xf000f014 | ||
83 | mov r1, #0x3a00 | ||
84 | ldr r0, =0xf000f010 | ||
85 | mov pc, #0x40000000 | ||
86 | |||
87 | remap_start: | ||
88 | str r1, [r0] | ||
89 | str r3, [r2] | ||
90 | ldr r0, L_post_remap | ||
91 | mov pc, r0 | ||
92 | L_post_remap: .word remap_end | ||
93 | remap_end: | ||
94 | |||
95 | /* After doing the remapping, send the COP to sleep. | ||
96 | On wakeup it will go to cop_init */ | ||
97 | ldr r0, =PROC_ID | ||
98 | ldr r0, [r0] | ||
99 | and r0, r0, #0xff | ||
100 | cmp r0, #0x55 | ||
101 | beq 1f | ||
102 | |||
103 | /* put us (co-processor) to sleep */ | ||
104 | ldr r4, =COP_CTRL | ||
105 | mov r3, #SLEEP | ||
106 | str r3, [r4] | ||
107 | |||
108 | ldr pc, =cop_init | ||
109 | |||
110 | 1: | ||
111 | |||
112 | #ifndef DEBUG | ||
113 | /* Copy exception handler code to address 0 */ | ||
114 | ldr r2, =_vectorsstart | ||
115 | ldr r3, =_vectorsend | ||
116 | ldr r4, =_vectorscopy | ||
117 | 1: | ||
118 | cmp r3, r2 | ||
119 | ldrhi r5, [r4], #4 | ||
120 | strhi r5, [r2], #4 | ||
121 | bhi 1b | ||
122 | #else | ||
123 | ldr r1, =vectors | ||
124 | ldr r0, =irq_handler | ||
125 | str r0, [r1, #24] | ||
126 | ldr r0, =fiq_handler | ||
127 | str r0, [r1, #28] | ||
128 | #endif | ||
129 | |||
130 | #ifndef STUB | ||
131 | /* Zero out IBSS */ | ||
132 | ldr r2, =_iedata | ||
133 | ldr r3, =_iend | ||
134 | mov r4, #0 | ||
135 | 1: | ||
136 | cmp r3, r2 | ||
137 | strhi r4, [r2], #4 | ||
138 | bhi 1b | ||
139 | |||
140 | /* Copy the IRAM */ | ||
141 | ldr r2, =_iramcopy | ||
142 | ldr r3, =_iramstart | ||
143 | ldr r4, =_iramend | ||
144 | 1: | ||
145 | cmp r4, r3 | ||
146 | ldrhi r5, [r2], #4 | ||
147 | strhi r5, [r3], #4 | ||
148 | bhi 1b | ||
149 | #endif /* !STUB */ | ||
150 | #endif /* !BOOTLOADER */ | ||
151 | |||
152 | /* Initialise bss section to zero */ | ||
153 | ldr r2, =_edata | ||
154 | ldr r3, =_end | ||
155 | mov r4, #0 | ||
156 | 1: | ||
157 | cmp r3, r2 | ||
158 | strhi r4, [r2], #4 | ||
159 | bhi 1b | ||
160 | |||
161 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
162 | ldr sp, =stackend | ||
163 | mov r3, sp | ||
164 | ldr r2, =stackbegin | ||
165 | ldr r4, =0xdeadbeef | ||
166 | 1: | ||
167 | cmp r3, r2 | ||
168 | strhi r4, [r2], #4 | ||
169 | bhi 1b | ||
170 | |||
171 | #ifdef BOOTLOADER | ||
172 | /* TODO: the high part of the address is probably dependent on CONFIG_CPU. | ||
173 | Since we tend to use ifdefs for each chipset target | ||
174 | anyway, we might as well just hardcode it here. | ||
175 | */ | ||
176 | |||
177 | /* get the high part of our execute address */ | ||
178 | ldr r0, =0xff000000 | ||
179 | and r8, pc, r0 @ r8 is used later | ||
180 | |||
181 | /* Find out which processor we are */ | ||
182 | mov r0, #PROC_ID | ||
183 | ldr r0, [r0] | ||
184 | and r0, r0, #0xff | ||
185 | cmp r0, #0x55 | ||
186 | beq 1f | ||
187 | |||
188 | /* put us (co-processor) to sleep */ | ||
189 | ldr r4, =COP_CTRL | ||
190 | mov r3, #SLEEP | ||
191 | str r3, [r4] | ||
192 | ldr pc, =cop_wake_start | ||
193 | |||
194 | cop_wake_start: | ||
195 | /* jump the COP to startup */ | ||
196 | ldr r0, =startup_loc | ||
197 | ldr pc, [r0] | ||
198 | |||
199 | 1: | ||
200 | |||
201 | /* get the high part of our execute address */ | ||
202 | ldr r2, =0xffffff00 | ||
203 | and r4, pc, r2 | ||
204 | |||
205 | /* Copy bootloader to safe area - 0x40000000 */ | ||
206 | mov r5, #0x40000000 | ||
207 | ldr r6, = _dataend | ||
208 | sub r0, r6, r5 /* length of loader */ | ||
209 | add r0, r4, r0 /* r0 points to start of loader */ | ||
210 | 1: | ||
211 | cmp r5, r6 | ||
212 | ldrcc r2, [r4], #4 | ||
213 | strcc r2, [r5], #4 | ||
214 | bcc 1b | ||
215 | |||
216 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
217 | |||
218 | start_loc: | ||
219 | |||
220 | /* execute the loader - this will load an image to 0x10000000 */ | ||
221 | bl main | ||
222 | |||
223 | /* Wake up the coprocessor before executing the firmware */ | ||
224 | |||
225 | /* save the startup address for the COP */ | ||
226 | ldr r1, =startup_loc | ||
227 | str r0, [r1] | ||
228 | |||
229 | /* make sure COP is sleeping */ | ||
230 | ldr r4, =COP_STATUS | ||
231 | 1: | ||
232 | ldr r3, [r4] | ||
233 | ands r3, r3, #SLEEPING | ||
234 | beq 1b | ||
235 | |||
236 | /* wake up COP */ | ||
237 | ldr r4, =COP_CTRL | ||
238 | mov r3, #WAKE | ||
239 | str r3, [r4] | ||
240 | |||
241 | /* jump to start location */ | ||
242 | mov pc, r0 | ||
243 | |||
244 | startup_loc: | ||
245 | .word 0x0 | ||
246 | |||
247 | .align 8 /* starts at 0x100 */ | ||
248 | .global boot_table | ||
249 | boot_table: | ||
250 | /* here comes the boot table, don't move its offset */ | ||
251 | .space 400 | ||
252 | |||
253 | #else /* BOOTLOADER */ | ||
254 | |||
255 | /* Set up stack for IRQ mode */ | ||
256 | msr cpsr_c, #0xd2 | ||
257 | ldr sp, =irq_stack | ||
258 | /* Set up stack for FIQ mode */ | ||
259 | msr cpsr_c, #0xd1 | ||
260 | ldr sp, =fiq_stack | ||
261 | /* We'll load the banked FIQ mode registers with useful values here. | ||
262 | These values will be used in the FIQ handler in pcm_playback.c */ | ||
263 | ldr r12, =IIS_CONFIG | ||
264 | |||
265 | ldr r11, =p | ||
266 | |||
267 | /* Let abort and undefined modes use IRQ stack */ | ||
268 | msr cpsr_c, #0xd7 | ||
269 | ldr sp, =irq_stack | ||
270 | msr cpsr_c, #0xdb | ||
271 | ldr sp, =irq_stack | ||
272 | /* Switch to supervisor mode */ | ||
273 | msr cpsr_c, #0xd3 | ||
274 | ldr sp, =stackend | ||
275 | bl main | ||
276 | /* main() should never return */ | ||
277 | |||
278 | cop_init: | ||
279 | ldr sp, =cop_stackend | ||
280 | mov r3, sp | ||
281 | ldr r2, =cop_stackbegin | ||
282 | ldr r4, =0xdeadbeef | ||
283 | 2: | ||
284 | cmp r3, r2 | ||
285 | strhi r4, [r2], #4 | ||
286 | bhi 2b | ||
287 | |||
288 | ldr sp, =cop_stackend | ||
289 | bl cop_main | ||
290 | |||
291 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | ||
292 | .section .vectors,"aw" | ||
293 | ldr pc, [pc, #24] | ||
294 | ldr pc, [pc, #24] | ||
295 | ldr pc, [pc, #24] | ||
296 | ldr pc, [pc, #24] | ||
297 | ldr pc, [pc, #24] | ||
298 | ldr pc, [pc, #24] | ||
299 | ldr pc, [pc, #24] | ||
300 | ldr pc, [pc, #24] | ||
301 | |||
302 | /* Exception vectors */ | ||
303 | .global vectors | ||
304 | vectors: | ||
305 | .word start | ||
306 | .word undef_instr_handler | ||
307 | .word software_int_handler | ||
308 | .word prefetch_abort_handler | ||
309 | .word data_abort_handler | ||
310 | .word reserved_handler | ||
311 | .word irq_handler | ||
312 | .word fiq_handler | ||
313 | |||
314 | .text | ||
315 | |||
316 | #ifndef STUB | ||
317 | .global irq | ||
318 | .global fiq | ||
319 | .global UIE | ||
320 | #endif | ||
321 | |||
322 | /* All illegal exceptions call into UIE with exception address as first | ||
323 | parameter. This is calculated differently depending on which exception | ||
324 | we're in. Second parameter is exception number, used for a string lookup | ||
325 | in UIE. | ||
326 | */ | ||
327 | undef_instr_handler: | ||
328 | mov r0, lr | ||
329 | mov r1, #0 | ||
330 | b UIE | ||
331 | |||
332 | /* We run supervisor mode most of the time, and should never see a software | ||
333 | exception being thrown. Perhaps make it illegal and call UIE? | ||
334 | */ | ||
335 | software_int_handler: | ||
336 | reserved_handler: | ||
337 | movs pc, lr | ||
338 | |||
339 | prefetch_abort_handler: | ||
340 | sub r0, lr, #4 | ||
341 | mov r1, #1 | ||
342 | b UIE | ||
343 | |||
344 | fiq_handler: | ||
345 | @ Branch straight to FIQ handler in pcm_playback.c. This also handles the | ||
346 | @ the correct return sequence. | ||
347 | ldr pc, =fiq | ||
348 | |||
349 | data_abort_handler: | ||
350 | sub r0, lr, #8 | ||
351 | mov r1, #2 | ||
352 | b UIE | ||
353 | |||
354 | irq_handler: | ||
355 | #ifndef STUB | ||
356 | stmfd sp!, {r0-r3, r12, lr} | ||
357 | bl irq | ||
358 | ldmfd sp!, {r0-r3, r12, lr} | ||
359 | #endif | ||
360 | subs pc, lr, #4 | ||
361 | |||
362 | #ifdef STUB | ||
363 | UIE: | ||
364 | b UIE | ||
365 | #endif | ||
366 | |||
367 | /* 256 words of IRQ stack */ | ||
368 | .space 256*4 | ||
369 | irq_stack: | ||
370 | |||
371 | /* 256 words of FIQ stack */ | ||
372 | .space 256*4 | ||
373 | fiq_stack: | ||
374 | |||
375 | #endif /* BOOTLOADER */ | ||
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S new file mode 100644 index 0000000000..82b7c31f92 --- /dev/null +++ b/firmware/target/arm/crt0.S | |||
@@ -0,0 +1,232 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | |||
22 | .section .init.text,"ax",%progbits | ||
23 | |||
24 | .global start | ||
25 | start: | ||
26 | |||
27 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader | ||
28 | * | ||
29 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
30 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
31 | * | ||
32 | */ | ||
33 | |||
34 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
35 | |||
36 | #ifndef BOOTLOADER | ||
37 | #if CONFIG_CPU == PNX0101 | ||
38 | |||
39 | #ifndef DEBUG | ||
40 | ldr r0, =0x80105000 | ||
41 | mov r1, #1 | ||
42 | str r1, [r0, #4] | ||
43 | mov r1, #0 | ||
44 | str r1, [r0, #4] | ||
45 | 1: ldr r1, [r0] | ||
46 | cmp r1, #0 | ||
47 | bne 1b | ||
48 | mov r1, #0x74 | ||
49 | str r1, [r0, #8] | ||
50 | mov r1, #2 | ||
51 | str r1, [r0, #0x18] | ||
52 | mov r1, #0x120 | ||
53 | str r1, [r0, #0x30] | ||
54 | mov r1, #6 | ||
55 | str r1, [r0, #4] | ||
56 | ldr r0, =1f | ||
57 | mov r15, r0 | ||
58 | 1: | ||
59 | #endif /* !DEBUG */ | ||
60 | #endif /* chipset specific */ | ||
61 | |||
62 | #ifndef DEBUG | ||
63 | /* Copy exception handler code to address 0 */ | ||
64 | ldr r2, =_vectorsstart | ||
65 | ldr r3, =_vectorsend | ||
66 | ldr r4, =_vectorscopy | ||
67 | 1: | ||
68 | cmp r3, r2 | ||
69 | ldrhi r5, [r4], #4 | ||
70 | strhi r5, [r2], #4 | ||
71 | bhi 1b | ||
72 | #else | ||
73 | ldr r1, =vectors | ||
74 | ldr r0, =irq_handler | ||
75 | str r0, [r1, #24] | ||
76 | ldr r0, =fiq_handler | ||
77 | str r0, [r1, #28] | ||
78 | #endif | ||
79 | |||
80 | #ifndef STUB | ||
81 | /* Zero out IBSS */ | ||
82 | ldr r2, =_iedata | ||
83 | ldr r3, =_iend | ||
84 | mov r4, #0 | ||
85 | 1: | ||
86 | cmp r3, r2 | ||
87 | strhi r4, [r2], #4 | ||
88 | bhi 1b | ||
89 | |||
90 | /* Copy the IRAM */ | ||
91 | ldr r2, =_iramcopy | ||
92 | ldr r3, =_iramstart | ||
93 | ldr r4, =_iramend | ||
94 | 1: | ||
95 | cmp r4, r3 | ||
96 | ldrhi r5, [r2], #4 | ||
97 | strhi r5, [r3], #4 | ||
98 | bhi 1b | ||
99 | #endif /* !STUB */ | ||
100 | #endif /* !BOOTLOADER */ | ||
101 | |||
102 | /* Initialise bss section to zero */ | ||
103 | ldr r2, =_edata | ||
104 | ldr r3, =_end | ||
105 | mov r4, #0 | ||
106 | 1: | ||
107 | cmp r3, r2 | ||
108 | strhi r4, [r2], #4 | ||
109 | bhi 1b | ||
110 | |||
111 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
112 | ldr sp, =stackend | ||
113 | mov r3, sp | ||
114 | ldr r2, =stackbegin | ||
115 | ldr r4, =0xdeadbeef | ||
116 | 1: | ||
117 | cmp r3, r2 | ||
118 | strhi r4, [r2], #4 | ||
119 | bhi 1b | ||
120 | |||
121 | #ifdef BOOTLOADER | ||
122 | /* Code for ARM bootloader targets other than iPod go here */ | ||
123 | |||
124 | #if CONFIG_CPU == S3C2440 | ||
125 | bl main | ||
126 | #endif | ||
127 | |||
128 | #else /* BOOTLOADER */ | ||
129 | |||
130 | /* Set up stack for IRQ mode */ | ||
131 | msr cpsr_c, #0xd2 | ||
132 | ldr sp, =irq_stack | ||
133 | /* Set up stack for FIQ mode */ | ||
134 | msr cpsr_c, #0xd1 | ||
135 | ldr sp, =fiq_stack | ||
136 | |||
137 | /* Let abort and undefined modes use IRQ stack */ | ||
138 | msr cpsr_c, #0xd7 | ||
139 | ldr sp, =irq_stack | ||
140 | msr cpsr_c, #0xdb | ||
141 | ldr sp, =irq_stack | ||
142 | /* Switch to supervisor mode */ | ||
143 | msr cpsr_c, #0xd3 | ||
144 | ldr sp, =stackend | ||
145 | bl main | ||
146 | /* main() should never return */ | ||
147 | |||
148 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | ||
149 | .section .vectors,"aw" | ||
150 | ldr pc, [pc, #24] | ||
151 | ldr pc, [pc, #24] | ||
152 | ldr pc, [pc, #24] | ||
153 | ldr pc, [pc, #24] | ||
154 | ldr pc, [pc, #24] | ||
155 | ldr pc, [pc, #24] | ||
156 | ldr pc, [pc, #24] | ||
157 | ldr pc, [pc, #24] | ||
158 | |||
159 | /* Exception vectors */ | ||
160 | .global vectors | ||
161 | vectors: | ||
162 | .word start | ||
163 | .word undef_instr_handler | ||
164 | .word software_int_handler | ||
165 | .word prefetch_abort_handler | ||
166 | .word data_abort_handler | ||
167 | .word reserved_handler | ||
168 | .word irq_handler | ||
169 | .word fiq_handler | ||
170 | |||
171 | .text | ||
172 | |||
173 | #ifndef STUB | ||
174 | .global irq | ||
175 | .global fiq | ||
176 | .global UIE | ||
177 | #endif | ||
178 | |||
179 | /* All illegal exceptions call into UIE with exception address as first | ||
180 | parameter. This is calculated differently depending on which exception | ||
181 | we're in. Second parameter is exception number, used for a string lookup | ||
182 | in UIE. | ||
183 | */ | ||
184 | undef_instr_handler: | ||
185 | mov r0, lr | ||
186 | mov r1, #0 | ||
187 | b UIE | ||
188 | |||
189 | /* We run supervisor mode most of the time, and should never see a software | ||
190 | exception being thrown. Perhaps make it illegal and call UIE? | ||
191 | */ | ||
192 | software_int_handler: | ||
193 | reserved_handler: | ||
194 | movs pc, lr | ||
195 | |||
196 | prefetch_abort_handler: | ||
197 | sub r0, lr, #4 | ||
198 | mov r1, #1 | ||
199 | b UIE | ||
200 | |||
201 | fiq_handler: | ||
202 | @ Branch straight to FIQ handler in pcm_playback.c. This also handles the | ||
203 | @ the correct return sequence. | ||
204 | ldr pc, =fiq | ||
205 | |||
206 | data_abort_handler: | ||
207 | sub r0, lr, #8 | ||
208 | mov r1, #2 | ||
209 | b UIE | ||
210 | |||
211 | irq_handler: | ||
212 | #ifndef STUB | ||
213 | stmfd sp!, {r0-r3, r12, lr} | ||
214 | bl irq | ||
215 | ldmfd sp!, {r0-r3, r12, lr} | ||
216 | #endif | ||
217 | subs pc, lr, #4 | ||
218 | |||
219 | #ifdef STUB | ||
220 | UIE: | ||
221 | b UIE | ||
222 | #endif | ||
223 | |||
224 | /* 256 words of IRQ stack */ | ||
225 | .space 256*4 | ||
226 | irq_stack: | ||
227 | |||
228 | /* 256 words of FIQ stack */ | ||
229 | .space 256*4 | ||
230 | fiq_stack: | ||
231 | |||
232 | #endif /* BOOTLOADER */ | ||
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S new file mode 100644 index 0000000000..a0e948486e --- /dev/null +++ b/firmware/target/coldfire/crt0.S | |||
@@ -0,0 +1,260 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | |||
22 | .section .init.text,"ax",@progbits | ||
23 | |||
24 | .global start | ||
25 | start: | ||
26 | |||
27 | move.w #0x2700,%sr | ||
28 | |||
29 | move.l #vectors,%d0 | ||
30 | movec.l %d0,%vbr | ||
31 | |||
32 | move.l #MBAR+1,%d0 | ||
33 | movec.l %d0,%mbar | ||
34 | |||
35 | move.l #MBAR2+1,%d0 | ||
36 | movec.l %d0,%mbar2 | ||
37 | |||
38 | lea MBAR,%a0 | ||
39 | lea MBAR2,%a1 | ||
40 | |||
41 | clr.l (0x180,%a1) /* PLLCR = 0 */ | ||
42 | |||
43 | /* 64K DMA-capable SRAM at 0x10000000 | ||
44 | DMA is enabled and has priority in both banks | ||
45 | All types of accesses are allowed | ||
46 | (We might want to restrict that to save power) */ | ||
47 | move.l #0x10000e01,%d0 | ||
48 | movec.l %d0,%rambar1 | ||
49 | |||
50 | /* 32K Non-DMA SRAM at 0x10010000 | ||
51 | All types of accesses are allowed | ||
52 | (We might want to restrict that to save power) */ | ||
53 | move.l #0x10010001,%d0 | ||
54 | movec.l %d0,%rambar0 | ||
55 | |||
56 | /* Chip select 0 - Flash ROM */ | ||
57 | moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */ | ||
58 | move.l %d0,(0x080,%a0) | ||
59 | move.l #FLASH_SIZE-0x10000+1,%d0 /* CSMR0 - All access */ | ||
60 | move.l %d0,(0x084,%a0) | ||
61 | move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */ | ||
62 | move.l %d0,(0x088,%a0) | ||
63 | |||
64 | /* Chip select 1 - LCD controller */ | ||
65 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ | ||
66 | move.l %d0,(0x08c,%a0) | ||
67 | moveq.l #0x1,%d0 /* CSMR1 - 64K */ | ||
68 | move.l %d0,(0x090,%a0) | ||
69 | move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ | ||
70 | move.l %d0,(0x094,%a0) | ||
71 | |||
72 | /* Chip select 2 - ATA controller */ | ||
73 | move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ | ||
74 | move.l %d0,(0x098,%a0) | ||
75 | move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */ | ||
76 | move.l %d0,(0x09c,%a0) | ||
77 | move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ | ||
78 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. | ||
79 | We have to be careful with the access times, | ||
80 | since IORDY isn't connected to the HDD. */ | ||
81 | |||
82 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
83 | /* Chip select 3 - USBOTG controller */ | ||
84 | move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */ | ||
85 | move.l %d0,(0x0a4,%a0) | ||
86 | moveq.l #0x1,%d0 /* CSMR3 - 64K */ | ||
87 | move.l %d0,(0x0a8,%a0) | ||
88 | move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */ | ||
89 | move.l %d0,(0x0ac,%a0) | ||
90 | #endif | ||
91 | |||
92 | #ifdef BOOTLOADER | ||
93 | /* Check if original firmware is still present */ | ||
94 | lea 0x00001000,%a2 | ||
95 | move.l (%a2),%d0 | ||
96 | move.l #0xfbfbfbf1,%d1 | ||
97 | cmp.l %d0,%d1 | ||
98 | beq.b .ignorecookie | ||
99 | |||
100 | /* The cookie is not reset. This must mean that the boot loader | ||
101 | has crashed. Let's start the original firmware immediately. */ | ||
102 | lea 0x10017ffc,%a2 | ||
103 | move.l (%a2),%d0 | ||
104 | move.l #0xc0015a17,%d1 | ||
105 | cmp.l %d0,%d1 | ||
106 | bne.b .nocookie | ||
107 | /* Clear the cookie again */ | ||
108 | clr.l (%a2) | ||
109 | jmp 8 | ||
110 | |||
111 | .nocookie: | ||
112 | /* Set the cookie */ | ||
113 | move.l %d1,(%a2) | ||
114 | .ignorecookie: | ||
115 | |||
116 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | ||
117 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | ||
118 | #if MEM < 32 | ||
119 | move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */ | ||
120 | #else | ||
121 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ | ||
122 | #endif | ||
123 | move.w %d0,(0x100,%a0) | ||
124 | |||
125 | /* Note on 32Mbyte models: | ||
126 | We place the SDRAM on an 0x1000000 (16M) offset because | ||
127 | the 5249 BGA chip has a fault which disables the use of A24. The | ||
128 | suggested workaround by FreeScale is to offset the base address by | ||
129 | half the DRAM size and increase the mask to the double. | ||
130 | In our case this means that we set the base address 16M ahead and | ||
131 | use a 64M mask. | ||
132 | */ | ||
133 | #if MEM < 32 | ||
134 | move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, | ||
135 | CAS latency 1, Page mode, No refresh yet */ | ||
136 | move.l %d0,(0x108,%a0) | ||
137 | move.l #0x00fc0001,%d0 /* Size: 16M */ | ||
138 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | ||
139 | #else | ||
140 | move.l #0x31002524,%d0 /* DACR0 - Base 0x31000000, Banks on 23 and up, | ||
141 | CAS latency 1, Page mode, No refresh yet */ | ||
142 | move.l %d0,(0x108,%a0) | ||
143 | move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */ | ||
144 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | ||
145 | #endif | ||
146 | |||
147 | /* Precharge */ | ||
148 | moveq.l #8,%d0 | ||
149 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a | ||
150 | Precharge command */ | ||
151 | move.l #0xabcd1234,%d0 | ||
152 | move.l %d0,0x31000000 /* Issue precharge command */ | ||
153 | |||
154 | move.l #0x8000,%d0 | ||
155 | or.l %d0,(0x108,%a0) /* Enable refresh */ | ||
156 | |||
157 | /* Let it refresh */ | ||
158 | move.l #500,%d0 | ||
159 | .delayloop: | ||
160 | subq.l #1,%d0 | ||
161 | bne.b .delayloop | ||
162 | |||
163 | /* Mode Register init */ | ||
164 | moveq.l #0x40,%d0 /* DACR0[IMRS] = 1, next access will set the | ||
165 | Mode Register */ | ||
166 | or.l %d0,(0x108,%a0) | ||
167 | |||
168 | move.l #0xabcd1234,%d0 | ||
169 | move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ | ||
170 | |||
171 | /* DACR0[IMRS] gets deactivated by the SDRAM controller */ | ||
172 | #endif /* BOOTLOADER */ | ||
173 | |||
174 | /* Invalicate cache */ | ||
175 | move.l #0x01000000,%d0 | ||
176 | movec.l %d0,%cacr | ||
177 | |||
178 | /* Enable cache, default=non-cacheable,no buffered writes */ | ||
179 | move.l #0x80000000,%d0 | ||
180 | movec.l %d0,%cacr | ||
181 | |||
182 | /* Cache enabled in SDRAM only, buffered writes enabled */ | ||
183 | move.l #0x3103c020,%d0 | ||
184 | movec.l %d0,%acr0 | ||
185 | moveq.l #0,%d0 | ||
186 | movec.l %d0,%acr1 | ||
187 | |||
188 | #ifndef BOOTLOADER | ||
189 | /* zero out .ibss */ | ||
190 | lea _iedata,%a2 | ||
191 | lea _iend,%a4 | ||
192 | bra.b .iedatastart | ||
193 | .iedataloop: | ||
194 | clr.l (%a2)+ | ||
195 | .iedatastart: | ||
196 | cmp.l %a2,%a4 | ||
197 | bhi.b .iedataloop | ||
198 | |||
199 | /* copy the .iram section */ | ||
200 | lea _iramcopy,%a2 | ||
201 | lea _iramstart,%a3 | ||
202 | lea _iramend,%a4 | ||
203 | bra.b .iramstart | ||
204 | .iramloop: | ||
205 | move.l (%a2)+,(%a3)+ | ||
206 | .iramstart: | ||
207 | cmp.l %a3,%a4 | ||
208 | bhi.b .iramloop | ||
209 | #endif /* !BOOTLOADER */ | ||
210 | |||
211 | #ifdef IRIVER_H300_SERIES | ||
212 | /* Set KEEP_ACT before doing the lengthy copy and zero-fill operations */ | ||
213 | move.l #0x00080000,%d0 | ||
214 | or.l %d0,(0xb4,%a1) | ||
215 | or.l %d0,(0xb8,%a1) | ||
216 | or.l %d0,(0xbc,%a1) | ||
217 | #endif | ||
218 | |||
219 | /* zero out bss */ | ||
220 | lea _edata,%a2 | ||
221 | lea _end,%a4 | ||
222 | bra.b .edatastart | ||
223 | .edataloop: | ||
224 | clr.l (%a2)+ | ||
225 | .edatastart: | ||
226 | cmp.l %a2,%a4 | ||
227 | bhi.b .edataloop | ||
228 | |||
229 | /* copy the .data section */ | ||
230 | lea _datacopy,%a2 | ||
231 | lea _datastart,%a3 | ||
232 | cmp.l %a2,%a3 | ||
233 | beq.b .nodatacopy /* Don't copy if src and dest are equal */ | ||
234 | lea _dataend,%a4 | ||
235 | bra.b .datastart | ||
236 | .dataloop: | ||
237 | move.l (%a2)+,(%a3)+ | ||
238 | .datastart: | ||
239 | cmp.l %a3,%a4 | ||
240 | bhi.b .dataloop | ||
241 | .nodatacopy: | ||
242 | |||
243 | /* Munge the main stack */ | ||
244 | lea stackbegin,%a2 | ||
245 | lea stackend,%a4 | ||
246 | move.l %a4,%sp | ||
247 | move.l #0xdeadbeef,%d0 | ||
248 | .mungeloop: | ||
249 | move.l %d0,(%a2)+ | ||
250 | cmp.l %a2,%a4 | ||
251 | bhi.b .mungeloop | ||
252 | |||
253 | jsr main | ||
254 | .hoo: | ||
255 | bra.b .hoo | ||
256 | |||
257 | .section .resetvectors | ||
258 | vectors: | ||
259 | .long stackend | ||
260 | .long start | ||
diff --git a/firmware/target/sh/crt0.S b/firmware/target/sh/crt0.S new file mode 100644 index 0000000000..87cef56e96 --- /dev/null +++ b/firmware/target/sh/crt0.S | |||
@@ -0,0 +1,214 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | |||
22 | .section .init.text,"ax",@progbits | ||
23 | |||
24 | .global start | ||
25 | start: | ||
26 | |||
27 | mov.l .vbr_k,r1 | ||
28 | #ifdef DEBUG | ||
29 | /* If we have built our code to be loaded via the standalone GDB | ||
30 | * stub, we will have out VBR at some other location than 0x9000000. | ||
31 | * We must copy the trap vectors for the GDB stub to our vector table. */ | ||
32 | mov.l .orig_vbr_k,r2 | ||
33 | |||
34 | /* Move the invalid instruction vector (4) */ | ||
35 | mov #4,r0 | ||
36 | shll2 r0 | ||
37 | mov.l @(r0,r2),r3 | ||
38 | mov.l r3,@(r0,r1) | ||
39 | |||
40 | /* Move the invalid slot vector (6) */ | ||
41 | mov #6,r0 | ||
42 | shll2 r0 | ||
43 | mov.l @(r0,r2),r3 | ||
44 | mov.l r3,@(r0,r1) | ||
45 | |||
46 | /* Move the bus error vector (9) */ | ||
47 | mov #9,r0 | ||
48 | shll2 r0 | ||
49 | mov.l @(r0,r2),r3 | ||
50 | mov.l r3,@(r0,r1) | ||
51 | |||
52 | /* Move the DMA bus error vector (10) */ | ||
53 | mov #10,r0 | ||
54 | shll2 r0 | ||
55 | mov.l @(r0,r2),r3 | ||
56 | mov.l r3,@(r0,r1) | ||
57 | |||
58 | /* Move the NMI vector as well (11) */ | ||
59 | mov #11,r0 | ||
60 | shll2 r0 | ||
61 | mov.l @(r0,r2),r3 | ||
62 | mov.l r3,@(r0,r1) | ||
63 | |||
64 | /* Move the UserBreak vector as well (12) */ | ||
65 | mov #12,r0 | ||
66 | shll2 r0 | ||
67 | mov.l @(r0,r2),r3 | ||
68 | mov.l r3,@(r0,r1) | ||
69 | |||
70 | /* Move the breakpoint trap vector (32) */ | ||
71 | mov #32,r0 | ||
72 | shll2 r0 | ||
73 | mov.l @(r0,r2),r3 | ||
74 | mov.l r3,@(r0,r1) | ||
75 | |||
76 | /* Move the IO trap vector (33) */ | ||
77 | mov #33,r0 | ||
78 | shll2 r0 | ||
79 | mov.l @(r0,r2),r3 | ||
80 | mov.l r3,@(r0,r1) | ||
81 | |||
82 | /* Move the serial Rx interrupt vector (105) */ | ||
83 | mov #105,r0 | ||
84 | shll2 r0 | ||
85 | mov.l @(r0,r2),r3 | ||
86 | mov.l r3,@(r0,r1) | ||
87 | |||
88 | /* Move the single step trap vector (127) */ | ||
89 | mov #127,r0 | ||
90 | shll2 r0 | ||
91 | mov.l @(r0,r2),r3 | ||
92 | mov.l r3,@(r0,r1) | ||
93 | #endif /* DEBUG */ | ||
94 | ldc r1,vbr | ||
95 | |||
96 | mov #0,r0 | ||
97 | ldc r0,gbr | ||
98 | |||
99 | /* zero out .ibss */ | ||
100 | mov.l .iedata_k,r0 | ||
101 | mov.l .iend_k,r1 | ||
102 | bra .iedatastart | ||
103 | mov #0,r2 | ||
104 | .iedataloop: /* backwards is faster and shorter */ | ||
105 | mov.l r2,@-r1 | ||
106 | .iedatastart: | ||
107 | cmp/hi r0,r1 | ||
108 | bt .iedataloop | ||
109 | |||
110 | /* copy the .iram section */ | ||
111 | mov.l .iramcopy_k,r0 | ||
112 | mov.l .iram_k,r1 | ||
113 | mov.l .iramend_k,r2 | ||
114 | /* Note: We cannot put a PC relative load into the delay slot of a 'bra' | ||
115 | instruction (the offset would be wrong), but there is nothing else to | ||
116 | do before the loop, so the delay slot would be 'nop'. The cmp / bf | ||
117 | sequence is the same length, but more efficient. */ | ||
118 | cmp/hi r1,r2 | ||
119 | bf .noiramcopy | ||
120 | .iramloop: | ||
121 | mov.l @r0+,r3 | ||
122 | mov.l r3,@r1 | ||
123 | add #4,r1 | ||
124 | cmp/hi r1,r2 | ||
125 | bt .iramloop | ||
126 | .noiramcopy: | ||
127 | |||
128 | /* zero out bss */ | ||
129 | mov.l .edata_k,r0 | ||
130 | mov.l .end_k,r1 | ||
131 | bra .edatastart | ||
132 | mov #0,r2 | ||
133 | .edataloop: /* backwards is faster and shorter */ | ||
134 | mov.l r2,@-r1 | ||
135 | .edatastart: | ||
136 | cmp/hi r0,r1 | ||
137 | bt .edataloop | ||
138 | |||
139 | /* copy the .data section, for rombased execution */ | ||
140 | mov.l .datacopy_k,r0 | ||
141 | mov.l .data_k,r1 | ||
142 | cmp/eq r0,r1 | ||
143 | bt .nodatacopy /* Don't copy if src and dest are equal */ | ||
144 | mov.l .dataend_k,r2 | ||
145 | cmp/hi r1,r2 | ||
146 | bf .nodatacopy | ||
147 | .dataloop: | ||
148 | mov.l @r0+,r3 | ||
149 | mov.l r3,@r1 | ||
150 | add #4,r1 | ||
151 | cmp/hi r1,r2 | ||
152 | bt .dataloop | ||
153 | .nodatacopy: | ||
154 | |||
155 | /* Munge the main thread stack */ | ||
156 | mov.l .stackbegin_k,r0 | ||
157 | mov.l .stackend_k,r1 | ||
158 | mov r1,r15 | ||
159 | mov.l .deadbeef_k,r2 | ||
160 | .mungeloop: /* backwards is faster and shorter */ | ||
161 | mov.l r2,@-r1 | ||
162 | cmp/hi r0,r1 | ||
163 | bt .mungeloop | ||
164 | |||
165 | /* call the mainline */ | ||
166 | mov.l .main_k,r0 | ||
167 | jsr @r0 | ||
168 | nop | ||
169 | .hoo: | ||
170 | bra .hoo | ||
171 | nop | ||
172 | |||
173 | .align 2 | ||
174 | .vbr_k: | ||
175 | .long vectors | ||
176 | #ifdef DEBUG | ||
177 | .orig_vbr_k: | ||
178 | .long 0x09000000 | ||
179 | #endif | ||
180 | .iedata_k: | ||
181 | .long _iedata | ||
182 | .iend_k: | ||
183 | .long _iend | ||
184 | .iramcopy_k: | ||
185 | .long _iramcopy | ||
186 | .iram_k: | ||
187 | .long _iramstart | ||
188 | .iramend_k: | ||
189 | .long _iramend | ||
190 | .edata_k: | ||
191 | .long _edata | ||
192 | .end_k: | ||
193 | .long _end | ||
194 | .datacopy_k: | ||
195 | .long _datacopy | ||
196 | .data_k: | ||
197 | .long _datastart | ||
198 | .dataend_k: | ||
199 | .long _dataend | ||
200 | .stackbegin_k: | ||
201 | .long _stackbegin | ||
202 | .stackend_k: | ||
203 | .long _stackend | ||
204 | .deadbeef_k: | ||
205 | .long 0xdeadbeef | ||
206 | .main_k: | ||
207 | .long _main | ||
208 | |||
209 | .section .resetvectors | ||
210 | vectors: | ||
211 | .long start | ||
212 | .long _stackend | ||
213 | .long start | ||
214 | .long _stackend | ||