diff options
-rwxr-xr-x | firmware/export/imx31l.h | 175 |
1 files changed, 167 insertions, 8 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index e38d4a2955..637b89b0ab 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -16,6 +16,8 @@ | |||
16 | * KIND, either express or implied. | 16 | * KIND, either express or implied. |
17 | * | 17 | * |
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | #ifndef __IMX31L_H__ | ||
20 | #define __IMX31L_H__ | ||
19 | 21 | ||
20 | /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ | 22 | /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ |
21 | 23 | ||
@@ -26,7 +28,6 @@ | |||
26 | /* Place in the section with the framebuffer */ | 28 | /* Place in the section with the framebuffer */ |
27 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) | 29 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) |
28 | 30 | ||
29 | /*Frame Buffer and TTB defines from gigabeat f/x build*/ | ||
30 | #define FRAME ((short *)0x80100000) /* Framebuffer */ | 31 | #define FRAME ((short *)0x80100000) /* Framebuffer */ |
31 | #define LCD_BUFFER_SIZE ((320*240*2)) | 32 | #define LCD_BUFFER_SIZE ((320*240*2)) |
32 | #define TTB_SIZE (0x4000) | 33 | #define TTB_SIZE (0x4000) |
@@ -82,6 +83,7 @@ | |||
82 | #define AIPS2_BASE_ADDR 0x53F00000 | 83 | #define AIPS2_BASE_ADDR 0x53F00000 |
83 | #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR | 84 | #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR |
84 | #define CCM_BASE_ADDR 0x53F80000 | 85 | #define CCM_BASE_ADDR 0x53F80000 |
86 | #define CSPI3_BASE_ADDR 0x53F84000 | ||
85 | #define FIRI_BASE_ADDR 0x53F8C000 | 87 | #define FIRI_BASE_ADDR 0x53F8C000 |
86 | #define GPT1_BASE_ADDR 0x53F90000 | 88 | #define GPT1_BASE_ADDR 0x53F90000 |
87 | #define EPIT1_BASE_ADDR 0x53F94000 | 89 | #define EPIT1_BASE_ADDR 0x53F94000 |
@@ -108,10 +110,10 @@ | |||
108 | /* IOMUXC */ | 110 | /* IOMUXC */ |
109 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) | 111 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) |
110 | 112 | ||
111 | /* GPR */ | 113 | /* GPR */ |
112 | #define IOMUXC_GPR IOMUXC_(0x008) | 114 | #define IOMUXC_GPR IOMUXC_(0x008) |
113 | 115 | ||
114 | /* SW_MUX_CTL */ | 116 | /* SW_MUX_CTL */ |
115 | #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C) | 117 | #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C) |
116 | #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010) | 118 | #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010) |
117 | #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014) | 119 | #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014) |
@@ -216,7 +218,7 @@ | |||
216 | #define SW_MUX_CTL_FLD_2(x) ((x) << 16) | 218 | #define SW_MUX_CTL_FLD_2(x) ((x) << 16) |
217 | #define SW_MUX_CTL_FLD_3(x) ((x) << 24) | 219 | #define SW_MUX_CTL_FLD_3(x) ((x) << 24) |
218 | 220 | ||
219 | /* SW_PAD_CTL */ | 221 | /* SW_PAD_CTL */ |
220 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | 222 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) |
221 | #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158) | 223 | #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158) |
222 | #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C) | 224 | #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C) |
@@ -453,18 +455,41 @@ | |||
453 | #define ATA_CONTROLLER_IDLE (1 << 4) | 455 | #define ATA_CONTROLLER_IDLE (1 << 4) |
454 | #define ATA_INTRQ2 (1 << 3) | 456 | #define ATA_INTRQ2 (1 << 3) |
455 | 457 | ||
456 | /* Timers */ | 458 | /* EPIT */ |
457 | #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) | 459 | #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) |
458 | #define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04)) | 460 | #define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04)) |
459 | #define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08)) | 461 | #define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08)) |
460 | #define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C)) | 462 | #define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C)) |
461 | #define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10)) | 463 | #define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10)) |
464 | |||
462 | #define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00)) | 465 | #define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00)) |
463 | #define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04)) | 466 | #define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04)) |
464 | #define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08)) | 467 | #define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08)) |
465 | #define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C)) | 468 | #define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C)) |
466 | #define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10)) | 469 | #define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10)) |
467 | 470 | ||
471 | #define EPITCR_CLKSRC_OFF (0 << 24) | ||
472 | #define EPITCR_CLKSRC_IPG_CLK (1 << 24) | ||
473 | #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ (2 << 24) | ||
474 | #define EPITCR_CLKSRC_IPG_CLK_32K (3 << 24) | ||
475 | #define EPITCR_OM_DISCONNECTED (0 << 22) | ||
476 | #define EPITCR_OM_TOGGLE (1 << 22) | ||
477 | #define EPITCR_OM_CLEAR (2 << 22) | ||
478 | #define EPITCR_OM_SET (3 << 22) | ||
479 | #define EPITCR_STOPEN (1 << 21) | ||
480 | #define EPITCR_DOZEN (1 << 20) | ||
481 | #define EPITCR_WAITEN (1 << 19) | ||
482 | #define EPITCR_DBGEN (1 << 18) | ||
483 | #define EPITCR_IOVW (1 << 17) | ||
484 | #define EPITCR_SWR (1 << 16) | ||
485 | #define EPITCR_PRESCALER(n) ((n) << 4) /* Divide by n+1 */ | ||
486 | #define EPITCR_RLD (1 << 3) | ||
487 | #define EPITCR_OCIEN (1 << 2) | ||
488 | #define EPITCR_ENMOD (1 << 1) | ||
489 | #define EPITCR_EN (1 << 0) | ||
490 | |||
491 | #define EPITSR_OCIF (1 << 0) | ||
492 | |||
468 | /* GPIO */ | 493 | /* GPIO */ |
469 | #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00)) | 494 | #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00)) |
470 | #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04)) | 495 | #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04)) |
@@ -490,7 +515,7 @@ | |||
490 | #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14)) | 515 | #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14)) |
491 | #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) | 516 | #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) |
492 | 517 | ||
493 | /* SPI */ | 518 | /* CSPI */ |
494 | #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00)) | 519 | #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00)) |
495 | #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04)) | 520 | #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04)) |
496 | #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08)) | 521 | #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08)) |
@@ -509,6 +534,79 @@ | |||
509 | #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18)) | 534 | #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18)) |
510 | #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0)) | 535 | #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0)) |
511 | 536 | ||
537 | #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00)) | ||
538 | #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04)) | ||
539 | #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08)) | ||
540 | #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C)) | ||
541 | #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10)) | ||
542 | #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14)) | ||
543 | #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18)) | ||
544 | #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0)) | ||
545 | |||
546 | /* CSPI CONREG flags/fields */ | ||
547 | #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24) | ||
548 | #define CSPI_CONREG_CHIP_SELECT_SS1 (1 << 24) | ||
549 | #define CSPI_CONREG_CHIP_SELECT_SS2 (2 << 24) | ||
550 | #define CSPI_CONREG_CHIP_SELECT_SS3 (3 << 24) | ||
551 | #define CSPI_CONREG_CHIP_SELECT_MASK (3 << 24) | ||
552 | #define CSPI_CONREG_DRCTL_DONT_CARE (0 << 20) | ||
553 | #define CSPI_CONREG_DRCTL_TRIG_FALLING (1 << 20) | ||
554 | #define CSPI_CONREG_DRCTL_TRIG_LOW (2 << 20) | ||
555 | #define CSPI_CONREG_DRCTL_TRIG_RSV (3 << 20) | ||
556 | #define CSPI_CONREG_DRCTL_MASK (3 << 20) | ||
557 | #define CSPI_CONREG_DATA_RATE_DIV_4 (0 << 16) | ||
558 | #define CSPI_CONREG_DATA_RATE_DIV_8 (1 << 16) | ||
559 | #define CSPI_CONREG_DATA_RATE_DIV_16 (2 << 16) | ||
560 | #define CSPI_CONREG_DATA_RATE_DIV_32 (3 << 16) | ||
561 | #define CSPI_CONREG_DATA_RATE_DIV_64 (4 << 16) | ||
562 | #define CSPI_CONREG_DATA_RATE_DIV_128 (5 << 16) | ||
563 | #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16) | ||
564 | #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16) | ||
565 | #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16) | ||
566 | #define CSPI_CONREG_SSPOL (1 << 7) | ||
567 | #define CSPI_CONREG_SSCTL (1 << 6) | ||
568 | #define CSPI_CONREG_PHA (1 << 6) | ||
569 | #define CSPI_CONREG_POL (1 << 4) | ||
570 | #define CSPI_CONREG_SMC (1 << 3) | ||
571 | #define CSPI_CONREG_XCH (1 << 2) | ||
572 | #define CSPI_CONREG_MODE (1 << 1) | ||
573 | #define CSPI_CONREG_EN (1 << 0) | ||
574 | |||
575 | /* CSPI INTREG flags */ | ||
576 | #define CSPI_INTREG_TCEN (1 << 8) | ||
577 | #define CSPI_INTREG_BOEN (1 << 7) | ||
578 | #define CSPI_INTREG_ROEN (1 << 6) | ||
579 | #define CSPI_INTREG_RFEN (1 << 5) | ||
580 | #define CSPI_INTREG_RHEN (1 << 4) | ||
581 | #define CSPI_INTREG_RREN (1 << 3) | ||
582 | #define CSPI_INTREG_TFEN (1 << 2) | ||
583 | #define CSPI_INTREG_THEN (1 << 1) | ||
584 | #define CSPI_INTREF_TEEN (1 << 0) | ||
585 | |||
586 | /* CSPI DMAREG flags */ | ||
587 | #define CSPI_DMAREG_RFDEN (1 << 5) | ||
588 | #define CSPI_DMAREG_RHDEN (1 << 4) | ||
589 | #define CSPI_DMAREG_THDEN (1 << 1) | ||
590 | #define CSPI_DMAREG_TEDEN (1 << 0) | ||
591 | |||
592 | /* CSPI STATREG flags */ | ||
593 | #define CSPI_STATREG_TC (1 << 8) /* w1c */ | ||
594 | #define CSPI_STATREG_BO (1 << 7) /* w1c */ | ||
595 | #define CSPI_STATREG_RO (1 << 6) | ||
596 | #define CSPI_STATREG_RF (1 << 5) | ||
597 | #define CSPI_STATREG_RH (1 << 4) | ||
598 | #define CSPI_STATREG_RR (1 << 3) | ||
599 | #define CSPI_STATREG_TF (1 << 2) | ||
600 | #define CSPI_STATREG_TH (1 << 1) | ||
601 | #define CSPI_STATREG_TE (1 << 0) | ||
602 | |||
603 | /* CSPI PERIODREG flags */ | ||
604 | #define CSPI_PERIODREG_CSRC (1 << 15) | ||
605 | |||
606 | /* CSPI TESTREG flags */ | ||
607 | #define CSPI_TESTREG_SWAP (1 << 15) | ||
608 | #define CSPI_TESTREG_LBC (1 << 14) | ||
609 | |||
512 | /* RTC */ | 610 | /* RTC */ |
513 | #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00)) | 611 | #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00)) |
514 | #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04)) | 612 | #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04)) |
@@ -642,7 +740,6 @@ | |||
642 | #define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) | 740 | #define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) |
643 | #define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) | 741 | #define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) |
644 | #define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) | 742 | #define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) |
645 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) | ||
646 | #define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) | 743 | #define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) |
647 | #define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) | 744 | #define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) |
648 | #define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) | 745 | #define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) |
@@ -652,8 +749,68 @@ | |||
652 | #define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) | 749 | #define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) |
653 | #define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) | 750 | #define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) |
654 | #define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) | 751 | #define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) |
752 | #define CLKCTL_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30)) | ||
753 | #define CLKCTL_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34)) | ||
754 | #define CLKCTL_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38)) | ||
755 | #define CLKCTL_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C)) | ||
756 | #define CLKCTL_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40)) | ||
757 | #define CLKCTL_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44)) | ||
758 | #define CLKCTL_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48)) | ||
759 | #define CLKCTL_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C)) | ||
760 | #define CLKCTL_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50)) | ||
761 | #define CLKCTL_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54)) | ||
762 | #define CLKCTL_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58)) | ||
655 | #define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) | 763 | #define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) |
656 | #define PLL_REF_CLK 26000000 | 764 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) |
765 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) | ||
766 | |||
767 | #define CG_OFF 0x0 /* Always off */ | ||
768 | #define CG_ON_RUN 0x1 /* On in run mode, off in wait and doze */ | ||
769 | #define CG_ON_RUN_WAIT 0x2 /* On in run and wait modes, off in doze */ | ||
770 | #define CG_ON_ALL 0x3 /* Always on */ | ||
771 | #define CG_MASK 0x3 /* bitmask */ | ||
772 | |||
773 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) | ||
774 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) | ||
775 | #define CGR0_GPT(cg) ((cg) << 2*2) | ||
776 | #define CGR0_EPIT1(cg) ((cg) << 3*2) | ||
777 | #define CGR0_EPIT2(cg) ((cg) << 4*2) | ||
778 | #define CGR0_IIM(cg) ((cg) << 5*2) | ||
779 | #define CGR0_ATA(cg) ((cg) << 6*2) | ||
780 | #define CGR0_SDMA(cg) ((cg) << 7*2) | ||
781 | #define CGR0_CSPI3(cg) ((cg) << 8*2) | ||
782 | #define CGR0_RNG(cg) ((cg) << 9*2) | ||
783 | #define CGR0_UART1(cg) ((cg) << 10*2) | ||
784 | #define CGR0_UART2(cg) ((cg) << 11*2) | ||
785 | #define CGR0_SSI1(cg) ((cg) << 12*2) | ||
786 | #define CGR0_I2C1(cg) ((cg) << 13*2) | ||
787 | #define CGR0_I2C2(cg) ((cg) << 14*2) | ||
788 | #define CGR0_I2C3(cg) ((cg) << 15*2) | ||
789 | |||
790 | #define CGR1_HANTRO(cg) ((cg) << 0*2) | ||
791 | #define CGR1_MEMSTICK1(cg) ((cg) << 1*2) | ||
792 | #define CGR1_MEMSTICK2(cg) ((cg) << 2*2) | ||
793 | #define CGR1_CSI(cg) ((cg) << 3*2) | ||
794 | #define CGR1_RTC(cg) ((cg) << 4*2) | ||
795 | #define CGR1_WDOG(cg) ((cg) << 5*2) | ||
796 | #define CGR1_PWM(cg) ((cg) << 6*2) | ||
797 | #define CGR1_SIM(cg) ((cg) << 7*2) | ||
798 | #define CGR1_ECT(cg) ((cg) << 8*2) | ||
799 | #define CGR1_USBOTG(cg) ((cg) << 9*2) | ||
800 | #define CGR1_KPP(cg) ((cg) << 10*2) | ||
801 | #define CGR1_IPU(cg) ((cg) << 11*2) | ||
802 | #define CGR1_UART3(cg) ((cg) << 12*2) | ||
803 | #define CGR1_UART4(cg) ((cg) << 13*2) | ||
804 | #define CGR1_UART5(cg) ((cg) << 14*2) | ||
805 | #define CGR1_1_WIRE(cg) ((cg) << 15*2) | ||
806 | |||
807 | #define CGR2_SSI2(cg) ((cg) << 0*2) | ||
808 | #define CGR2_CSPI1(cg) ((cg) << 1*2) | ||
809 | #define CGR2_CSPI2(cg) ((cg) << 2*2) | ||
810 | #define CGR2_GACC(cg) ((cg) << 3*2) | ||
811 | #define CGR2_EMI(cg) ((cg) << 4*2) | ||
812 | #define CGR2_RTIC(cg) ((cg) << 5*2) | ||
813 | #define CGR2_FIR(cg) ((cg) << 6*2) | ||
657 | 814 | ||
658 | /* WEIM - CS0 */ | 815 | /* WEIM - CS0 */ |
659 | #define CSCRU 0x00 | 816 | #define CSCRU 0x00 |
@@ -829,3 +986,5 @@ | |||
829 | #define readl(a) (*(REG32_PTR_T)(a)) | 986 | #define readl(a) (*(REG32_PTR_T)(a)) |
830 | #define writew(v,a) (*(REG16_PTR_T)(a) = (v)) | 987 | #define writew(v,a) (*(REG16_PTR_T)(a) = (v)) |
831 | #define readw(a) (*(REG16_PTR_T)(a)) | 988 | #define readw(a) (*(REG16_PTR_T)(a)) |
989 | |||
990 | #endif /* __IMX31L_H__ */ | ||