diff options
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 64 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 1 |
2 files changed, 42 insertions, 23 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index d32e74345f..7b6ef486cd 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -107,7 +107,6 @@ static void pp_set_cpu_frequency(long frequency) | |||
107 | #endif | 107 | #endif |
108 | { | 108 | { |
109 | unsigned long clcd_clock_src; | 109 | unsigned long clcd_clock_src; |
110 | bool use_pll = true; | ||
111 | 110 | ||
112 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 111 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
113 | /* Using mutex or spinlock isn't safe here. */ | 112 | /* Using mutex or spinlock isn't safe here. */ |
@@ -121,31 +120,39 @@ static void pp_set_cpu_frequency(long frequency) | |||
121 | cpu_frequency = frequency; | 120 | cpu_frequency = frequency; |
122 | clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */ | 121 | clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */ |
123 | 122 | ||
124 | CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf000000f) | 0x10000002; | ||
125 | /* set clock source 1 to 24MHz and select it */ | ||
126 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
127 | |||
128 | switch (frequency) | 123 | switch (frequency) |
129 | { | 124 | { |
130 | #if CONFIG_CPU == PP5020 | 125 | #if CONFIG_CPU == PP5020 |
131 | case CPUFREQ_MAX: | 126 | case CPUFREQ_MAX: |
132 | DEV_TIMING1 = 0x00000808; | 127 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
133 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ | 128 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ |
134 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ | 129 | DEV_TIMING1 = 0x00000808; |
135 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ | 130 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ |
136 | udelay(500); /* wait for relock */ | 131 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ |
132 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ | ||
133 | udelay(500); /* wait for relock */ | ||
137 | break; | 134 | break; |
138 | 135 | ||
139 | case CPUFREQ_NORMAL: | 136 | case CPUFREQ_NORMAL: |
140 | DEV_TIMING1 = 0x00000303; | 137 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
141 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ | 138 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ |
142 | udelay(500); /* wait for relock */ | 139 | DEV_TIMING1 = 0x00000303; |
140 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ | ||
141 | udelay(500); /* wait for relock */ | ||
142 | break; | ||
143 | |||
144 | case CPUFREQ_SLEEP: | ||
145 | CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */ | ||
146 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
147 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
148 | udelay(10000); /* let 32kHz source stabilize? */ | ||
143 | break; | 149 | break; |
144 | 150 | ||
145 | default: | 151 | default: |
146 | DEV_TIMING1 = 0x00000303; | 152 | CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ |
153 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
154 | DEV_TIMING1 = 0x00000303; | ||
147 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | 155 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
148 | use_pll = false; | ||
149 | cpu_frequency = CPUFREQ_DEFAULT; | 156 | cpu_frequency = CPUFREQ_DEFAULT; |
150 | break; | 157 | break; |
151 | 158 | ||
@@ -155,29 +162,40 @@ static void pp_set_cpu_frequency(long frequency) | |||
155 | * PP5026 is similar to PP5022 except it doesn't | 162 | * PP5026 is similar to PP5022 except it doesn't |
156 | * have this limitation (and the post divider?) */ | 163 | * have this limitation (and the post divider?) */ |
157 | case CPUFREQ_MAX: | 164 | case CPUFREQ_MAX: |
158 | DEV_TIMING1 = 0x00000808; | 165 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
159 | PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */ | 166 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ |
167 | DEV_TIMING1 = 0x00000808; | ||
168 | PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */ | ||
160 | udelay(250); | 169 | udelay(250); |
161 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | 170 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ |
162 | break; | 171 | break; |
163 | 172 | ||
164 | case CPUFREQ_NORMAL: | 173 | case CPUFREQ_NORMAL: |
165 | DEV_TIMING1 = 0x00000303; | 174 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
166 | PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */ | 175 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ |
176 | DEV_TIMING1 = 0x00000303; | ||
177 | PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */ | ||
167 | udelay(250); | 178 | udelay(250); |
168 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | 179 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ |
169 | break; | 180 | break; |
170 | 181 | ||
182 | case CPUFREQ_SLEEP: | ||
183 | CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */ | ||
184 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
185 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
186 | udelay(10000); /* let 32kHz source stabilize? */ | ||
187 | break; | ||
188 | |||
171 | default: | 189 | default: |
172 | DEV_TIMING1 = 0x00000303; | 190 | CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ |
191 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
192 | DEV_TIMING1 = 0x00000303; | ||
173 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | 193 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
174 | use_pll = false; | ||
175 | cpu_frequency = CPUFREQ_DEFAULT; | 194 | cpu_frequency = CPUFREQ_DEFAULT; |
176 | break; | 195 | break; |
177 | #endif | 196 | #endif |
178 | } | 197 | } |
179 | if (use_pll) /* set clock source 2 to PLL and select it */ | 198 | CLOCK_SOURCE = (CLOCK_SOURCE&~0xf000000)|0x20000000; /* select source #2 */ |
180 | CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf00000f0) | 0x20000070; | ||
181 | 199 | ||
182 | CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */ | 200 | CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */ |
183 | CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */ | 201 | CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */ |
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 426d83f71a..522e73123a 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -32,6 +32,7 @@ | |||
32 | #define CPUFREQ_MAX 80000000 | 32 | #define CPUFREQ_MAX 80000000 |
33 | 33 | ||
34 | #else /* PP5022, PP5024 */ | 34 | #else /* PP5022, PP5024 */ |
35 | #define CPUFREQ_SLEEP 32768 | ||
35 | #define CPUFREQ_DEFAULT 24000000 | 36 | #define CPUFREQ_DEFAULT 24000000 |
36 | #define CPUFREQ_NORMAL 30000000 | 37 | #define CPUFREQ_NORMAL 30000000 |
37 | #define CPUFREQ_MAX 80000000 | 38 | #define CPUFREQ_MAX 80000000 |