diff options
| -rw-r--r-- | firmware/target/arm/rk27xx/crt0.S | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/firmware/target/arm/rk27xx/crt0.S b/firmware/target/arm/rk27xx/crt0.S index 032c637458..4ddae01c53 100644 --- a/firmware/target/arm/rk27xx/crt0.S +++ b/firmware/target/arm/rk27xx/crt0.S | |||
| @@ -47,14 +47,20 @@ newstart2: | |||
| 47 | mov r0, #0x18000000 | 47 | mov r0, #0x18000000 |
| 48 | add r0, r0, #0x1c000 | 48 | add r0, r0, #0x1c000 |
| 49 | 49 | ||
| 50 | /* setup ARM core freq = 200MHz */ | 50 | /* setup ARM core freq = 200MHz |
| 51 | /* AHB bus freq (HCLK) = 100MHz */ | 51 | * AHB bus freq (HCLK) = 100MHz |
| 52 | /* APB bus freq (PCLK) = 50MHz */ | 52 | * APB bus freq (PCLK) = 50MHz |
| 53 | * Note: it seems there is no way to run AHB bus at ARM freq | ||
| 54 | * bit2 in DIVCON1 must have different meaning to what datasheet | ||
| 55 | * states. It influences SDRAM read speed but does not change | ||
| 56 | * APB freq | ||
| 57 | */ | ||
| 53 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ | 58 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ |
| 54 | orr r1, #9 /* ARM slow mode, HCLK:PCLK = 2:1 */ | 59 | bic r1, r1, #0x1f |
| 60 | orr r1, r1, #9 /* ((1<<3)|(1<<0)) ARM slow mode, HCLK:PCLK = 2:1 */ | ||
| 55 | str r1, [r0,#0x14] | 61 | str r1, [r0,#0x14] |
| 56 | 62 | ||
| 57 | ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */ | 63 | ldr r1,=0x1850310 /* ((1<<24)|(1<<23)|(5<<16)|(49<<4)) */ |
| 58 | str r1, [r0,#0x08] | 64 | str r1, [r0,#0x08] |
| 59 | 65 | ||
| 60 | ldr r2,=0x40000 | 66 | ldr r2,=0x40000 |
| @@ -62,11 +68,11 @@ newstart2: | |||
| 62 | ldr r1, [r0,#0x2c] /* SCU_STATUS */ | 68 | ldr r1, [r0,#0x2c] /* SCU_STATUS */ |
| 63 | tst r1, #1 /* ARM pll lock */ | 69 | tst r1, #1 /* ARM pll lock */ |
| 64 | bne 1f | 70 | bne 1f |
| 65 | subs r2, #1 | 71 | subs r2, r2, #1 |
| 66 | bne 1b | 72 | bne 1b |
| 67 | 1: | 73 | 1: |
| 68 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ | 74 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ |
| 69 | bic r1, #5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */ | 75 | bic r1, #1 /* leave ARM slow mode */ |
| 70 | str r1, [r0,#0x14] | 76 | str r1, [r0,#0x14] |
| 71 | 77 | ||
| 72 | #if defined(BOOTLOADER) | 78 | #if defined(BOOTLOADER) |
| @@ -75,7 +81,6 @@ newstart2: | |||
| 75 | str r1, [r0, #4] | 81 | str r1, [r0, #4] |
| 76 | #endif | 82 | #endif |
| 77 | 83 | ||
| 78 | #if 0 | ||
| 79 | /* setup caches */ | 84 | /* setup caches */ |
| 80 | ldr r0, =0xefff0000 /* cache controler base address */ | 85 | ldr r0, =0xefff0000 /* cache controler base address */ |
| 81 | ldrh r1, [r0] | 86 | ldrh r1, [r0] |
| @@ -110,7 +115,6 @@ newstart2: | |||
| 110 | ldr r1, [r0] | 115 | ldr r1, [r0] |
| 111 | orr r1, r1, #0x80000000 | 116 | orr r1, r1, #0x80000000 |
| 112 | str r1, [r0] /* global cache enable */ | 117 | str r1, [r0] /* global cache enable */ |
| 113 | #endif | ||
| 114 | 118 | ||
| 115 | /* Copy interrupt vectors to iram */ | 119 | /* Copy interrupt vectors to iram */ |
| 116 | ldr r2, =_intvectstart | 120 | ldr r2, =_intvectstart |