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-rw-r--r--firmware/led.c34
-rw-r--r--firmware/led.h16
-rw-r--r--firmware/serial.c64
-rw-r--r--firmware/sh7034.h409
-rw-r--r--firmware/system.c359
-rw-r--r--firmware/system.h21
6 files changed, 507 insertions, 396 deletions
diff --git a/firmware/led.c b/firmware/led.c
index 488964bcb9..d01c9de612 100644
--- a/firmware/led.c
+++ b/firmware/led.c
@@ -22,49 +22,49 @@
22#include <led.h> 22#include <led.h>
23 23
24#define turn_on() \ 24#define turn_on() \
25 set_bit (LEDB,PBDR+1) 25 set_bit (LEDB,PBDR_ADDR+1)
26 26
27#define turn_off() \ 27#define turn_off() \
28 clear_bit (LEDB,PBDR+1) 28 clear_bit (LEDB,PBDR_ADDR+1)
29 29
30#define start_timer() \ 30#define start_timer() \
31 set_bit (2,ITUTSTR) 31 set_bit (2,TSTR_ADDR)
32 32
33#define stop_timer() \ 33#define stop_timer() \
34 clear_bit (2,ITUTSTR) 34 clear_bit (2,TSTR_ADDR)
35 35
36#define eoi(subinterrupt) \ 36#define eoi(subinterrupt) \
37 clear_bit (subinterrupt,ITUTSR2) 37 clear_bit (subinterrupt,TSR2_ADDR)
38 38
39#define set_volume(volume) \ 39#define set_volume(volume) \
40 HI(ITUGRA2) = volume & 0x7FFF 40 GRA2 = volume & 0x7FFF
41 41
42 42
43void led_set_volume (unsigned short volume) 43void led_set_volume (unsigned short volume)
44 { 44{
45 volume <<= 10; 45 volume <<= 10;
46 if (volume == 0) 46 if (volume == 0)
47 led_turn_off (); 47 led_turn_off ();
48 else if (volume == 0x8000) 48 else if (volume == 0x8000)
49 led_turn_on (); 49 led_turn_on ();
50 else 50 else
51 { 51 {
52 set_volume (volume); 52 set_volume (volume);
53 start_timer (); 53 start_timer ();
54 } 54 }
55 } 55}
56 56
57#pragma interrupt 57#pragma interrupt
58void IMIA2 (void) 58void IMIA2 (void)
59 { 59{
60 turn_off (); 60 turn_off ();
61 eoi (0); 61 eoi (0);
62 } 62}
63 63
64#pragma interrupt 64#pragma interrupt
65void OVI2 (void) 65void OVI2 (void)
66 { 66{
67 turn_on (); 67 turn_on ();
68 eoi (2); 68 eoi (2);
69 } 69}
70 70
diff --git a/firmware/led.h b/firmware/led.h
index 0c43a70e74..955c59aa81 100644
--- a/firmware/led.h
+++ b/firmware/led.h
@@ -26,21 +26,21 @@
26#define LEDB 6 /* PB6 : red LED */ 26#define LEDB 6 /* PB6 : red LED */
27 27
28static inline void led_turn_off (void) 28static inline void led_turn_off (void)
29 { 29{
30 clear_bit (LEDB,PBDR+1); 30 clear_bit (LEDB,PBDR+1);
31 clear_bit (2,ITUTSTR); 31 clear_bit (2,TSTR_ADDR);
32 } 32}
33 33
34static inline void led_turn_on (void) 34static inline void led_turn_on (void)
35 { 35{
36 set_bit (LEDB,PBDR+1); 36 set_bit (LEDB,PBDR+1);
37 set_bit (2,ITUTSTR); 37 set_bit (2,TSTR_ADDR);
38 } 38}
39 39
40static inline void led_toggle (void) 40static inline void led_toggle (void)
41 { 41{
42 toggle_bit (LEDB,PBDR+1); 42 toggle_bit (LEDB,PBDR+1);
43 } 43}
44 44
45extern void led_set_volume (unsigned short volume); 45extern void led_set_volume (unsigned short volume);
46extern void led_setup (void); 46extern void led_setup (void);
diff --git a/firmware/serial.c b/firmware/serial.c
index f9708f98cf..217f23eb6f 100644
--- a/firmware/serial.c
+++ b/firmware/serial.c
@@ -31,54 +31,52 @@
31static int serial_byte,serial_flag; 31static int serial_byte,serial_flag;
32 32
33void serial_putc (char byte) 33void serial_putc (char byte)
34 { 34{
35 static int i = 0; 35 while (!(SSR1 & (1<<TDRE)));
36 while (!(QI(SCISSR1) & (1<<TDRE))); 36 TDR1 = byte;
37 QI(SCITDR1) = byte; 37 clear_bit(TDRE,SSR1_ADDR);
38 clear_bit (TDRE,SCISSR1); 38}
39 lcd_goto ((i++)%11,1); lcd_putc (byte);
40 }
41 39
42void serial_puts (char const *string) 40void serial_puts (char const *string)
43 { 41{
44 int byte; 42 int byte;
45 while ((byte = *string++)) 43 while ((byte = *string++))
46 serial_putc (byte); 44 serial_putc (byte);
47 } 45}
48 46
49int serial_getc( void ) 47int serial_getc( void )
50 { 48{
51 int byte; 49 int byte;
52 while (!serial_flag); 50 while (!serial_flag);
53 byte = serial_byte; 51 byte = serial_byte;
54 serial_flag = 0; 52 serial_flag = 0;
55 serial_putc (byte); 53 serial_putc (byte);
56 return byte; 54 return byte;
57 } 55}
58 56
59void serial_setup (int baudrate) 57void serial_setup (int baudrate)
60 { 58{
61 QI(SCISCR1) = 59 SCR1 = 0;
62 QI(SCISSR1) = 60 SSR1 = 0;
63 QI(SCISMR1) = 0; 61 SMR1 = 0;
64 QI(SCIBRR1) = (PHI/(32*baudrate))-1; 62 BRR1 = (FREQ/(32*baudrate))-1;
65 QI(SCISCR1) = 0x70; 63 SCR1 = 0x70;
66 } 64}
67 65
68#pragma interrupt 66#pragma interrupt
69void REI1 (void) 67void REI1 (void)
70 { 68{
71 clear_bit (FER,SCISSR1); 69 clear_bit (FER,SSR1_ADDR);
72 } 70}
73 71
74#pragma interrupt 72#pragma interrupt
75void RXI1 (void) 73void RXI1 (void)
76 { 74{
77 serial_byte = QI(SCIRDR1); 75 serial_byte = RDR1;
78 serial_flag = 1; 76 serial_flag = 1;
79 clear_bit (RDRF,SCISSR1); 77 clear_bit(RDRF,SSR1_ADDR);
80 if (serial_byte == '0') 78 if (serial_byte == '0')
81 lcd_turn_off_backlight (); 79 lcd_turn_off_backlight ();
82 if (serial_byte == '1') 80 if (serial_byte == '1')
83 lcd_turn_on_backlight (); 81 lcd_turn_on_backlight ();
84 } 82}
diff --git a/firmware/sh7034.h b/firmware/sh7034.h
index cbc59a04d5..57f617d544 100644
--- a/firmware/sh7034.h
+++ b/firmware/sh7034.h
@@ -22,146 +22,275 @@
22 22
23#define GBR 0x00000000 23#define GBR 0x00000000
24 24
25#define SCISMR0 0x05FFFEC0 25/* register address macros: */
26#define SCIBRR0 0x05FFFEC1
27#define SCISCR0 0x05FFFEC2
28#define SCITDR0 0x05FFFEC3
29#define SCISSR0 0x05FFFEC4
30#define SCIRDR0 0x05FFFEC5
31#define SCISMR1 0x05FFFEC8
32#define SCIBRR1 0x05FFFEC9
33#define SCISCR1 0x05FFFECA
34#define SCITDR1 0x05FFFECB
35#define SCISSR1 0x05FFFECC
36#define SCIRDR1 0x05FFFECD
37
38#define ADDRA 0x05FFFEE0
39#define ADDRAH 0x05FFFEE0
40#define ADDRAL 0x05FFFEE1
41#define ADDRB 0x05FFFEE2
42#define ADDRBH 0x05FFFEE2
43#define ADDRBL 0x05FFFEE3
44#define ADDRC 0x05FFFEE4
45#define ADDRCH 0x05FFFEE4
46#define ADDRCL 0x05FFFEE5
47#define ADDRD 0x05FFFEE6
48#define ADDRDH 0x05FFFEE6
49#define ADDRDL 0x05FFFEE6
50#define ADCSR 0x05FFFEE8
51#define ADCR 0x05FFFEE9
52
53#define ITUTSTR 0x05FFFF00
54#define ITUTSNC 0x05FFFF01
55#define ITUTMDR 0x05FFFF02
56#define ITUTFCR 0x05FFFF03
57#define ITUTCR0 0x05FFFF04
58#define ITUTIOR0 0x05FFFF05
59#define ITUTIER0 0x05FFFF06
60#define ITUTSR0 0x05FFFF07
61#define ITUTCNT0 0x05FFFF08
62#define ITUGRA0 0x05FFFF0A
63#define ITUGRB0 0x05FFFF0C
64#define ITUTCR1 0x05FFFF0E
65#define ITUTIOR1 0x05FFFF0F
66#define ITUTIER1 0x05FFFF10
67#define ITUTSR1 0x05FFFF11
68#define ITUTCNT1 0x05FFFF12
69#define ITUGRA1 0x05FFFF14
70#define ITUGRB1 0x05FFFF16
71#define ITUTCR2 0x05FFFF18
72#define ITUTIOR2 0x05FFFF19
73#define ITUTIER2 0x05FFFF1A
74#define ITUTSR2 0x05FFFF1B
75#define ITUTCNT2 0x05FFFF1C
76#define ITUGRA2 0x05FFFF1E
77#define ITUGRB2 0x05FFFF20
78#define ITUTCR3 0x05FFFF22
79#define ITUTIOR3 0x05FFFF23
80#define ITUTIER3 0x05FFFF24
81#define ITUTSR3 0x05FFFF25
82#define ITUTCNT3 0x05FFFF26
83#define ITUGRA3 0x05FFFF28
84#define ITUGRB3 0x05FFFF2A
85#define ITUBRA3 0x05FFFF2C
86#define ITUBRB3 0x05FFFF2E
87#define ITUTOCR 0x05FFFF31
88#define ITUTCR4 0x05FFFF32
89#define ITUTIOR4 0x05FFFF33
90#define ITUTIER4 0x05FFFF34
91#define ITUTSR4 0x05FFFF35
92#define ITUTCNT4 0x05FFFF36
93#define ITUGRA4 0x05FFFF38
94#define ITUGRB4 0x05FFFF3A
95#define ITUBRA4 0x05FFFF3C
96#define ITUBRB4 0x05FFFF3E
97
98#define DMACSAR0 0x05FFFF40
99#define DMACDAR0 0x05FFFF44
100#define DMACOR 0x05FFFF48
101#define DMACTCR0 0x05FFFF4A
102#define DMACCHCR0 0x05FFFF4E
103#define DMACSAR1 0x05FFFF50
104#define DMACDAR1 0x05FFFF54
105#define DMACTCR1 0x05FFFF5A
106#define DMACCHCR1 0x05FFFF5E
107#define DMACSAR2 0x05FFFF60
108#define DMACDAR2 0x05FFFF64
109#define DMACTCR2 0x05FFFF6A
110#define DMACCHCR2 0x05FFFF6E
111#define DMACSAR3 0x05FFFF70
112#define DMACDAR3 0x05FFFF74
113#define DMACTCR3 0x05FFFF7A
114#define DMACCHCR3 0x05FFFF7E
115
116#define INTCIPRAB 0x05FFFF84
117#define INTCIPRA 0x05FFFF84
118#define INTCIPRB 0x05FFFF86
119#define INTCIPRCD 0x05FFFF88
120#define INTCIPRC 0x05FFFF88
121#define INTCIPRD 0x05FFFF8A
122#define INTCIPRE 0x05FFFF8C
123#define INTCICR 0x05FFFF8E
124
125#define UBCBAR 0x05FFFF90
126#define UBCBARH 0x05FFFF90
127#define UBCBARL 0x05FFFF92
128#define UBCBAMR 0x05FFFF94
129#define UBCBAMRH 0x05FFFF94
130#define UBCBAMRL 0x05FFFF96
131#define UBCBBR 0x05FFFF98
132
133#define BSCBCR 0x05FFFFA0
134#define BSCWCR1 0x05FFFFA2
135#define BSCWCR2 0x05FFFFA4
136#define BSCWCR3 0x05FFFFA6
137#define BSCDCR 0x05FFFFA8
138#define BSCPCR 0x05FFFFAA
139#define BSCRCR 0x05FFFFAC
140#define BSCRTCSR 0x05FFFFAE
141#define BSCRTCNT 0x05FFFFB0
142#define BSCRTCOR 0x05FFFFB2
143
144#define WDTTCSR 0x05FFFFB8
145#define WDTTCNT 0x05FFFFB9
146#define WDTRSTCSR 0x05FFFFBB
147
148#define SBYCR 0x05FFFFBC
149
150#define PABDR 0x05FFFFC0
151#define PADR 0x05FFFFC0
152#define PBDR 0x05FFFFC2
153#define PABIOR 0x05FFFFC4
154#define PAIOR (*((volatile unsigned short *)0x05FFFFC4))
155#define PBIOR (*((volatile unsigned short *)0x05FFFFC6))
156#define PACR 0x05FFFFC8
157#define PACR1 0x05FFFFC8
158#define PACR2 0x05FFFFCA
159#define PBCR 0x05FFFFCC
160#define PBCR1 0x05FFFFCC
161#define PBCR2 0x05FFFFCE
162#define PCDR 0x05FFFFD1
163
164#define CASCR 0x05FFFFEE
165 26
27#define SMR0_ADDR 0x05FFFEC0
28#define BRR0_ADDR 0x05FFFEC1
29#define SCR0_ADDR 0x05FFFEC2
30#define TDR0_ADDR 0x05FFFEC3
31#define SSR0_ADDR 0x05FFFEC4
32#define RDR0_ADDR 0x05FFFEC5
33#define SMR1_ADDR 0x05FFFEC8
34#define BRR1_ADDR 0x05FFFEC9
35#define SCR1_ADDR 0x05FFFECA
36#define TDR1_ADDR 0x05FFFECB
37#define SSR1_ADDR 0x05FFFECC
38#define RDR1_ADDR 0x05FFFECD
39
40#define ADDRA_ADDR 0x05FFFEE0
41#define ADDRAH_ADDR 0x05FFFEE0
42#define ADDRAL_ADDR 0x05FFFEE1
43#define ADDRB_ADDR 0x05FFFEE2
44#define ADDRBH_ADDR 0x05FFFEE2
45#define ADDRBL_ADDR 0x05FFFEE3
46#define ADDRC_ADDR 0x05FFFEE4
47#define ADDRCH_ADDR 0x05FFFEE4
48#define ADDRCL_ADDR 0x05FFFEE5
49#define ADDRD_ADDR 0x05FFFEE6
50#define ADDRDH_ADDR 0x05FFFEE6
51#define ADDRDL_ADDR 0x05FFFEE6
52#define ADCSR_ADDR 0x05FFFEE8
53#define ADCR_ADDR 0x05FFFEE9
54
55#define TSTR_ADDR 0x05FFFF00
56#define TSNC_ADDR 0x05FFFF01
57#define TMDR_ADDR 0x05FFFF02
58#define TFCR_ADDR 0x05FFFF03
59#define TCR0_ADDR 0x05FFFF04
60#define TIOR0_ADDR 0x05FFFF05
61#define TIER0_ADDR 0x05FFFF06
62#define TSR0_ADDR 0x05FFFF07
63#define TCNT0_ADDR 0x05FFFF08
64#define GRA0_ADDR 0x05FFFF0A
65#define GRB0_ADDR 0x05FFFF0C
66#define TCR1_ADDR 0x05FFFF0E
67#define TIOR1_ADDR 0x05FFFF0F
68#define TIER1_ADDR 0x05FFFF10
69#define TSR1_ADDR 0x05FFFF11
70#define TCNT1_ADDR 0x05FFFF12
71#define GRA_ADDR1 0x05FFFF14
72#define GRB1_ADDR 0x05FFFF16
73#define TCR2_ADDR 0x05FFFF18
74#define TIOR2_ADDR 0x05FFFF19
75#define TIER2_ADDR 0x05FFFF1A
76#define TSR2_ADDR 0x05FFFF1B
77#define TCNT2_ADDR 0x05FFFF1C
78#define GRA2_ADDR 0x05FFFF1E
79#define GRB2_ADDR 0x05FFFF20
80#define TCR3_ADDR 0x05FFFF22
81#define TIOR3_ADDR 0x05FFFF23
82#define TIER3_ADDR 0x05FFFF24
83#define TSR3_ADDR 0x05FFFF25
84#define TCNT3_ADDR 0x05FFFF26
85#define GRA3_ADDR 0x05FFFF28
86#define GRB3_ADDR 0x05FFFF2A
87#define BRA3_ADDR 0x05FFFF2C
88#define BRB3_ADDR 0x05FFFF2E
89#define TOCR_ADDR 0x05FFFF31
90#define TCR4_ADDR 0x05FFFF32
91#define TIOR4_ADDR 0x05FFFF33
92#define TIER4_ADDR 0x05FFFF34
93#define TSR4_ADDR 0x05FFFF35
94#define TCNT4_ADDR 0x05FFFF36
95#define GRA4_ADDR 0x05FFFF38
96#define GRB4_ADDR 0x05FFFF3A
97#define BRA4_ADDR 0x05FFFF3C
98#define BRB4_ADDR 0x05FFFF3E
99
100#define SAR0_ADDR 0x05FFFF40
101#define DAR0_ADDR 0x05FFFF44
102#define OR_ADDR 0x05FFFF48
103#define TCR0_ADDR 0x05FFFF4A
104#define CHCR0_ADDR 0x05FFFF4E
105#define SAR1_ADDR 0x05FFFF50
106#define DAR1_ADDR 0x05FFFF54
107#define TCR1_ADDR 0x05FFFF5A
108#define CHCR1_ADDR 0x05FFFF5E
109#define SAR2_ADDR 0x05FFFF60
110#define DAR2_ADDR 0x05FFFF64
111#define TCR2_ADDR 0x05FFFF6A
112#define CHCR2_ADDR 0x05FFFF6E
113#define SAR3_ADDR 0x05FFFF70
114#define DAR3_ADDR 0x05FFFF74
115#define TCR3_ADDR 0x05FFFF7A
116#define CHCR3_ADDR 0x05FFFF7E
117
118#define IPRA_ADDR 0x05FFFF84
119#define IPRB_ADDR 0x05FFFF86
120#define IPRC_ADDR 0x05FFFF88
121#define IPRD_ADDR 0x05FFFF8A
122#define IPRE_ADDR 0x05FFFF8C
123#define ICR_ADDR 0x05FFFF8E
124
125#define BARH_ADDR 0x05FFFF90
126#define BARL_ADDR 0x05FFFF92
127#define BAMRH_ADDR 0x05FFFF94
128#define BAMRL_ADDR 0x05FFFF96
129#define BBR_ADDR 0x05FFFF98
130
131#define BCR_ADDR 0x05FFFFA0
132#define WCR1_ADDR 0x05FFFFA2
133#define WCR2_ADDR 0x05FFFFA4
134#define WCR3_ADDR 0x05FFFFA6
135#define DCR_ADDR 0x05FFFFA8
136#define PCR_ADDR 0x05FFFFAA
137#define RCR_ADDR 0x05FFFFAC
138#define RTCSR_ADDR 0x05FFFFAE
139#define RTCNT_ADDR 0x05FFFFB0
140#define RTCOR_ADDR 0x05FFFFB2
141
142#define TCSR_ADDR 0x05FFFFB8
143#define TCNT_ADDR 0x05FFFFB9
144#define RSTCSR_ADDR 0x05FFFFBB
145
146#define SBYCR_ADDR 0x05FFFFBC
147
148#define PADR_ADDR 0x05FFFFC0
149#define PBDR_ADDR 0x05FFFFC2
150#define PAIOR_ADDR 0x05FFFFC4
151#define PBIOR_ADDR 0x05FFFFC6
152#define PACR1_ADDR 0x05FFFFC8
153#define PACR2_ADDR 0x05FFFFCA
154#define PBCR1_ADDR 0x05FFFFCC
155#define PBCR2_ADDR 0x05FFFFCE
156#define PCDR_ADDR 0x05FFFFD0
157
158#define CASCR_ADDR 0x05FFFFEE
159
160
161/* register macros for direct access: */
162
163#define SMR0 (*((volatile unsigned char*)SMR0_ADDR))
164#define BRR0 (*((volatile unsigned char*)BRR0_ADDR))
165#define SCR0 (*((volatile unsigned char*)SCR0_ADDR))
166#define TDR0 (*((volatile unsigned char*)TDR0_ADDR))
167#define SSR0 (*((volatile unsigned char*)SSR0_ADDR))
168#define RDR0 (*((volatile unsigned char*)RDR0_ADDR))
169#define SMR1 (*((volatile unsigned char*)SMR1_ADDR))
170#define BRR1 (*((volatile unsigned char*)BRR1_ADDR))
171#define SCR1 (*((volatile unsigned char*)SCR1_ADDR))
172#define TDR1 (*((volatile unsigned char*)TDR1_ADDR))
173#define SSR1 (*((volatile unsigned char*)SSR1_ADDR))
174#define RDR1 (*((volatile unsigned char*)RDR1_ADDR))
175
176#define ADDRA (*((volatile unsigned short*)ADDRA_ADDR))
177#define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR))
178#define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR))
179#define ADDRB (*((volatile unsigned short*)ADDRB_ADDR))
180#define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR))
181#define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR))
182#define ADDRC (*((volatile unsigned short*)ADDRC_ADDR))
183#define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR))
184#define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR))
185#define ADDRD (*((volatile unsigned short*)ADDRD_ADDR))
186#define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR))
187#define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR))
188#define ADCSR (*((volatile unsigned char*)ADCSR_ADDR))
189#define ADCR (*((volatile unsigned char*)ADCR_ADDR))
190
191#define TSTR (*((volatile unsigned char*)TSTR_ADDR))
192#define TSNC (*((volatile unsigned char*)TSNC_ADDR))
193#define TMDR (*((volatile unsigned char*)TMDR_ADDR))
194#define TFCR (*((volatile unsigned char*)TFCR_ADDR))
195#define TCR0 (*((volatile unsigned char*)TCR0_ADDR))
196#define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR))
197#define TIER0 (*((volatile unsigned char*)TIER0_ADDR))
198#define TSR0 (*((volatile unsigned char*)TSR0_ADDR))
199#define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR))
200#define GRA0 (*((volatile unsigned short*)GRA0_ADDR))
201#define GRB0 (*((volatile unsigned short*)GRB0_ADDR))
202#define TCR1 (*((volatile unsigned char*)TCR1_ADDR))
203#define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR))
204#define TIER1 (*((volatile unsigned char*)TIER1_ADDR))
205#define TSR1 (*((volatile unsigned char*)TSR1_ADDR))
206#define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR))
207#define GRA1 (*((volatile unsigned short*)GRA_ADDR))1
208#define GRB1 (*((volatile unsigned short*)GRB1_ADDR))
209#define TCR2 (*((volatile unsigned char*)TCR2_ADDR))
210#define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR))
211#define TIER2 (*((volatile unsigned char*)TIER2_ADDR))
212#define TSR2 (*((volatile unsigned char*)TSR2_ADDR))
213#define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR))
214#define GRA2 (*((volatile unsigned short*)GRA2_ADDR))
215#define GRB2 (*((volatile unsigned short*)GRB2_ADDR))
216#define TCR3 (*((volatile unsigned char*)TCR3_ADDR))
217#define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR))
218#define TIER3 (*((volatile unsigned char*)TIER3_ADDR))
219#define TSR3 (*((volatile unsigned char*)TSR3_ADDR))
220#define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR))
221#define GRA3 (*((volatile unsigned short*)GRA3_ADDR))
222#define GRB3 (*((volatile unsigned short*)GRB3_ADDR))
223#define BRA3 (*((volatile unsigned short*)BRA3_ADDR))
224#define BRB3 (*((volatile unsigned short*)BRB3_ADDR))
225#define TOCR (*((volatile unsigned char*)TOCR_ADDR))
226#define TCR4 (*((volatile unsigned char*)TCR4_ADDR))
227#define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR))
228#define TIER4 (*((volatile unsigned char*)TIER4_ADDR))
229#define TSR4 (*((volatile unsigned char*)TSR4_ADDR))
230#define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR))
231#define GRA4 (*((volatile unsigned short*)GRA4_ADDR))
232#define GRB4 (*((volatile unsigned short*)GRB4_ADDR))
233#define BRA4 (*((volatile unsigned short*)BRA4_ADDR))
234#define BRB4 (*((volatile unsigned short*)BRB4_ADDR))
235
236#define SAR0 (*((volatile unsigned long*)SAR0_ADDR))
237#define DAR0 (*((volatile unsigned long*)DAR0_ADDR))
238#define DMAOR (*((volatile unsigned long*)DMAOR_ADDR))
239#define TCR0 (*((volatile unsigned long*)TCR0_ADDR))
240#define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR))
241#define SAR1 (*((volatile unsigned long*)SAR1_ADDR))
242#define DAR1 (*((volatile unsigned long*)DAR1_ADDR))
243#define TCR1 (*((volatile unsigned long*)TCR1_ADDR))
244#define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR))
245#define SAR2 (*((volatile unsigned long*)SAR2_ADDR))
246#define DAR2 (*((volatile unsigned long*)DAR2_ADDR))
247#define TCR2 (*((volatile unsigned long*)TCR2_ADDR))
248#define HCR2 (*((volatile unsigned short*)CHCR2_ADDR))
249#define SAR3 (*((volatile unsigned long*)SAR3_ADDR))
250#define DAR3 (*((volatile unsigned long*)DAR3_ADDR))
251#define TCR3 (*((volatile unsigned long*)TCR3_ADDR))
252#define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR))
253
254#define IPRA (*((volatile unsigned short*)IPRA_ADDR))
255#define IPRB (*((volatile unsigned short*)IPRB_ADDR))
256#define IPRC (*((volatile unsigned short*)IPRC_ADDR))
257#define IPRD (*((volatile unsigned short*)IPRD_ADDR))
258#define IPRE (*((volatile unsigned short*)IPRE_ADDR))
259#define ICR (*((volatile unsigned short*)ICR_ADDR))
260
261#define BARH (*((volatile unsigned short*)BARH_ADDR))
262#define BARL (*((volatile unsigned short*)BARL_ADDR))
263#define BAMRH (*((volatile unsigned short*)BAMRH_ADDR))
264#define BAMRL (*((volatile unsigned short*)BAMRL_ADDR))
265#define BBR (*((volatile unsigned short*)BBR_ADDR))
266
267#define BCR (*((volatile unsigned short*)BCR_ADDR))
268#define WCR1 (*((volatile unsigned short*)WCR1_ADDR))
269#define WCR2 (*((volatile unsigned short*)WCR2_ADDR))
270#define WCR3 (*((volatile unsigned short*)WCR3_ADDR))
271#define DCR (*((volatile unsigned short*)DCR_ADDR))
272#define PCR (*((volatile unsigned short*)PCR_ADDR))
273#define RCR (*((volatile unsigned short*)RCR_ADDR))
274#define RTCSR (*((volatile unsigned short*)RTCSR_ADDR))
275#define RTCNT (*((volatile unsigned short*)RTCNT_ADDR))
276#define RTCOR (*((volatile unsigned short*)RTCOR_ADDR))
277
278#define TCSR (*((volatile unsigned char*)TCSR_ADDR))
279#define TCNT (*((volatile unsigned char*)TCNT_ADDR))
280#define RSTCSR (*((volatile unsigned char*)RSTCSR_ADDR))
281
282#define SBYCR (*((volatile unsigned char*)SBYCR_ADDR))
283
284#define PADR (*((volatile unsigned short*)PADR_ADDR))
285#define PBDR (*((volatile unsigned short*)PBDR_ADDR))
286#define PAIOR (*((volatile unsigned short*)PAIOR_ADDR))
287#define PBIOR (*((volatile unsigned short*)PBIOR_ADDR))
288#define PACR1 (*((volatile unsigned short*)PACR1_ADDR))
289#define PACR2 (*((volatile unsigned short*)PACR2_ADDR))
290#define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR))
291#define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR))
292#define PCDR (*((volatile unsigned short*)PCDR_ADDR))
293
294#define CASCR (*((volatile unsigned char*)CASCR_ADDR))
166 295
167#endif 296#endif
diff --git a/firmware/system.c b/firmware/system.c
index 0769ac7b45..de45c3785a 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -142,166 +142,169 @@ reserve_interrupt ( 108);
142default_interrupt (ADITI, 109); 142default_interrupt (ADITI, 109);
143 143
144void (*vbr[]) (void) __attribute__ ((section (".sram.vbr"))) = 144void (*vbr[]) (void) __attribute__ ((section (".sram.vbr"))) =
145 { 145{
146 /*** 0-1 Power-on Reset ***/ 146 /*** 0-1 Power-on Reset ***/
147 147
148 reset_pc,reset_sp, 148 reset_pc,reset_sp,
149 149
150 /*** 2-3 Manual Reset ***/ 150 /*** 2-3 Manual Reset ***/
151 151
152 reset_pc,reset_sp, 152 reset_pc,reset_sp,
153 153
154 /*** 4 General Illegal Instruction ***/ 154 /*** 4 General Illegal Instruction ***/
155 155
156 GII, 156 GII,
157 157
158 /*** 5 Reserved ***/ 158 /*** 5 Reserved ***/
159 159
160 UIE5, 160 UIE5,
161 161
162 /*** 6 Illegal Slot Instruction ***/ 162 /*** 6 Illegal Slot Instruction ***/
163 163
164 ISI, 164 ISI,
165 165
166 /*** 7-8 Reserved ***/ 166 /*** 7-8 Reserved ***/
167 167
168 UIE7,UIE8, 168 UIE7,UIE8,
169 169
170 /*** 9 CPU Address Error ***/ 170 /*** 9 CPU Address Error ***/
171 171
172 CPUAE, 172 CPUAE,
173 173
174 /*** 10 DMA Address Error ***/ 174 /*** 10 DMA Address Error ***/
175 175
176 DMAAE, 176 DMAAE,
177 177
178 /*** 11 NMI ***/ 178 /*** 11 NMI ***/
179 179
180 NMI, 180 NMI,
181 181
182 /*** 12 User Break ***/ 182 /*** 12 User Break ***/
183 183
184 UB, 184 UB,
185 185
186 /*** 13-31 Reserved ***/ 186 /*** 13-31 Reserved ***/
187 187
188 UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31, 188 UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
189 189
190 /*** 32-63 TRAPA #20...#3F ***/ 190 /*** 32-63 TRAPA #20...#3F ***/
191 191
192 TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63, 192 TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
193 193
194 /*** 64-71 IRQ0-7 ***/ 194 /*** 64-71 IRQ0-7 ***/
195 195
196 IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7, 196 IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
197 197
198 /*** 72 DMAC0 ***/ 198 /*** 72 DMAC0 ***/
199 199
200 DEI0, 200 DEI0,
201 201
202 /*** 73 Reserved ***/ 202 /*** 73 Reserved ***/
203 203
204 UIE73, 204 UIE73,
205 205
206 /*** 74 DMAC1 ***/ 206 /*** 74 DMAC1 ***/
207 207
208 DEI1, 208 DEI1,
209 209
210 /*** 75 Reserved ***/ 210 /*** 75 Reserved ***/
211 211
212 UIE75, 212 UIE75,
213 213
214 /*** 76 DMAC2 ***/ 214 /*** 76 DMAC2 ***/
215 215
216 DEI2, 216 DEI2,
217 217
218 /*** 77 Reserved ***/ 218 /*** 77 Reserved ***/
219 219
220 UIE77, 220 UIE77,
221 221
222 /*** 78 DMAC3 ***/ 222 /*** 78 DMAC3 ***/
223 223
224 DEI3, 224 DEI3,
225 225
226 /*** 79 Reserved ***/ 226 /*** 79 Reserved ***/
227 227
228 UIE79, 228 UIE79,
229 229
230 /*** 80-82 ITU0 ***/ 230 /*** 80-82 ITU0 ***/
231 231
232 IMIA0,IMIB0,OVI0, 232 IMIA0,IMIB0,OVI0,
233 233
234 /*** 83 Reserved ***/ 234 /*** 83 Reserved ***/
235 235
236 UIE83, 236 UIE83,
237 237
238 /*** 84-86 ITU1 ***/ 238 /*** 84-86 ITU1 ***/
239 239
240 IMIA1,IMIB1,OVI1, 240 IMIA1,IMIB1,OVI1,
241 241
242 /*** 87 Reserved ***/ 242 /*** 87 Reserved ***/
243 243
244 UIE87, 244 UIE87,
245 245
246 /*** 88-90 ITU2 ***/ 246 /*** 88-90 ITU2 ***/
247 247
248 IMIA2,IMIB2,OVI2, 248 IMIA2,IMIB2,OVI2,
249 249
250 /*** 91 Reserved ***/ 250 /*** 91 Reserved ***/
251 251
252 UIE91, 252 UIE91,
253 253
254 /*** 92-94 ITU3 ***/ 254 /*** 92-94 ITU3 ***/
255 255
256 IMIA3,IMIB3,OVI3, 256 IMIA3,IMIB3,OVI3,
257 257
258 /*** 95 Reserved ***/ 258 /*** 95 Reserved ***/
259 259
260 UIE95, 260 UIE95,
261 261
262 /*** 96-98 ITU4 ***/ 262 /*** 96-98 ITU4 ***/
263 263
264 IMIA4,IMIB4,OVI4, 264 IMIA4,IMIB4,OVI4,
265 265
266 /*** 99 Reserved ***/ 266 /*** 99 Reserved ***/
267 267
268 UIE99, 268 UIE99,
269 269
270 /*** 100-103 SCI0 ***/ 270 /*** 100-103 SCI0 ***/
271 271
272 REI0,RXI0,TXI0,TEI0, 272 REI0,RXI0,TXI0,TEI0,
273 273
274 /*** 104-107 SCI1 ***/ 274 /*** 104-107 SCI1 ***/
275 275
276 REI1,RXI1,TXI1,TEI1, 276 REI1,RXI1,TXI1,TEI1,
277 277
278 /*** 108 Parity Control Unit ***/ 278 /*** 108 Parity Control Unit ***/
279 279
280 UIE108, 280 UIE108,
281 281
282 /*** 109 AD Converter ***/ 282 /*** 109 AD Converter ***/
283 283
284 ADITI 284 ADITI
285 285
286 }; 286};
287 287
288 288
289void system_reboot (void) 289void system_reboot (void)
290 { 290{
291 cli (); 291 cli ();
292 292
293 asm volatile ("ldc\t%0,vbr" : : "r"(0)); 293 asm volatile ("ldc\t%0,vbr" : : "r"(0));
294 294
295 SI(INTCIPRAB) = 295 IPRA = 0;
296 SI(INTCIPRCD) = 0; 296 IPRB = 0;
297 HI(INTCIPRE) = 297 IPRC = 0;
298 HI(INTCICR) = 0; 298 IPRD = 0;
299 IPRE = 0;
300 ICR = 0;
299 301
300 asm volatile ("jmp @%0; mov.l @%1,r15" : : "r"(SI(0)),"r"(4)); 302 asm volatile ("jmp @%0; mov.l @%1,r15" : :
301 } 303 "r"(*(char*)0),"r"(4));
304}
302 305
303void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */ 306void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
304 { 307{
305 unsigned int i,n; 308 unsigned int i,n;
306 lcd_stop (); 309 lcd_stop ();
307 asm volatile ("sts\tpr,%0" : "=r"(n)); 310 asm volatile ("sts\tpr,%0" : "=r"(n));
@@ -314,121 +317,121 @@ void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
314 lcd_stop (); 317 lcd_stop ();
315 318
316 while (1) 319 while (1)
317 { 320 {
318 led_toggle (); 321 led_toggle ();
319 322
320 for (i = 0; i < 240000; ++i); 323 for (i = 0; i < 240000; ++i);
321 } 324 }
322 } 325}
323 326
324asm ( 327asm (
325 "_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 328 "_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
326 "_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 329 "_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
327 "_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 330 "_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
328 "_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 331 "_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
329 "_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 332 "_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
330 "_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 333 "_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
331 "_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 334 "_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
332 "_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 335 "_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
333 "_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 336 "_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
334 "_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 337 "_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
335 "_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 338 "_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
336 "_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 339 "_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
337 "_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 340 "_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
338 "_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 341 "_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
339 "_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 342 "_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
340 "_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 343 "_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
341 "_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 344 "_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
342 "_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 345 "_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
343 "_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 346 "_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
344 "_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 347 "_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
345 "_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 348 "_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
346 "_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 349 "_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
347 "_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 350 "_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
348 "_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 351 "_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
349 "_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 352 "_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
350 "_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 353 "_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
351 "_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 354 "_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
352 "_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 355 "_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
353 "_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 356 "_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
354 "_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 357 "_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
355 "_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 358 "_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
356 "_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 359 "_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
357 "_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 360 "_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
358 "_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 361 "_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
359 "_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 362 "_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
360 "_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 363 "_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
361 "_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 364 "_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
362 "_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 365 "_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
363 "_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 366 "_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
364 "_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 367 "_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
365 "_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 368 "_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
366 "_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 369 "_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
367 "_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 370 "_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
368 "_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 371 "_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
369 "_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 372 "_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
370 "_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 373 "_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
371 "_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 374 "_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
372 "_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 375 "_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
373 "_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 376 "_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
374 "_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 377 "_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
375 "_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 378 "_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
376 "_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 379 "_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
377 "_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 380 "_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
378 "_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 381 "_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
379 "_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 382 "_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
380 "_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 383 "_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
381 "_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 384 "_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
382 "_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 385 "_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
383 "_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 386 "_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
384 "_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 387 "_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
385 "_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 388 "_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
386 "_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 389 "_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
387 "_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 390 "_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
388 "_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 391 "_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
389 "_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 392 "_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
390 "_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 393 "_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
391 "_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 394 "_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
392 "_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 395 "_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
393 "_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 396 "_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
394 "_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 397 "_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
395 "_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 398 "_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
396 "_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 399 "_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
397 "_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 400 "_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
398 "_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 401 "_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
399 "_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 402 "_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
400 "_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 403 "_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
401 "_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 404 "_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
402 "_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 405 "_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
403 "_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 406 "_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
404 "_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 407 "_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
405 "_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 408 "_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
406 "_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 409 "_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
407 "_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 410 "_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
408 "_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 411 "_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
409 "_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 412 "_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
410 "_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 413 "_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
411 "_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 414 "_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
412 "_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 415 "_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
413 "_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 416 "_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
414 "_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 417 "_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
415 "_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 418 "_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
416 "_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 419 "_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
417 "_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 420 "_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
418 "_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 421 "_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
419 "_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 422 "_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
420 "_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 423 "_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
421 "_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 424 "_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
422 "_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 425 "_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
423 "_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 426 "_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
424 "_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 427 "_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
425 "_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 428 "_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
426 "_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 429 "_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
427 "_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 430 "_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
428 "_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 431 "_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
429 "_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 432 "_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
430 "_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 433 "_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
431 "_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 434 "_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
432 "_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 435 "_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
433 "_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" 436 "_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
434 "_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4"); 437 "_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
diff --git a/firmware/system.h b/firmware/system.h
index 7495f3a889..88c8449df4 100644
--- a/firmware/system.h
+++ b/firmware/system.h
@@ -21,36 +21,17 @@
21#define __SYSTEM_H__ 21#define __SYSTEM_H__
22#include <sh7034.h> 22#include <sh7034.h>
23 23
24#define KB *1024
25#define MB *1024 KB
26#define GB *1024 MB
27
28#define Hz *1
29#define KHz *1000 Hz
30#define MHz *1000 KHz
31
32#define ns *1
33#define us *1000 ns
34#define ms *1000 us
35
36/* 24/*
37 * 11.059,200 MHz => 90.4224537037037037037037037037037... ns 25 * 11.059,200 MHz => 90.4224537037037037037037037037037... ns
38 * 12.000,000 MHz => 83.3333333333333333333333333333333... ns 26 * 12.000,000 MHz => 83.3333333333333333333333333333333... ns
39 */ 27 */
40 28
41#define PHI ((int)(12.000000 MHz)) 29#define FREQ 12000000
42#define BAUDRATE 9600 30#define BAUDRATE 9600
43 31
44//#define PHI ((int)(11.059200 MHz)) 32//#define PHI ((int)(11.059200 MHz))
45//#define BAUDRATE 115200 /* 115200 - 9600 */ 33//#define BAUDRATE 115200 /* 115200 - 9600 */
46 34
47#define SI(a) \
48 (*((volatile int *)a)) /* single integer access - 32-bit */
49#define HI(a) \
50 (*((volatile short *)a)) /* half integer access - 16-bit */
51#define QI(a) \
52 (*((volatile char *)a)) /* quarter integer access - 8-bit */
53
54#define nop \ 35#define nop \
55 asm volatile ("nop") 36 asm volatile ("nop")
56 37
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-24 14:28:43 +0000