diff options
-rw-r--r-- | firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c index 36f653a9dd..47abb9d46a 100644 --- a/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c +++ b/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c | |||
@@ -87,14 +87,14 @@ static void enable_mmu(void) { | |||
87 | /* Invalidate DCache for this range */ | 87 | /* Invalidate DCache for this range */ |
88 | /* Will do write back */ | 88 | /* Will do write back */ |
89 | void invalidate_dcache_range(const void *base, unsigned int size) { | 89 | void invalidate_dcache_range(const void *base, unsigned int size) { |
90 | unsigned int addr = ((int) base) & ~31; | 90 | unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/ |
91 | unsigned int end = addr+size+32; | 91 | unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */ |
92 | asm volatile( | 92 | asm volatile( |
93 | "inv_start: \n" | 93 | "inv_start: \n" |
94 | "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | 94 | "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ |
95 | "add %0, %0, #32 \n" | 95 | "add %0, %0, #32 \n" |
96 | "cmp %0, %1 \n" | 96 | "cmp %0, %1 \n" |
97 | "ble inv_start \n" | 97 | "bne inv_start \n" |
98 | "mov %0, #0\n" | 98 | "mov %0, #0\n" |
99 | "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */ | 99 | "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */ |
100 | : : "r" (addr), "r" (end)); | 100 | : : "r" (addr), "r" (end)); |
@@ -105,7 +105,7 @@ void invalidate_dcache_range(const void *base, unsigned int size) { | |||
105 | void clean_dcache_range(const void *base, unsigned int size) { | 105 | void clean_dcache_range(const void *base, unsigned int size) { |
106 | unsigned int addr = (int) base; | 106 | unsigned int addr = (int) base; |
107 | unsigned int end = addr+size+32; | 107 | unsigned int end = addr+size+32; |
108 | asm volatile( | 108 | asm volatile( |
109 | "bic %0, %0, #31 \n" | 109 | "bic %0, %0, #31 \n" |
110 | "clean_start: \n" | 110 | "clean_start: \n" |
111 | "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | 111 | "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ |
@@ -123,18 +123,16 @@ void dump_dcache_range(const void *base, unsigned int size) { | |||
123 | unsigned int addr = (int) base; | 123 | unsigned int addr = (int) base; |
124 | unsigned int end = addr+size; | 124 | unsigned int end = addr+size; |
125 | asm volatile( | 125 | asm volatile( |
126 | "tst %0, #31 \n" | 126 | "tst %0, #31 \n" /* Check to see if low five bits are set */ |
127 | "bic %0, %0, #31 \n" | 127 | "bic %0, %0, #31 \n" /* Clear them */ |
128 | "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | 128 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */ |
129 | "add %0, %0, #32 \n" | 129 | "add %0, %0, #32 \n" /* Move to the next cache line */ |
130 | "tst %1, #31 \n" | 130 | "tst %1, #31 \n" /* Check last line for bits set */ |
131 | "bic %1, %1, #31 \n" | 131 | "bic %1, %1, #31 \n" /* Clear those bits */ |
132 | "mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */ | 132 | "mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */ |
133 | "cmp %0, %1 \n" | ||
134 | "beq dump_end \n" | ||
135 | "dump_start: \n" | 133 | "dump_start: \n" |
136 | "mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */ | 134 | "mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */ |
137 | "add %0, %0, #32 \n" | 135 | "add %0, %0, #32 \n" /* Next cache line */ |
138 | "cmp %0, %1 \n" | 136 | "cmp %0, %1 \n" |
139 | "bne dump_start \n" | 137 | "bne dump_start \n" |
140 | "dump_end: \n" | 138 | "dump_end: \n" |