diff options
-rwxr-xr-x | firmware/export/imx31l.h | 263 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/button-imx31.c | 247 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/spi-imx31.c | 2 |
3 files changed, 382 insertions, 130 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index b10fc1ea17..e2ee7762f4 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -105,6 +105,261 @@ | |||
105 | #define WDOG1_BASE_ADDR WDOG_BASE_ADDR | 105 | #define WDOG1_BASE_ADDR WDOG_BASE_ADDR |
106 | #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR | 106 | #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR |
107 | 107 | ||
108 | /* IOMUXC */ | ||
109 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) | ||
110 | |||
111 | /* GPR */ | ||
112 | #define IOMUXC_GPR IOMUXC_(0x008) | ||
113 | |||
114 | /* SW_MUX_CTL */ | ||
115 | #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C) | ||
116 | #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010) | ||
117 | #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014) | ||
118 | #define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 IOMUXC_(0x018) | ||
119 | #define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x01C) | ||
120 | #define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS IOMUXC_(0x020) | ||
121 | #define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ IOMUXC_(0x024) | ||
122 | #define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x028) | ||
123 | #define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I IOMUXC_(0x02C) | ||
124 | #define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 IOMUXC_(0x030) | ||
125 | #define SW_MUX_CTL_LD11_LD12_LD13_LD14 IOMUXC_(0x034) | ||
126 | #define SW_MUX_CTL_LD7_LD8_LD9_LD10 IOMUXC_(0x038) | ||
127 | #define SW_MUX_CTL_LD3_LD4_LD5_LD6 IOMUXC_(0x03C) | ||
128 | #define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 IOMUXC_(0x040) | ||
129 | #define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 IOMUXC_(0x044) | ||
130 | #define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK IOMUXC_(0x048) | ||
131 | #define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x04C) | ||
132 | #define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 IOMUXC_(0x050) | ||
133 | #define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK IOMUXC_(0x054) | ||
134 | #define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD IOMUXC_(0x058) | ||
135 | #define SW_MUX_CTL_RTCK_TCK_TMS_TDI IOMUXC_(0x05C) | ||
136 | #define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 IOMUXC_(0x060) | ||
137 | #define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x064) | ||
138 | #define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 IOMUXC_(0x068) | ||
139 | #define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 IOMUXC_(0x06C) | ||
140 | #define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE IOMUXC_(0x070) | ||
141 | #define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 IOMUXC_(0x074) | ||
142 | #define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 IOMUXC_(0x078) | ||
143 | #define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x07C) | ||
144 | #define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 IOMUXC_(0x080) | ||
145 | #define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 IOMUXC_(0x084) | ||
146 | #define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x088) | ||
147 | #define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 IOMUXC_(0x08C) | ||
148 | #define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 IOMUXC_(0x090) | ||
149 | #define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 IOMUXC_(0x094) | ||
150 | #define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 IOMUXC_(0x098) | ||
151 | #define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 IOMUXC_(0x09C) | ||
152 | #define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x0A0) | ||
153 | #define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC IOMUXC_(0x0A4) | ||
154 | #define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 IOMUXC_(0x0A8) | ||
155 | #define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x0AC) | ||
156 | #define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 IOMUXC_(0x0B0) | ||
157 | #define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE IOMUXC_(0x0B4) | ||
158 | #define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x0B8) | ||
159 | #define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON IOMUXC_(0x0BC) | ||
160 | #define SW_MUX_CTL_D2_D1_D0_PC_CD1_B IOMUXC_(0x0C0) | ||
161 | #define SW_MUX_CTL_D6_D5_D4_D3 IOMUXC_(0x0C4) | ||
162 | #define SW_MUX_CTL_D10_D9_D8_D7 IOMUXC_(0x0C8) | ||
163 | #define SW_MUX_CTL_D14_D13_D12_D11 IOMUXC_(0x0CC) | ||
164 | #define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 IOMUXC_(0x0D0) | ||
165 | #define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE IOMUXC_(0x0D4) | ||
166 | #define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 IOMUXC_(0x0D8) | ||
167 | #define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x0DC) | ||
168 | #define SW_MUX_CTL_RW_RAS_CAS_SDWE IOMUXC_(0x0E0) | ||
169 | #define SW_MUX_CTL_CS5_ECB_LBA_BCLK IOMUXC_(0x0E4) | ||
170 | #define SW_MUX_CTL_CS1_CS2_CS3_CS4 IOMUXC_(0x0E8) | ||
171 | #define SW_MUX_CTL_EB0_EB1_OE_CS0 IOMUXC_(0x0EC) | ||
172 | #define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 IOMUXC_(0x0F0) | ||
173 | #define SW_MUX_CTL_SD28_SD29_SD30_SD31 IOMUXC_(0x0F4) | ||
174 | #define SW_MUX_CTL_SD24_SD25_SD26_SD27 IOMUXC_(0x0F8) | ||
175 | #define SW_MUX_CTL_SD20_SD21_SD22_SD23 IOMUXC_(0x0FC) | ||
176 | #define SW_MUX_CTL_SD16_SD17_SD18_SD19 IOMUXC_(0x100) | ||
177 | #define SW_MUX_CTL_SD12_SD13_SD14_SD15 IOMUXC_(0x104) | ||
178 | #define SW_MUX_CTL_SD8_SD9_SD10_SD11 IOMUXC_(0x108) | ||
179 | #define SW_MUX_CTL_SD4_SD5_SD6_SD7 IOMUXC_(0x10C) | ||
180 | #define SW_MUX_CTL_SD0_SD1_SD2_SD3 IOMUXC_(0x110) | ||
181 | #define SW_MUX_CTL_A24_A25_SDBA1_SDBA0 IOMUXC_(0x114) | ||
182 | #define SW_MUX_CTL_A20_A21_A22_A23 IOMUXC_(0x118) | ||
183 | #define SW_MUX_CTL_A16_A17_A18_A19 IOMUXC_(0x11C) | ||
184 | #define SW_MUX_CTL_A12_A13_A14_A15 IOMUXC_(0x120) | ||
185 | #define SW_MUX_CTL_A9_A10_MA10_A11 IOMUXC_(0x124) | ||
186 | #define SW_MUX_CTL_A5_A6_A7_A8 IOMUXC_(0x128) | ||
187 | #define SW_MUX_CTL_A1_A2_A3_A4 IOMUXC_(0x12C) | ||
188 | #define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 IOMUXC_(0x130) | ||
189 | #define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 IOMUXC_(0x134) | ||
190 | #define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 IOMUXC_(0x138) | ||
191 | #define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x13C) | ||
192 | #define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH IOMUXC_(0x140) | ||
193 | #define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 IOMUXC_(0x144) | ||
194 | #define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x148) | ||
195 | #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C) | ||
196 | #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150) | ||
197 | |||
198 | #define SW_MUX_OUT_EN_GPIO_DR 0x0 | ||
199 | #define SW_MUX_OUT_FUNCTIONAL 0x1 | ||
200 | #define SW_MUX_OUT_ALTERNATE_1 0x2 | ||
201 | #define SW_MUX_OUT_ALTERNATE_2 0x3 | ||
202 | #define SW_MUX_OUT_ALTERNATE_3 0x4 | ||
203 | #define SW_MUX_OUT_ALTERNATE_4 0x5 | ||
204 | #define SW_MUX_OUT_ALTERNATE_5 0x6 | ||
205 | #define SW_MUX_OUT_ALTERNATE_6 0x7 | ||
206 | |||
207 | #define SW_MUX_IN_NO_INPUTS 0x0 | ||
208 | #define SW_MUX_IN_GPIO_PSR_ISR 0x1 | ||
209 | #define SW_MUX_IN_FUNCTIONAL 0x2 | ||
210 | #define SW_MUX_IN_ALTERNATE_1 0x3 | ||
211 | #define SW_MUX_IN_ALTERNATE_2 0x4 | ||
212 | |||
213 | /* Shift above flags into one of the four fields in each register */ | ||
214 | #define SW_MUX_CTL_FLD_0(x) ((x) << 0) | ||
215 | #define SW_MUX_CTL_FLD_1(x) ((x) << 8) | ||
216 | #define SW_MUX_CTL_FLD_2(x) ((x) << 16) | ||
217 | #define SW_MUX_CTL_FLD_3(x) ((x) << 24) | ||
218 | |||
219 | /* SW_PAD_CTL */ | ||
220 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | ||
221 | #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158) | ||
222 | #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C) | ||
223 | #define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B IOMUXC_(0x160) | ||
224 | #define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR IOMUXC_(0x164) | ||
225 | #define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 IOMUXC_(0x168) | ||
226 | #define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x16C) | ||
227 | #define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL IOMUXC_(0x170) | ||
228 | #define SW_PAD_CTL_READ_VSYNC3_CONTRAST IOMUXC_(0x174) | ||
229 | #define SW_PAD_CTL_SER_RS_PAR_RS_WRITE IOMUXC_(0x178) | ||
230 | #define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x17C) | ||
231 | #define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO IOMUXC_(0x180) | ||
232 | #define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT IOMUXC_(0x184) | ||
233 | #define SW_PAD_CTL_LD15_LD16_LD17 IOMUXC_(0x188) | ||
234 | #define SW_PAD_CTL_LD12_LD13_LD14 IOMUXC_(0x18C) | ||
235 | #define SW_PAD_CTL_LD9_LD10_LD11 IOMUXC_(0x190) | ||
236 | #define SW_PAD_CTL_LD6_LD7_LD8 IOMUXC_(0x194) | ||
237 | #define SW_PAD_CTL_LD3_LD4_LD5 IOMUXC_(0x198) | ||
238 | #define SW_PAD_CTL_LD0_LD1_LD2 IOMUXC_(0x19C) | ||
239 | #define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 IOMUXC_(0x1A0) | ||
240 | #define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP IOMUXC_(0x1A4) | ||
241 | #define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 IOMUXC_(0x1A8) | ||
242 | #define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x1AC) | ||
243 | #define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 IOMUXC_(0x1B0) | ||
244 | #define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP IOMUXC_(0x1B4) | ||
245 | #define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP IOMUXC_(0x1B8) | ||
246 | #define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD IOMUXC_(0x1BC) | ||
247 | #define SW_PAD_CTL_TMS_TDI_TDO IOMUXC_(0x1C0) | ||
248 | #define SW_PAD_CTL_KEY_COL7_RTCK_TCK IOMUXC_(0x1C4) | ||
249 | #define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 IOMUXC_(0x1C8) | ||
250 | #define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x1CC) | ||
251 | #define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 IOMUXC_(0x1D0) | ||
252 | #define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 IOMUXC_(0x1D4) | ||
253 | #define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 IOMUXC_(0x1D8) | ||
254 | #define SW_PAD_CTL_RTS2_CTS2_BATT_LINE IOMUXC_(0x1DC) | ||
255 | #define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 IOMUXC_(0x1E0) | ||
256 | #define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 IOMUXC_(0x1E4) | ||
257 | #define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 IOMUXC_(0x1E8) | ||
258 | #define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x1EC) | ||
259 | #define SW_PAD_CTL_RXD1_TXD1_RTS1 IOMUXC_(0x1F0) | ||
260 | #define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY IOMUXC_(0x1F4) | ||
261 | #define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 IOMUXC_(0x1F8) | ||
262 | #define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x1FC) | ||
263 | #define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS IOMUXC_(0x200) | ||
264 | #define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO IOMUXC_(0x204) | ||
265 | #define SW_PAD_CTL_STXD6_SRXD6_SCK6 IOMUXC_(0x208) | ||
266 | #define SW_PAD_CTL_SRXD5_SCK5_SFS5 IOMUXC_(0x20C) | ||
267 | #define SW_PAD_CTL_SCK4_SFS4_STXD5 IOMUXC_(0x210) | ||
268 | #define SW_PAD_CTL_SFS3_STXD4_SRXD4 IOMUXC_(0x214) | ||
269 | #define SW_PAD_CTL_STXD3_SRXD3_SCK3 IOMUXC_(0x218) | ||
270 | #define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x21C) | ||
271 | #define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC IOMUXC_(0x220) | ||
272 | #define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 IOMUXC_(0x224) | ||
273 | #define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 IOMUXC_(0x228) | ||
274 | #define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x22C) | ||
275 | #define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 IOMUXC_(0x230) | ||
276 | #define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT IOMUXC_(0x234) | ||
277 | #define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B IOMUXC_(0x238) | ||
278 | #define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x23C) | ||
279 | #define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 IOMUXC_(0x240) | ||
280 | #define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B IOMUXC_(0x244) | ||
281 | #define SW_PAD_CTL_D2_D1_D0 IOMUXC_(0x248) | ||
282 | #define SW_PAD_CTL_D5_D4_D3 IOMUXC_(0x24C) | ||
283 | #define SW_PAD_CTL_D8_D7_D6 IOMUXC_(0x250) | ||
284 | #define SW_PAD_CTL_D11_D10_D9 IOMUXC_(0x254) | ||
285 | #define SW_PAD_CTL_D14_D13_D12 IOMUXC_(0x258) | ||
286 | #define SW_PAD_CTL_NFCE_B_NFRB_D15 IOMUXC_(0x25C) | ||
287 | #define SW_PAD_CTL_NFALE_NFCLE_NFWP_B IOMUXC_(0x260) | ||
288 | #define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B IOMUXC_(0x264) | ||
289 | #define SW_PAD_CTL_SDQS0_SDQS1_SDQS2 IOMUXC_(0x268) | ||
290 | #define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x26C) | ||
291 | #define SW_PAD_CTL_CAS_SDWE_SDCKE0 IOMUXC_(0x270) | ||
292 | #define SW_PAD_CTL_BCLK_RW_RAS IOMUXC_(0x274) | ||
293 | #define SW_PAD_CTL_CS5_ECB_LBA IOMUXC_(0x278) | ||
294 | #define SW_PAD_CTL_CS2_CS3_CS4 IOMUXC_(0x27C) | ||
295 | #define SW_PAD_CTL_OE_CS0_CS1 IOMUXC_(0x280) | ||
296 | #define SW_PAD_CTL_DQM3_EB0_EB1 IOMUXC_(0x284) | ||
297 | #define SW_PAD_CTL_DQM0_DQM1_DQM2 IOMUXC_(0x288) | ||
298 | #define SW_PAD_CTL_SD29_SD30_SD31 IOMUXC_(0x28C) | ||
299 | #define SW_PAD_CTL_SD26_SD27_SD28 IOMUXC_(0x290) | ||
300 | #define SW_PAD_CTL_SD23_SD24_SD25 IOMUXC_(0x294) | ||
301 | #define SW_PAD_CTL_SD20_SD21_SD22 IOMUXC_(0x298) | ||
302 | #define SW_PAD_CTL_SD17_SD18_SD19 IOMUXC_(0x29C) | ||
303 | #define SW_PAD_CTL_SD14_SD15_SD16 IOMUXC_(0x2A0) | ||
304 | #define SW_PAD_CTL_SD11_SD12_SD13 IOMUXC_(0x2A4) | ||
305 | #define SW_PAD_CTL_SD8_SD9_SD10 IOMUXC_(0x2A8) | ||
306 | #define SW_PAD_CTL_SD5_SD6_SD7 IOMUXC_(0x2AC) | ||
307 | #define SW_PAD_CTL_SD2_SD3_SD4 IOMUXC_(0x2B0) | ||
308 | #define SW_PAD_CTL_SDBA0_SD0_SD1 IOMUXC_(0x2B4) | ||
309 | #define SW_PAD_CTL_A24_A25_SDBA1 IOMUXC_(0x2B8) | ||
310 | #define SW_PAD_CTL_A21_A22_A23 IOMUXC_(0x2BC) | ||
311 | #define SW_PAD_CTL_A18_A19_A20 IOMUXC_(0x2C0) | ||
312 | #define SW_PAD_CTL_A15_A16_A17 IOMUXC_(0x2C4) | ||
313 | #define SW_PAD_CTL_A12_A13_A14 IOMUXC_(0x2C8) | ||
314 | #define SW_PAD_CTL_A10_MA10_A11 IOMUXC_(0x2CC) | ||
315 | #define SW_PAD_CTL_A7_A8_A9 IOMUXC_(0x2D0) | ||
316 | #define SW_PAD_CTL_A4_A5_A6 IOMUXC_(0x2D4) | ||
317 | #define SW_PAD_CTL_A1_A2_A3 IOMUXC_(0x2D8) | ||
318 | #define SW_PAD_CTL_VPG0_VPG1_A0 IOMUXC_(0x2DC) | ||
319 | #define SW_PAD_CTL_VSTBY_DVFS0_DVFS1 IOMUXC_(0x2E0) | ||
320 | #define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL IOMUXC_(0x2E4) | ||
321 | #define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 IOMUXC_(0x2E8) | ||
322 | #define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x2EC) | ||
323 | #define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B IOMUXC_(0x2F0) | ||
324 | #define SW_PAD_CTL_SVEN0_STX0_SRX0 IOMUXC_(0x2F4) | ||
325 | #define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 IOMUXC_(0x2F8) | ||
326 | #define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x2FC) | ||
327 | #define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 IOMUXC_(0x300) | ||
328 | #define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 IOMUXC_(0x304) | ||
329 | #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308) | ||
330 | |||
331 | /* SW_PAD_CTL flags */ | ||
332 | #define SW_PAD_CTL_LOOPBACK (1 << 9) | ||
333 | #define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER (0 << 7) | ||
334 | #if 0 /* Same as 0 */ | ||
335 | #define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER (1 << 7) | ||
336 | #endif | ||
337 | #define SW_PAD_CTL_ENABLE_KEEPER (2 << 7) | ||
338 | #define SW_PAD_CTL_ENABLE_PULL_UP_OR_PULL_DOWN (3 << 7) | ||
339 | #define SW_PAD_CTL_100K_PULL_DOWN (0 << 5) | ||
340 | #define SW_PAD_CTL_100K_PULL_UP (1 << 5) | ||
341 | #if 0 /* Completeness */ | ||
342 | #define SW_PAD_CTL_47K_PULL_UP (2 << 5) /* Not in IMX31/L */ | ||
343 | #define SW_PAD_CTL_22K_PULL_UP (3 << 5) /* Not in IMX31/L */ | ||
344 | #endif | ||
345 | #define SW_PAD_CTL_IPP_HYS_STD (0 << 4) | ||
346 | #define SW_PAD_CTL_IPP_HYS_SCHIMDT (1 << 4) | ||
347 | #define SW_PAD_CTL_IPP_ODE_CMOS (0 << 3) | ||
348 | #define SW_PAD_CTL_IPP_ODE_OPEN (1 << 3) | ||
349 | #define SW_PAD_CTL_IPP_DSE_STD (0 << 1) | ||
350 | #define SW_PAD_CTL_IPP_DSE_HIGH (1 << 1) | ||
351 | #define SW_PAD_CTL_IPP_DSE_MAX (2 << 1) | ||
352 | #if 0 /* Same as 2 */ | ||
353 | #define SW_PAD_CTL_IPP_DSE_MAX (3 << 1) | ||
354 | #endif | ||
355 | #define SW_PAD_CTL_IPP_SRE_SLOW (0 << 0) | ||
356 | #define SW_PAD_CTL_IPP_SRE_FAST (1 << 0) | ||
357 | |||
358 | /* Shift above flags into one of the three fields in each register */ | ||
359 | #define SW_PAD_CTL_FLD_0(x) ((x) << 0) | ||
360 | #define SW_PAD_CTL_FLD_1(x) ((x) << 10) | ||
361 | #define SW_PAD_CTL_FLD_2(x) ((x) << 20) | ||
362 | |||
108 | /* IPU */ | 363 | /* IPU */ |
109 | #define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00)) | 364 | #define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00)) |
110 | #define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04)) | 365 | #define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04)) |
@@ -272,6 +527,14 @@ | |||
272 | #define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4)) | 527 | #define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4)) |
273 | #define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6)) | 528 | #define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6)) |
274 | 529 | ||
530 | /* KPP_KPSR bits */ | ||
531 | #define KPP_KPSR_KRIE (1 << 9) | ||
532 | #define KPP_KPSR_KDIE (1 << 8) | ||
533 | #define KPP_KPSR_KRSS (1 << 3) | ||
534 | #define KPP_KPSR_KDSC (1 << 2) | ||
535 | #define KPP_KPSR_KPKR (1 << 1) | ||
536 | #define KPP_KPSR_KPKD (1 << 0) | ||
537 | |||
275 | /* ROMPATCH and AVIC */ | 538 | /* ROMPATCH and AVIC */ |
276 | #define ROMPATCH_BASE_ADDR 0x60000000 | 539 | #define ROMPATCH_BASE_ADDR 0x60000000 |
277 | 540 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c index eea0faa4eb..493ce3af3e 100644 --- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c | |||
@@ -21,156 +21,143 @@ | |||
21 | #include "cpu.h" | 21 | #include "cpu.h" |
22 | #include "system.h" | 22 | #include "system.h" |
23 | #include "button.h" | 23 | #include "button.h" |
24 | #include "kernel.h" | ||
25 | #include "backlight.h" | 24 | #include "backlight.h" |
26 | #include "adc.h" | ||
27 | #include "system.h" | 25 | #include "system.h" |
28 | #include "backlight-target.h" | 26 | #include "backlight-target.h" |
29 | #include "debug.h" | 27 | #include "avic-imx31.h" |
30 | #include "stdio.h" | ||
31 | 28 | ||
32 | /* Most code in here is taken from the Linux BSP provided by Freescale | 29 | /* Most code in here is taken from the Linux BSP provided by Freescale |
33 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. */ | 30 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. */ |
34 | 31 | ||
32 | static uint32_t int_btn = BUTTON_NONE; | ||
33 | static bool hold_button = false; | ||
34 | static bool hold_button_old = false; | ||
35 | #define _button_hold() (GPIO3_DR & 0x10) | ||
36 | |||
37 | static __attribute__((interrupt("IRQ"))) void KPP_HANDLER(void) | ||
38 | { | ||
39 | static const int key_mtx[5][3] = | ||
40 | { | ||
41 | { BUTTON_LEFT, BUTTON_BACK, BUTTON_VOL_UP }, | ||
42 | { BUTTON_UP, BUTTON_MENU, BUTTON_VOL_DOWN }, | ||
43 | { BUTTON_DOWN, BUTTON_NONE, BUTTON_PREV }, | ||
44 | { BUTTON_RIGHT, BUTTON_NONE, BUTTON_PLAY }, | ||
45 | { BUTTON_SELECT, BUTTON_NONE, BUTTON_NEXT }, | ||
46 | }; | ||
47 | |||
48 | unsigned short reg_val; | ||
49 | int col, row; | ||
50 | int i; | ||
51 | int button = BUTTON_NONE; | ||
52 | |||
53 | /* 1. Disable both (depress and release) keypad interrupts. */ | ||
54 | KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE); | ||
55 | |||
56 | for (col = 0; col < 3; col++) /* Col */ | ||
57 | { | ||
58 | /* 2. Write 1s to KPDR[10:8] setting column data to 1s */ | ||
59 | KPP_KPDR |= (0x7 << 8); | ||
60 | |||
61 | /* 3. Configure columns as totem pole outputs(for quick | ||
62 | * discharging of keypad capacitance) */ | ||
63 | KPP_KPCR &= ~(0x7 << 8); | ||
64 | |||
65 | /* Give the columns time to discharge */ | ||
66 | for (i = 0; i < 256; i++) | ||
67 | asm volatile (""); | ||
68 | |||
69 | /* 4. Configure columns as open-drain */ | ||
70 | KPP_KPCR |= (0x7 << 8); | ||
71 | |||
72 | /* 5. Write a single column to 0, others to 1. | ||
73 | * 6. Sample row inputs and save data. Multiple key presses | ||
74 | * can be detected on a single column. | ||
75 | * 7. Repeat steps 2 - 6 for remaining columns. */ | ||
76 | |||
77 | /* Col bit starts at 8th bit in KPDR */ | ||
78 | KPP_KPDR &= ~(1 << (8 + col)); | ||
79 | |||
80 | /* Delay added to avoid propagating the 0 from column to row | ||
81 | * when scanning. */ | ||
82 | for (i = 0; i < 256; i++) | ||
83 | asm volatile (""); | ||
84 | |||
85 | /* Read row input */ | ||
86 | reg_val = KPP_KPDR; | ||
87 | for (row = 0; row < 5; row++) /* sample row */ | ||
88 | { | ||
89 | if (!(reg_val & (1 << row))) | ||
90 | button |= key_mtx[row][col]; | ||
91 | } | ||
92 | } | ||
93 | |||
94 | /* 8. Return all columns to 0 in preparation for standby mode. */ | ||
95 | KPP_KPDR &= ~(0x7 << 8); | ||
96 | |||
97 | /* 9. Clear KPKD and KPKR status bit(s) by writing to a .1., | ||
98 | * set the KPKR synchronizer chain by writing "1" to KRSS register, | ||
99 | * clear the KPKD synchronizer chain by writing "1" to KDSC register */ | ||
100 | KPP_KPSR = KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKR | KPP_KPSR_KPKD; | ||
101 | |||
102 | /* 10. Re-enable the appropriate keypad interrupt(s) so that the KDIE | ||
103 | * detects a key hold condition, or the KRIE detects a key-release | ||
104 | * event. */ | ||
105 | if (int_btn != BUTTON_NONE) | ||
106 | KPP_KPSR |= KPP_KPSR_KRIE; | ||
107 | else | ||
108 | KPP_KPSR |= KPP_KPSR_KDIE; | ||
109 | |||
110 | int_btn = button; | ||
111 | } | ||
112 | |||
35 | void button_init_device(void) | 113 | void button_init_device(void) |
36 | { | 114 | { |
37 | unsigned int reg_val; | ||
38 | /* Enable keypad clock */ | 115 | /* Enable keypad clock */ |
39 | CLKCTL_CGR1 |= (3 << 2*10); | 116 | CLKCTL_CGR1 |= (3 << 2*10); |
40 | 117 | ||
41 | /* Enable number of rows in keypad (KPCR[7:0]) | 118 | /* 1. Enable number of rows in keypad (KPCR[4:0]) |
42 | * Configure keypad columns as open-drain (KPCR[15:8]) | ||
43 | * | 119 | * |
44 | * Configure the rows/cols in KPP | 120 | * Configure the rows/cols in KPP |
45 | * LSB nibble in KPP is for 8 rows | 121 | * LSB nybble in KPP is for 5 rows |
46 | * MSB nibble in KPP is for 8 cols | 122 | * MSB nybble in KPP is for 3 cols */ |
47 | */ | 123 | KPP_KPCR |= 0x1f; |
48 | #if 0 | 124 | |
49 | KPP_KPCR = (0xff << 8) | 0xff; | 125 | /* 2. Write 0's to KPDR[10:8] */ |
50 | /* Write 0's to KPDR[15:8] */ | 126 | KPP_KPDR &= ~(0x7 << 8); |
51 | reg_val = KPP_KPDR; | 127 | |
52 | reg_val &= 0x00ff; | 128 | /* 3. Configure the keypad columns as open-drain (KPCR[10:8]). */ |
53 | KPP_KPDR = reg_val; | 129 | KPP_KPCR |= (0x7 << 8); |
54 | 130 | ||
55 | /* Configure columns as output, rows as input (KDDR[15:0]) */ | 131 | /* 4. Configure columns as output, rows as input (KDDR[10:8,4:0]) */ |
56 | KPP_KDDR = 0xff00; | 132 | KPP_KDDR = (KPP_KDDR | (0x7 << 8)) & ~0x1f; |
57 | #endif | 133 | |
58 | 134 | /* 5. Clear the KPKD Status Flag and Synchronizer chain. | |
59 | KPP_KPSR = (1 << 3) | (1 << 2); | 135 | * 6. Set the KDIE control bit, and set the KRIE control |
136 | * bit (to force immediate scan). */ | ||
137 | KPP_KPSR = KPP_KPSR_KRIE | KPP_KPSR_KDIE | KPP_KPSR_KRSS | | ||
138 | KPP_KPSR_KDSC | KPP_KPSR_KPKR | KPP_KPSR_KPKD; | ||
139 | |||
140 | /* KPP IRQ at priority 3 */ | ||
141 | avic_enable_int(KPP, IRQ, 3, KPP_HANDLER); | ||
60 | } | 142 | } |
61 | 143 | ||
62 | inline bool button_hold(void) | 144 | bool button_hold(void) |
63 | { | 145 | { |
64 | return GPIO3_DR & 0x10; | 146 | return _button_hold(); |
65 | } | 147 | } |
66 | 148 | ||
67 | int button_read_device(void) | 149 | int button_read_device(void) |
68 | { | 150 | { |
69 | unsigned short reg_val; | 151 | /* Simple poll of GPIO status */ |
70 | int col, row; | 152 | hold_button = _button_hold(); |
71 | int button = BUTTON_NONE; | 153 | |
72 | 154 | /* Backlight hold handling */ | |
73 | if(!button_hold()) { | 155 | if (hold_button != hold_button_old) |
74 | for (col = 0; col < 3; col++) { /* Col */ | 156 | { |
75 | /* 1. Write 1s to KPDR[15:8] setting column data to 1s */ | 157 | hold_button_old = hold_button; |
76 | reg_val = KPP_KPDR; | 158 | backlight_hold_changed(hold_button); |
77 | reg_val |= 0xff00; | ||
78 | KPP_KPDR = reg_val; | ||
79 | |||
80 | /* | ||
81 | * 2. Configure columns as totem pole outputs(for quick | ||
82 | * discharging of keypad capacitance) | ||
83 | */ | ||
84 | reg_val = KPP_KPCR; | ||
85 | reg_val &= 0x00ff; | ||
86 | KPP_KPCR = reg_val; | ||
87 | |||
88 | /* Give the columns time to discharge */ | ||
89 | udelay(2); | ||
90 | |||
91 | /* 3. Configure columns as open-drain */ | ||
92 | reg_val = KPP_KPCR; | ||
93 | reg_val |= ((1 << 8) - 1) << 8; | ||
94 | KPP_KPCR = reg_val; | ||
95 | |||
96 | /* 4. Write a single column to 0, others to 1. | ||
97 | * 5. Sample row inputs and save data. Multiple key presses | ||
98 | * can be detected on a single column. | ||
99 | * 6. Repeat steps 1 - 5 for remaining columns. | ||
100 | */ | ||
101 | |||
102 | /* Col bit starts at 8th bit in KPDR */ | ||
103 | reg_val = KPP_KPDR; | ||
104 | reg_val &= ~(1 << (8 + col)); | ||
105 | KPP_KPDR = reg_val; | ||
106 | |||
107 | /* Delay added to avoid propagating the 0 from column to row | ||
108 | * when scanning. */ | ||
109 | udelay(2); | ||
110 | |||
111 | /* Read row input */ | ||
112 | reg_val = KPP_KPDR; | ||
113 | for (row = 0; row < 5; row++) { /* sample row */ | ||
114 | if (!(reg_val & (1 << row))) { | ||
115 | if(row == 0) { | ||
116 | if(col == 0) { | ||
117 | button |= BUTTON_LEFT; | ||
118 | } | ||
119 | if(col == 1) { | ||
120 | button |= BUTTON_BACK; | ||
121 | } | ||
122 | if(col == 2) { | ||
123 | button |= BUTTON_VOL_UP; | ||
124 | } | ||
125 | } else if(row == 1) { | ||
126 | if(col == 0) { | ||
127 | button |= BUTTON_UP; | ||
128 | } | ||
129 | if(col == 1) { | ||
130 | button |= BUTTON_MENU; | ||
131 | } | ||
132 | if(col == 2) { | ||
133 | button |= BUTTON_VOL_DOWN; | ||
134 | } | ||
135 | } else if(row == 2) { | ||
136 | if(col == 0) { | ||
137 | button |= BUTTON_DOWN; | ||
138 | } | ||
139 | if(col == 2) { | ||
140 | button |= BUTTON_PREV; | ||
141 | } | ||
142 | } else if(row == 3) { | ||
143 | if(col == 0) { | ||
144 | button |= BUTTON_RIGHT; | ||
145 | } | ||
146 | if(col == 2) { | ||
147 | button |= BUTTON_PLAY; | ||
148 | } | ||
149 | } else if(row == 4) { | ||
150 | if(col == 0) { | ||
151 | button |= BUTTON_SELECT; | ||
152 | } | ||
153 | if(col == 2) { | ||
154 | button |= BUTTON_NEXT; | ||
155 | } | ||
156 | } | ||
157 | } | ||
158 | } | ||
159 | } | ||
160 | |||
161 | /* | ||
162 | * 7. Return all columns to 0 in preparation for standby mode. | ||
163 | * 8. Clear KPKD and KPKR status bit(s) by writing to a .1., | ||
164 | * set the KPKR synchronizer chain by writing "1" to KRSS register, | ||
165 | * clear the KPKD synchronizer chain by writing "1" to KDSC register | ||
166 | */ | ||
167 | reg_val = 0x00; | ||
168 | KPP_KPDR = reg_val; | ||
169 | reg_val = KPP_KPDR; | ||
170 | reg_val = KPP_KPSR; | ||
171 | reg_val |= 0xF; | ||
172 | KPP_KPSR = reg_val; | ||
173 | } | 159 | } |
174 | 160 | ||
175 | return button; | 161 | /* If hold, ignore any pressed button */ |
162 | return hold_button ? BUTTON_NONE : int_btn; | ||
176 | } | 163 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c index 7d6e8efd22..10ee3f44c0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c | |||
@@ -35,6 +35,8 @@ void spi_init(void) { | |||
35 | } | 35 | } |
36 | 36 | ||
37 | static int spi_transfer(int address, long data, long* buffer, bool read) { | 37 | static int spi_transfer(int address, long data, long* buffer, bool read) { |
38 | return -1; /* Disable for now - hangs - and we'll use interrupts */ | ||
39 | |||
38 | unsigned long packet = 0; | 40 | unsigned long packet = 0; |
39 | if(!read) { | 41 | if(!read) { |
40 | /* Set the appropriate bit in the packet to indicate a write */ | 42 | /* Set the appropriate bit in the packet to indicate a write */ |