Gigabeat S: Get button driver at 100%. Disable SPI because it hangs and will be changed to interrupt-based. Add some more iMX.31 register definitions and flags.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16247 a1c6a512-1295-4272-9138-f99709370657

3 files changed, 382 insertions, 130 deletions

diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index b10fc1ea17..e2ee7762f4 100755
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -105,6 +105,261 @@
 #define WDOG1_BASE_ADDR         WDOG_BASE_ADDR
 #define CRM_MCU_BASE_ADDR       CCM_BASE_ADDR
 
+/* IOMUXC */
+#define IOMUXC_(o)              (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
+
+    /* GPR */
+#define IOMUXC_GPR              IOMUXC_(0x008)
+
+    /* SW_MUX_CTL */
+#define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD          IOMUXC_(0x00C)
+#define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI              IOMUXC_(0x010)
+#define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK                  IOMUXC_(0x014)
+#define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0                IOMUXC_(0x018)
+#define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0                     IOMUXC_(0x01C)
+#define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS                        IOMUXC_(0x020)
+#define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ                             IOMUXC_(0x024)
+#define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1                           IOMUXC_(0x028)
+#define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I                           IOMUXC_(0x02C)
+#define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0                                IOMUXC_(0x030)
+#define SW_MUX_CTL_LD11_LD12_LD13_LD14                                  IOMUXC_(0x034)
+#define SW_MUX_CTL_LD7_LD8_LD9_LD10                                     IOMUXC_(0x038)
+#define SW_MUX_CTL_LD3_LD4_LD5_LD6                                      IOMUXC_(0x03C)
+#define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2                              IOMUXC_(0x040)
+#define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0            IOMUXC_(0x044)
+#define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK     IOMUXC_(0x048)
+#define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4  IOMUXC_(0x04C)
+#define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0        IOMUXC_(0x050)
+#define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK                    IOMUXC_(0x054)
+#define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD                               IOMUXC_(0x058)
+#define SW_MUX_CTL_RTCK_TCK_TMS_TDI                                     IOMUXC_(0x05C)
+#define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7                  IOMUXC_(0x060)
+#define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3                  IOMUXC_(0x064)
+#define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7                  IOMUXC_(0x068)
+#define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3                  IOMUXC_(0x06C)
+#define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE                             IOMUXC_(0x070)
+#define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2                       IOMUXC_(0x074)
+#define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1                   IOMUXC_(0x078)
+#define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1                          IOMUXC_(0x07C)
+#define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1                   IOMUXC_(0x080)
+#define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2             IOMUXC_(0x084)
+#define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI        IOMUXC_(0x088)
+#define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1            IOMUXC_(0x08C)
+#define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6                                IOMUXC_(0x090)
+#define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5                                IOMUXC_(0x094)
+#define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4                                IOMUXC_(0x098)
+#define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3                                IOMUXC_(0x09C)
+#define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT                 IOMUXC_(0x0A0)
+#define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC                   IOMUXC_(0x0A4)
+#define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13                      IOMUXC_(0x0A8)
+#define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9                          IOMUXC_(0x0AC)
+#define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5                      IOMUXC_(0x0B0)
+#define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE                         IOMUXC_(0x0B4)
+#define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2                        IOMUXC_(0x0B8)
+#define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON                 IOMUXC_(0x0BC)
+#define SW_MUX_CTL_D2_D1_D0_PC_CD1_B                                    IOMUXC_(0x0C0)
+#define SW_MUX_CTL_D6_D5_D4_D3                                          IOMUXC_(0x0C4)
+#define SW_MUX_CTL_D10_D9_D8_D7                                         IOMUXC_(0x0C8)
+#define SW_MUX_CTL_D14_D13_D12_D11                                      IOMUXC_(0x0CC)
+#define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15                               IOMUXC_(0x0D0)
+#define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE                            IOMUXC_(0x0D4)
+#define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3                              IOMUXC_(0x0D8)
+#define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B                          IOMUXC_(0x0DC)
+#define SW_MUX_CTL_RW_RAS_CAS_SDWE                                      IOMUXC_(0x0E0)
+#define SW_MUX_CTL_CS5_ECB_LBA_BCLK                                     IOMUXC_(0x0E4)
+#define SW_MUX_CTL_CS1_CS2_CS3_CS4                                      IOMUXC_(0x0E8)
+#define SW_MUX_CTL_EB0_EB1_OE_CS0                                       IOMUXC_(0x0EC)
+#define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3                                  IOMUXC_(0x0F0)
+#define SW_MUX_CTL_SD28_SD29_SD30_SD31                                  IOMUXC_(0x0F4)
+#define SW_MUX_CTL_SD24_SD25_SD26_SD27                                  IOMUXC_(0x0F8)
+#define SW_MUX_CTL_SD20_SD21_SD22_SD23                                  IOMUXC_(0x0FC)
+#define SW_MUX_CTL_SD16_SD17_SD18_SD19                                  IOMUXC_(0x100)
+#define SW_MUX_CTL_SD12_SD13_SD14_SD15                                  IOMUXC_(0x104)
+#define SW_MUX_CTL_SD8_SD9_SD10_SD11                                    IOMUXC_(0x108)
+#define SW_MUX_CTL_SD4_SD5_SD6_SD7                                      IOMUXC_(0x10C)
+#define SW_MUX_CTL_SD0_SD1_SD2_SD3                                      IOMUXC_(0x110)
+#define SW_MUX_CTL_A24_A25_SDBA1_SDBA0                                  IOMUXC_(0x114)
+#define SW_MUX_CTL_A20_A21_A22_A23                                      IOMUXC_(0x118)
+#define SW_MUX_CTL_A16_A17_A18_A19                                      IOMUXC_(0x11C)
+#define SW_MUX_CTL_A12_A13_A14_A15                                      IOMUXC_(0x120)
+#define SW_MUX_CTL_A9_A10_MA10_A11                                      IOMUXC_(0x124)
+#define SW_MUX_CTL_A5_A6_A7_A8                                          IOMUXC_(0x128)
+#define SW_MUX_CTL_A1_A2_A3_A4                                          IOMUXC_(0x12C)
+#define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0                                   IOMUXC_(0x130)
+#define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0                          IOMUXC_(0x134)
+#define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4          IOMUXC_(0x138)
+#define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0                     IOMUXC_(0x13C)
+#define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH                                IOMUXC_(0x140)
+#define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0                            IOMUXC_(0x144)
+#define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0                      IOMUXC_(0x148)
+#define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3                      IOMUXC_(0x14C)
+#define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO                    IOMUXC_(0x150)
+
+#define SW_MUX_OUT_EN_GPIO_DR   0x0
+#define SW_MUX_OUT_FUNCTIONAL   0x1
+#define SW_MUX_OUT_ALTERNATE_1  0x2
+#define SW_MUX_OUT_ALTERNATE_2  0x3
+#define SW_MUX_OUT_ALTERNATE_3  0x4
+#define SW_MUX_OUT_ALTERNATE_4  0x5
+#define SW_MUX_OUT_ALTERNATE_5  0x6
+#define SW_MUX_OUT_ALTERNATE_6  0x7
+
+#define SW_MUX_IN_NO_INPUTS     0x0
+#define SW_MUX_IN_GPIO_PSR_ISR  0x1
+#define SW_MUX_IN_FUNCTIONAL    0x2
+#define SW_MUX_IN_ALTERNATE_1   0x3
+#define SW_MUX_IN_ALTERNATE_2   0x4
+
+/* Shift above flags into one of the four fields in each register */
+#define SW_MUX_CTL_FLD_0(x)     ((x) << 0)
+#define SW_MUX_CTL_FLD_1(x)     ((x) << 8)
+#define SW_MUX_CTL_FLD_2(x)     ((x) << 16)
+#define SW_MUX_CTL_FLD_3(x)     ((x) << 24)
+
+    /* SW_PAD_CTL */
+#define SW_PAD_CTL_TTM_PAD__X__X                            IOMUXC_(0x154)
+#define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY      IOMUXC_(0x158)
+#define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI              IOMUXC_(0x15C)
+#define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B           IOMUXC_(0x160)
+#define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR                 IOMUXC_(0x164)
+#define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3            IOMUXC_(0x168)
+#define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0                IOMUXC_(0x16C)
+#define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL                     IOMUXC_(0x170)
+#define SW_PAD_CTL_READ_VSYNC3_CONTRAST                     IOMUXC_(0x174)
+#define SW_PAD_CTL_SER_RS_PAR_RS_WRITE                      IOMUXC_(0x178)
+#define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1                       IOMUXC_(0x17C)
+#define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO                     IOMUXC_(0x180)
+#define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT                     IOMUXC_(0x184)
+#define SW_PAD_CTL_LD15_LD16_LD17                           IOMUXC_(0x188)
+#define SW_PAD_CTL_LD12_LD13_LD14                           IOMUXC_(0x18C)
+#define SW_PAD_CTL_LD9_LD10_LD11                            IOMUXC_(0x190)
+#define SW_PAD_CTL_LD6_LD7_LD8                              IOMUXC_(0x194)
+#define SW_PAD_CTL_LD3_LD4_LD5                              IOMUXC_(0x198)
+#define SW_PAD_CTL_LD0_LD1_LD2                              IOMUXC_(0x19C)
+#define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1        IOMUXC_(0x1A0)
+#define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP            IOMUXC_(0x1A4)
+#define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7   IOMUXC_(0x1A8)
+#define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4   IOMUXC_(0x1AC)
+#define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1     IOMUXC_(0x1B0)
+#define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP         IOMUXC_(0x1B4)
+#define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP                   IOMUXC_(0x1B8)
+#define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD                       IOMUXC_(0x1BC)
+#define SW_PAD_CTL_TMS_TDI_TDO                              IOMUXC_(0x1C0)
+#define SW_PAD_CTL_KEY_COL7_RTCK_TCK                        IOMUXC_(0x1C4)
+#define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6               IOMUXC_(0x1C8)
+#define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3               IOMUXC_(0x1CC)
+#define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0               IOMUXC_(0x1D0)
+#define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5               IOMUXC_(0x1D4)
+#define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2               IOMUXC_(0x1D8)
+#define SW_PAD_CTL_RTS2_CTS2_BATT_LINE                      IOMUXC_(0x1DC)
+#define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2                       IOMUXC_(0x1E0)
+#define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1                IOMUXC_(0x1E4)
+#define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1                IOMUXC_(0x1E8)
+#define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1                   IOMUXC_(0x1EC)
+#define SW_PAD_CTL_RXD1_TXD1_RTS1                           IOMUXC_(0x1F0)
+#define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY       IOMUXC_(0x1F4)
+#define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1           IOMUXC_(0x1F8)
+#define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI      IOMUXC_(0x1FC)
+#define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS             IOMUXC_(0x200)
+#define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO               IOMUXC_(0x204)
+#define SW_PAD_CTL_STXD6_SRXD6_SCK6                         IOMUXC_(0x208)
+#define SW_PAD_CTL_SRXD5_SCK5_SFS5                          IOMUXC_(0x20C)
+#define SW_PAD_CTL_SCK4_SFS4_STXD5                          IOMUXC_(0x210)
+#define SW_PAD_CTL_SFS3_STXD4_SRXD4                         IOMUXC_(0x214)
+#define SW_PAD_CTL_STXD3_SRXD3_SCK3                         IOMUXC_(0x218)
+#define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT               IOMUXC_(0x21C)
+#define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC             IOMUXC_(0x220)
+#define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15                  IOMUXC_(0x224)
+#define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12                  IOMUXC_(0x228)
+#define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9                     IOMUXC_(0x22C)
+#define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6                     IOMUXC_(0x230)
+#define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT                 IOMUXC_(0x234)
+#define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B                    IOMUXC_(0x238)
+#define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2                   IOMUXC_(0x23C)
+#define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1                 IOMUXC_(0x240)
+#define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B              IOMUXC_(0x244)
+#define SW_PAD_CTL_D2_D1_D0                                 IOMUXC_(0x248)
+#define SW_PAD_CTL_D5_D4_D3                                 IOMUXC_(0x24C)
+#define SW_PAD_CTL_D8_D7_D6                                 IOMUXC_(0x250)
+#define SW_PAD_CTL_D11_D10_D9                               IOMUXC_(0x254)
+#define SW_PAD_CTL_D14_D13_D12                              IOMUXC_(0x258)
+#define SW_PAD_CTL_NFCE_B_NFRB_D15                          IOMUXC_(0x25C)
+#define SW_PAD_CTL_NFALE_NFCLE_NFWP_B                       IOMUXC_(0x260)
+#define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B                      IOMUXC_(0x264)
+#define SW_PAD_CTL_SDQS0_SDQS1_SDQS2                        IOMUXC_(0x268)
+#define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B                     IOMUXC_(0x26C)
+#define SW_PAD_CTL_CAS_SDWE_SDCKE0                          IOMUXC_(0x270)
+#define SW_PAD_CTL_BCLK_RW_RAS                              IOMUXC_(0x274)
+#define SW_PAD_CTL_CS5_ECB_LBA                              IOMUXC_(0x278)
+#define SW_PAD_CTL_CS2_CS3_CS4                              IOMUXC_(0x27C)
+#define SW_PAD_CTL_OE_CS0_CS1                               IOMUXC_(0x280)
+#define SW_PAD_CTL_DQM3_EB0_EB1                             IOMUXC_(0x284)
+#define SW_PAD_CTL_DQM0_DQM1_DQM2                           IOMUXC_(0x288)
+#define SW_PAD_CTL_SD29_SD30_SD31                           IOMUXC_(0x28C)
+#define SW_PAD_CTL_SD26_SD27_SD28                           IOMUXC_(0x290)
+#define SW_PAD_CTL_SD23_SD24_SD25                           IOMUXC_(0x294)
+#define SW_PAD_CTL_SD20_SD21_SD22                           IOMUXC_(0x298)
+#define SW_PAD_CTL_SD17_SD18_SD19                           IOMUXC_(0x29C)
+#define SW_PAD_CTL_SD14_SD15_SD16                           IOMUXC_(0x2A0)
+#define SW_PAD_CTL_SD11_SD12_SD13                           IOMUXC_(0x2A4)
+#define SW_PAD_CTL_SD8_SD9_SD10                             IOMUXC_(0x2A8)
+#define SW_PAD_CTL_SD5_SD6_SD7                              IOMUXC_(0x2AC)
+#define SW_PAD_CTL_SD2_SD3_SD4                              IOMUXC_(0x2B0)
+#define SW_PAD_CTL_SDBA0_SD0_SD1                            IOMUXC_(0x2B4)
+#define SW_PAD_CTL_A24_A25_SDBA1                            IOMUXC_(0x2B8)
+#define SW_PAD_CTL_A21_A22_A23                              IOMUXC_(0x2BC)
+#define SW_PAD_CTL_A18_A19_A20                              IOMUXC_(0x2C0)
+#define SW_PAD_CTL_A15_A16_A17                              IOMUXC_(0x2C4)
+#define SW_PAD_CTL_A12_A13_A14                              IOMUXC_(0x2C8)
+#define SW_PAD_CTL_A10_MA10_A11                             IOMUXC_(0x2CC)
+#define SW_PAD_CTL_A7_A8_A9                                 IOMUXC_(0x2D0)
+#define SW_PAD_CTL_A4_A5_A6                                 IOMUXC_(0x2D4)
+#define SW_PAD_CTL_A1_A2_A3                                 IOMUXC_(0x2D8)
+#define SW_PAD_CTL_VPG0_VPG1_A0                             IOMUXC_(0x2DC)
+#define SW_PAD_CTL_VSTBY_DVFS0_DVFS1                        IOMUXC_(0x2E0)
+#define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL               IOMUXC_(0x2E4)
+#define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3         IOMUXC_(0x2E8)
+#define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0                    IOMUXC_(0x2EC)
+#define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B                   IOMUXC_(0x2F0)
+#define SW_PAD_CTL_SVEN0_STX0_SRX0                          IOMUXC_(0x2F4)
+#define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0                      IOMUXC_(0x2F8)
+#define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0                  IOMUXC_(0x2FC)
+#define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4                  IOMUXC_(0x300)
+#define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1                     IOMUXC_(0x304)
+#define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST             IOMUXC_(0x308)
+
+/* SW_PAD_CTL flags */
+#define SW_PAD_CTL_LOOPBACK                         (1 << 9)
+#define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER  (0 << 7)
+#if 0 /* Same as 0 */
+#define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER  (1 << 7)
+#endif
+#define SW_PAD_CTL_ENABLE_KEEPER                    (2 << 7)
+#define SW_PAD_CTL_ENABLE_PULL_UP_OR_PULL_DOWN      (3 << 7)
+#define SW_PAD_CTL_100K_PULL_DOWN                   (0 << 5)
+#define SW_PAD_CTL_100K_PULL_UP                     (1 << 5)
+#if 0 /* Completeness */
+#define SW_PAD_CTL_47K_PULL_UP                      (2 << 5) /* Not in IMX31/L */
+#define SW_PAD_CTL_22K_PULL_UP                      (3 << 5) /* Not in IMX31/L */
+#endif
+#define SW_PAD_CTL_IPP_HYS_STD                      (0 << 4)
+#define SW_PAD_CTL_IPP_HYS_SCHIMDT                  (1 << 4)
+#define SW_PAD_CTL_IPP_ODE_CMOS                     (0 << 3)
+#define SW_PAD_CTL_IPP_ODE_OPEN                     (1 << 3)
+#define SW_PAD_CTL_IPP_DSE_STD                      (0 << 1)
+#define SW_PAD_CTL_IPP_DSE_HIGH                     (1 << 1)
+#define SW_PAD_CTL_IPP_DSE_MAX                      (2 << 1)
+#if 0 /* Same as 2 */
+#define SW_PAD_CTL_IPP_DSE_MAX                      (3 << 1)
+#endif
+#define SW_PAD_CTL_IPP_SRE_SLOW                     (0 << 0)
+#define SW_PAD_CTL_IPP_SRE_FAST                     (1 << 0)
+
+/* Shift above flags into one of the three fields in each register */
+#define SW_PAD_CTL_FLD_0(x)                         ((x) << 0)
+#define SW_PAD_CTL_FLD_1(x)                         ((x) << 10)
+#define SW_PAD_CTL_FLD_2(x)                         ((x) << 20)
+
 /* IPU */
 #define IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
 #define IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
@@ -272,6 +527,14 @@
 #define KPP_KDDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
 #define KPP_KPDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
 
+/* KPP_KPSR bits */
+#define KPP_KPSR_KRIE           (1 << 9)
+#define KPP_KPSR_KDIE           (1 << 8)
+#define KPP_KPSR_KRSS           (1 << 3)
+#define KPP_KPSR_KDSC           (1 << 2)
+#define KPP_KPSR_KPKR           (1 << 1)
+#define KPP_KPSR_KPKD           (1 << 0)
+
 /* ROMPATCH and AVIC */
 #define ROMPATCH_BASE_ADDR      0x60000000
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
index eea0faa4eb..493ce3af3e 100644
--- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
@@ -21,156 +21,143 @@
 #include "cpu.h"
 #include "system.h"
 #include "button.h"
-#include "kernel.h"
 #include "backlight.h"
-#include "adc.h"
 #include "system.h"
 #include "backlight-target.h"
-#include "debug.h"
-#include "stdio.h"
+#include "avic-imx31.h"
 
 /* Most code in here is taken from the Linux BSP provided by Freescale
  * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. */
 
+static uint32_t int_btn = BUTTON_NONE;
+static bool hold_button     = false;
+static bool hold_button_old = false;
+#define _button_hold() (GPIO3_DR & 0x10)
+
+static __attribute__((interrupt("IRQ"))) void KPP_HANDLER(void)
+{
+    static const int key_mtx[5][3] =
+    {
+        { BUTTON_LEFT,   BUTTON_BACK, BUTTON_VOL_UP   },
+        { BUTTON_UP,     BUTTON_MENU, BUTTON_VOL_DOWN },
+        { BUTTON_DOWN,   BUTTON_NONE, BUTTON_PREV     },
+        { BUTTON_RIGHT,  BUTTON_NONE, BUTTON_PLAY     },
+        { BUTTON_SELECT, BUTTON_NONE, BUTTON_NEXT     },
+    };
+
+    unsigned short reg_val;
+    int col, row;
+    int i;
+    int button = BUTTON_NONE;
+
+    /* 1. Disable both (depress and release) keypad interrupts. */
+    KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE);
+
+    for (col = 0; col < 3; col++) /* Col */
+    {
+        /* 2. Write 1s to KPDR[10:8] setting column data to 1s */
+        KPP_KPDR |= (0x7 << 8);
+
+        /* 3. Configure columns as totem pole outputs(for quick
+         * discharging of keypad capacitance) */
+        KPP_KPCR &= ~(0x7 << 8);
+
+        /* Give the columns time to discharge */
+        for (i = 0; i < 256; i++)
+            asm volatile ("");
+
+        /* 4. Configure columns as open-drain */
+        KPP_KPCR |= (0x7 << 8);
+
+        /* 5. Write a single column to 0, others to 1.
+         * 6. Sample row inputs and save data. Multiple key presses
+         *    can be detected on a single column.
+         * 7. Repeat steps 2 - 6 for remaining columns. */
+
+        /* Col bit starts at 8th bit in KPDR */
+        KPP_KPDR &= ~(1 << (8 + col));
+
+        /* Delay added to avoid propagating the 0 from column to row
+         * when scanning. */
+        for (i = 0; i < 256; i++)
+            asm volatile ("");
+
+        /* Read row input */
+        reg_val = KPP_KPDR;
+        for (row = 0; row < 5; row++)   /* sample row */
+        {
+            if (!(reg_val & (1 << row)))
+                button |= key_mtx[row][col];
+        }
+    }
+
+    /* 8. Return all columns to 0 in preparation for standby mode. */
+    KPP_KPDR &= ~(0x7 << 8);
+
+    /* 9. Clear KPKD and KPKR status bit(s) by writing to a .1.,
+     *    set the KPKR synchronizer chain by writing "1" to KRSS register,
+     *    clear the KPKD synchronizer chain by writing "1" to KDSC register */
+    KPP_KPSR = KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKR | KPP_KPSR_KPKD;
+
+    /* 10. Re-enable the appropriate keypad interrupt(s) so that the KDIE
+     *     detects a key hold condition, or the KRIE detects a key-release
+     *     event. */
+    if (int_btn != BUTTON_NONE)
+        KPP_KPSR |= KPP_KPSR_KRIE;
+    else
+        KPP_KPSR |= KPP_KPSR_KDIE;
+
+    int_btn = button;
+}
+
 void button_init_device(void)
 {
-    unsigned int reg_val;
     /* Enable keypad clock */
     CLKCTL_CGR1 |= (3 << 2*10);
-    
-    /* Enable number of rows in keypad (KPCR[7:0])
-     * Configure keypad columns as open-drain (KPCR[15:8])
+
+    /* 1. Enable number of rows in keypad (KPCR[4:0])
      *
      * Configure the rows/cols in KPP
-     * LSB nibble in KPP is for 8 rows
-     * MSB nibble in KPP is for 8 cols
-     */
-#if 0
-    KPP_KPCR = (0xff << 8) | 0xff;
-    /* Write 0's to KPDR[15:8] */
-    reg_val = KPP_KPDR;
-    reg_val &= 0x00ff;
-    KPP_KPDR = reg_val;
-
-    /* Configure columns as output, rows as input (KDDR[15:0]) */
-    KPP_KDDR = 0xff00;
-#endif
-
-    KPP_KPSR = (1 << 3) | (1 << 2);
+     * LSB nybble in KPP is for 5 rows
+     * MSB nybble in KPP is for 3 cols */
+    KPP_KPCR |= 0x1f;
+
+    /* 2. Write 0's to KPDR[10:8] */
+    KPP_KPDR &= ~(0x7 << 8);
+
+    /* 3. Configure the keypad columns as open-drain (KPCR[10:8]). */
+    KPP_KPCR |= (0x7 << 8);
+
+    /* 4. Configure columns as output, rows as input (KDDR[10:8,4:0]) */
+    KPP_KDDR = (KPP_KDDR | (0x7 << 8)) & ~0x1f;
+
+    /* 5. Clear the KPKD Status Flag and Synchronizer chain.
+     * 6. Set the KDIE control bit, and set the KRIE control
+     *    bit (to force immediate scan). */
+    KPP_KPSR = KPP_KPSR_KRIE | KPP_KPSR_KDIE | KPP_KPSR_KRSS |
+               KPP_KPSR_KDSC | KPP_KPSR_KPKR | KPP_KPSR_KPKD;
+
+    /* KPP IRQ at priority 3 */
+    avic_enable_int(KPP, IRQ, 3, KPP_HANDLER);
 }
 
-inline bool button_hold(void)
+bool button_hold(void)
 {
-    return GPIO3_DR & 0x10;
+    return _button_hold();
 }
 
 int button_read_device(void)
 {
-    unsigned short reg_val;
-    int col, row;
-    int button = BUTTON_NONE;
-
-    if(!button_hold()) {
-        for (col = 0; col < 3; col++) {  /* Col */
-            /* 1. Write 1s to KPDR[15:8] setting column data to 1s */
-            reg_val = KPP_KPDR;
-            reg_val |= 0xff00;
-            KPP_KPDR = reg_val;
-
-            /*
-             * 2. Configure columns as totem pole outputs(for quick
-             * discharging of keypad capacitance)
-             */
-            reg_val = KPP_KPCR;
-            reg_val &= 0x00ff;
-            KPP_KPCR = reg_val;
-
-            /* Give the columns time to discharge */
-            udelay(2);
-
-            /* 3. Configure columns as open-drain */
-            reg_val = KPP_KPCR;
-            reg_val |= ((1 << 8) - 1) << 8;
-            KPP_KPCR = reg_val;
-
-            /* 4. Write a single column to 0, others to 1.
-             * 5. Sample row inputs and save data. Multiple key presses
-             * can be detected on a single column.
-             * 6. Repeat steps 1 - 5 for remaining columns.
-             */
-
-            /* Col bit starts at 8th bit in KPDR */
-            reg_val = KPP_KPDR;
-            reg_val &= ~(1 << (8 + col));
-            KPP_KPDR = reg_val;
-
-            /* Delay added to avoid propagating the 0 from column to row
-             * when scanning. */
-            udelay(2);
-
-            /* Read row input */
-            reg_val = KPP_KPDR;
-            for (row = 0; row < 5; row++) {  /* sample row */
-                if (!(reg_val & (1 << row))) {
-                    if(row == 0) {
-                            if(col == 0) {
-                                button |= BUTTON_LEFT;
-                            }
-                            if(col == 1) {
-                                button |= BUTTON_BACK;
-                            }
-                            if(col == 2) {
-                                button |= BUTTON_VOL_UP;
-                            }
-                    } else if(row == 1) {
-                            if(col == 0) {
-                                button |= BUTTON_UP;
-                            }
-                            if(col == 1) {
-                                button |= BUTTON_MENU;
-                            }
-                            if(col == 2) {
-                                button |= BUTTON_VOL_DOWN;
-                            }
-                    } else if(row == 2) {
-                            if(col == 0) {
-                                button |= BUTTON_DOWN;
-                            }
-                            if(col == 2) {
-                                button |= BUTTON_PREV;
-                            }
-                    } else if(row == 3) {
-                            if(col == 0) {
-                                button |= BUTTON_RIGHT;
-                            }
-                            if(col == 2) {
-                                button |= BUTTON_PLAY;
-                            }
-                    } else if(row == 4) {
-                            if(col == 0) {
-                                button |= BUTTON_SELECT;
-                            }
-                            if(col == 2) {
-                                button |= BUTTON_NEXT;
-                            }
-                    }
-                }
-            }
-        }
-
-        /*
-         * 7. Return all columns to 0 in preparation for standby mode.
-         * 8. Clear KPKD and KPKR status bit(s) by writing to a .1.,
-         * set the KPKR synchronizer chain by writing "1" to KRSS register,
-         * clear the KPKD synchronizer chain by writing "1" to KDSC register
-         */
-        reg_val = 0x00;
-        KPP_KPDR = reg_val;
-        reg_val = KPP_KPDR;
-        reg_val = KPP_KPSR;
-        reg_val |= 0xF;
-        KPP_KPSR = reg_val;
+    /* Simple poll of GPIO status */
+    hold_button = _button_hold();
+
+    /* Backlight hold handling */
+    if (hold_button != hold_button_old)
+    {
+        hold_button_old = hold_button;
+        backlight_hold_changed(hold_button);
     }
 
-    return button;
+    /* If hold, ignore any pressed button */
+    return hold_button ? BUTTON_NONE : int_btn;
 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
index 7d6e8efd22..10ee3f44c0 100644
--- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
@@ -35,6 +35,8 @@ void spi_init(void) {
 }
 
 static int spi_transfer(int address, long data, long* buffer, bool read) {
+    return -1; /* Disable for now - hangs - and we'll use interrupts */
+
     unsigned long packet = 0;
     if(!read) {
         /* Set the appropriate bit in the packet to indicate a write */