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author | Marcin Bukat <marcin.bukat@gmail.com> | 2014-11-06 10:31:11 +0100 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2014-11-06 10:31:11 +0100 |
commit | bb5341c4be06237e5da2ec8cf57dac2cebd13eba (patch) | |
tree | 3b67b622198265f923ed113a7357b1b63dd49a3c /utils/regtools | |
parent | df2ac7428f1ab98ccc2109d4f70521c5f8404c2c (diff) | |
download | rockbox-bb5341c4be06237e5da2ec8cf57dac2cebd13eba.tar.gz rockbox-bb5341c4be06237e5da2ec8cf57dac2cebd13eba.zip |
regtools: ATJ213x description file
Change-Id: I5b4d29e0808c57e252f5b6c3b9ba26a52c1bd112
Diffstat (limited to 'utils/regtools')
-rw-r--r-- | utils/regtools/desc/regs-atj213x.xml | 759 |
1 files changed, 759 insertions, 0 deletions
diff --git a/utils/regtools/desc/regs-atj213x.xml b/utils/regtools/desc/regs-atj213x.xml new file mode 100644 index 0000000000..dface7e549 --- /dev/null +++ b/utils/regtools/desc/regs-atj213x.xml | |||
@@ -0,0 +1,759 @@ | |||
1 | <?xml version="1.0"?> | ||
2 | <soc name="atj213x" desc="Actions atj213x"> | ||
3 | <dev name="ADC" long_name="Analog to Digital Converter" desc="" version="1.0"> | ||
4 | <addr name="ADC" addr="0xb0110000"/> | ||
5 | </dev> | ||
6 | <dev name="ATA" long_name="" desc="" version="1.0"> | ||
7 | <addr name="ATA" addr="0xb0090000"/> | ||
8 | <reg name="CONFIG" desc=""> | ||
9 | <addr name="CONFIG" addr="0x0"/> | ||
10 | </reg> | ||
11 | <reg name="UDMACTL" desc=""> | ||
12 | <addr name="UDMACTL" addr="0x4"/> | ||
13 | </reg> | ||
14 | <reg name="DATA" desc=""> | ||
15 | <addr name="DATA" addr="0x8"/> | ||
16 | </reg> | ||
17 | <reg name="FEATURE" desc=""> | ||
18 | <addr name="FEATURE" addr="0xc"/> | ||
19 | </reg> | ||
20 | <reg name="SECCNT" desc=""> | ||
21 | <addr name="SECCNT" addr="0x10"/> | ||
22 | </reg> | ||
23 | <reg name="SECNUM" desc=""> | ||
24 | <addr name="SECNUM" addr="0x14"/> | ||
25 | </reg> | ||
26 | <reg name="CLDLOW" desc=""> | ||
27 | <addr name="CLDL" addr="0x18"/> | ||
28 | </reg> | ||
29 | <reg name="CLDHI" desc=""> | ||
30 | <addr name="CLDHIGH" addr="0x1c"/> | ||
31 | </reg> | ||
32 | <reg name="HEAD" desc=""> | ||
33 | <addr name="HEAD" addr="0x20"/> | ||
34 | </reg> | ||
35 | <reg name="CMD" desc=""> | ||
36 | <addr name="CMD" addr="0x24"/> | ||
37 | </reg> | ||
38 | <reg name="BYTECNT" desc=""> | ||
39 | <addr name="BYTECNT" addr="0x28"/> | ||
40 | </reg> | ||
41 | <reg name="FIFOCTL" desc=""> | ||
42 | <addr name="FIFOCTL" addr="0x2c"/> | ||
43 | </reg> | ||
44 | <reg name="FIFOCFG" desc=""> | ||
45 | <addr name="FIFOCTL" addr="0x30"/> | ||
46 | </reg> | ||
47 | <reg name="ADDRDEC" desc=""> | ||
48 | <addr name="ADDRDEC" addr="0x34"/> | ||
49 | </reg> | ||
50 | <reg name="IRQCTL" desc=""> | ||
51 | <addr name="IRQCTL" addr="0x38"/> | ||
52 | </reg> | ||
53 | </dev> | ||
54 | <dev name="BOOT" long_name="" desc="" version=""> | ||
55 | <addr name="BOOT" addr="0xb0038000"/> | ||
56 | <reg name="NORCTL" desc=""> | ||
57 | <addr name="NORCTL" addr="0x0"/> | ||
58 | </reg> | ||
59 | <reg name="BROMCTL" desc=""> | ||
60 | <addr name="BROMCTL" addr="0x4"/> | ||
61 | </reg> | ||
62 | <reg name="CHIPID" desc=""> | ||
63 | <addr name="CHIPID" addr="0x8"/> | ||
64 | </reg> | ||
65 | </dev> | ||
66 | <dev name="BT" long_name="" desc="" version=""> | ||
67 | <addr name="BT" addr="0xb00d0000"/> | ||
68 | </dev> | ||
69 | <dev name="CMU" long_name="Clock Management Unit" desc="" version="1.0"> | ||
70 | <addr name="CMU" addr="0xb0010000"/> | ||
71 | <reg name="COREPLL" desc=""> | ||
72 | <addr name="COREPLL" addr="0x0"/> | ||
73 | </reg> | ||
74 | <reg name="DSPPLL" desc=""> | ||
75 | <addr name="DSPPLL" addr="0x4"/> | ||
76 | </reg> | ||
77 | <reg name="AUDIOPLL" desc=""> | ||
78 | <addr name="AUDIOPLL" addr="0x8"/> | ||
79 | </reg> | ||
80 | <reg name="BUSCLK" desc=""> | ||
81 | <addr name="BUSCLK" addr="0xc"/> | ||
82 | </reg> | ||
83 | <reg name="SDRCLK" desc=""> | ||
84 | <addr name="SDRCLK" addr="0x10"/> | ||
85 | </reg> | ||
86 | <reg name="NANDCLK" desc=""> | ||
87 | <addr name="NANDCLK" addr="0x18"/> | ||
88 | </reg> | ||
89 | <reg name="SDCLK" desc=""> | ||
90 | <addr name="SDCLK" addr="0x1c"/> | ||
91 | </reg> | ||
92 | <reg name="MHACLK" desc=""> | ||
93 | <addr name="MHACLK" addr="0x20"/> | ||
94 | </reg> | ||
95 | <reg name="UART2CLK" desc=""> | ||
96 | <addr name="UART2CLK" addr="0x2c"/> | ||
97 | </reg> | ||
98 | <reg name="DMACLK" desc=""> | ||
99 | <addr name="DMACLK" addr="0x30"/> | ||
100 | </reg> | ||
101 | <reg name="FMCLK" desc=""> | ||
102 | <addr name="FMCLK" addr="0x34"/> | ||
103 | </reg> | ||
104 | <reg name="MCACLK" desc=""> | ||
105 | <addr name="MCACLK" addr="0x38"/> | ||
106 | </reg> | ||
107 | <reg name="DEVCLKEN" desc=""> | ||
108 | <addr name="DEVCLKEN" addr="0x80"/> | ||
109 | </reg> | ||
110 | <reg name="DEVRST" desc=""> | ||
111 | <addr name="DEVRST" addr="0x84"/> | ||
112 | </reg> | ||
113 | </dev> | ||
114 | <dev name="DAC" long_name="Digital Analog Converter" desc="" version="1.0"> | ||
115 | <addr name="DAC" addr="0xb0100000"/> | ||
116 | </dev> | ||
117 | <dev name="DMAC" long_name="Direct Memory Access Controller" desc="Channels 0-3 work with retular AHB bus, channels 4-7 work with 'special' bus." version=""> | ||
118 | <addr name="DMAC" addr="0xb0060000"/> | ||
119 | <reg name="CTL" desc=""> | ||
120 | <addr name="CTL" addr="0x0"/> | ||
121 | </reg> | ||
122 | <reg name="IRQEN" desc=""> | ||
123 | <addr name="IRQEN" addr="0x4"/> | ||
124 | </reg> | ||
125 | <reg name="IRQPD" desc=""> | ||
126 | <addr name="IRQPD" addr="0x8"/> | ||
127 | </reg> | ||
128 | <reg name="DMA_MODE" desc=""> | ||
129 | <addr name="DMA0_MODE" addr="0x100"/> | ||
130 | <addr name="DMA1_MODE" addr="0x200"/> | ||
131 | <addr name="DMA2_MODE" addr="0x300"/> | ||
132 | <addr name="DMA3_MODE" addr="0x400"/> | ||
133 | <addr name="DMA4_MODE" addr="0x500"/> | ||
134 | <addr name="DMA5_MODE" addr="0x600"/> | ||
135 | <addr name="DMA6_MODE" addr="0x700"/> | ||
136 | <addr name="DMA7_MODE" addr="0x800"/> | ||
137 | <field name="DBURLEN" desc="Destination burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary." bitrange="31:29"> | ||
138 | <value name="SINGLE" value="0x0" desc=""/> | ||
139 | <value name="INCR4" value="0x3" desc=""/> | ||
140 | <value name="INCR8" value="0x5" desc=""/> | ||
141 | </field> | ||
142 | <field name="RELO" desc="DMA Reload Bit." bitrange="28:28"/> | ||
143 | <field name="DDSP" desc="Destination DSP mode. " bitrange="27:27"/> | ||
144 | <field name="DCOL" desc="Destination Column Mode." bitrange="26:26"/> | ||
145 | <field name="DDIR" desc="Destination address direction. If DBURLEN is INCR4 or INCR8 only INCREASE is allowed." bitrange="25:25"> | ||
146 | <value name="INCREASE" value="0x0" desc=""/> | ||
147 | <value name="DECREASE" value="0x1" desc=""/> | ||
148 | </field> | ||
149 | <field name="DFXA" desc="Destination Fixed Address bit." bitrange="24:24"> | ||
150 | <value name="NOT_FIXED" value="0x0" desc=""/> | ||
151 | <value name="FIXED" value="0x1" desc=""/> | ||
152 | </field> | ||
153 | <field name="DTRG" desc="Destination DRQ Trig Source." bitrange="23:19"> | ||
154 | <value name="DAC" value="0x6" desc=""/> | ||
155 | <value name="SDRAM" value="0x10" desc=""/> | ||
156 | <value name="IRAM" value="0x11" desc=""/> | ||
157 | <value name="SD" value="0x16" desc=""/> | ||
158 | <value name="OTG" value="0x17" desc=""/> | ||
159 | <value name="LCM" value="0x18" desc=""/> | ||
160 | </field> | ||
161 | <field name="DTRANWID" desc="" bitrange="18:17"> | ||
162 | <value name="WIDTH8" value="0x0" desc=""/> | ||
163 | <value name="WIDTH16" value="0x1" desc=""/> | ||
164 | <value name="WIDTH32" value="0x2" desc=""/> | ||
165 | </field> | ||
166 | <field name="DFXS" desc="If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than DTRANWID. If DFXS=1, DMA will always transfer in DTRANWID. " bitrange="16:16"/> | ||
167 | <field name="SBURLEN" desc="Source burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary." bitrange="15:13"> | ||
168 | <value name="SINGLE" value="0x0" desc=""/> | ||
169 | <value name="INCR4" value="0x3" desc=""/> | ||
170 | <value name="INCR8" value="0x5" desc=""/> | ||
171 | </field> | ||
172 | <field name="SDSP" desc="Source DSP mode. " bitrange="11:11"/> | ||
173 | <field name="SCOL" desc="Source Column Mode." bitrange="10:10"/> | ||
174 | <field name="SDIR" desc="Source address direction. If SBURLEN is INCR4 or INCR8 only INCREASE is allowed." bitrange="9:9"> | ||
175 | <value name="INCREASE" value="0x0" desc=""/> | ||
176 | <value name="DECREASE" value="0x1" desc=""/> | ||
177 | </field> | ||
178 | <field name="SFXA" desc="Source Fixed Addres bit." bitrange="8:8"> | ||
179 | <value name="NOT_FIXED" value="0x0" desc=""/> | ||
180 | <value name="FIXED" value="0x1" desc=""/> | ||
181 | </field> | ||
182 | <field name="STRG" desc="DRQ trig source." bitrange="7:3"> | ||
183 | <value name="DAC" value="0x6" desc=""/> | ||
184 | <value name="SDRAM" value="0x10" desc=""/> | ||
185 | <value name="IRAM" value="0x11" desc=""/> | ||
186 | <value name="SD" value="0x16" desc=""/> | ||
187 | <value name="OTG" value="0x17" desc=""/> | ||
188 | <value name="LCM" value="0x18" desc=""/> | ||
189 | </field> | ||
190 | <field name="STRANWID" desc="" bitrange="2:1"> | ||
191 | <value name="WIDTH8" value="0x0" desc=""/> | ||
192 | <value name="WIDTH16" value="0x1" desc=""/> | ||
193 | <value name="WIDTH32" value="0x2" desc=""/> | ||
194 | </field> | ||
195 | <field name="SFXS" desc="Source Fix Size. If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than STRANWID. If SFXS=1, DMA will always transfer in STRANWID." bitrange="0:0"/> | ||
196 | </reg> | ||
197 | <reg name="DMA_SRC" desc=""> | ||
198 | <addr name="DMA0_SRC" addr="0x104"/> | ||
199 | <addr name="DMA1_SRC" addr="0x204"/> | ||
200 | <addr name="DMA2_SRC" addr="0x304"/> | ||
201 | <addr name="DMA3_SRC" addr="0x404"/> | ||
202 | <addr name="DMA4_SRC" addr="0x504"/> | ||
203 | <addr name="DMA5_SRC" addr="0x604"/> | ||
204 | <addr name="DMA6_SRC" addr="0x704"/> | ||
205 | <addr name="DMA7_SRC" addr="0x804"/> | ||
206 | </reg> | ||
207 | <reg name="DMA_DST" desc=""> | ||
208 | <addr name="DMA0_DST" addr="0x108"/> | ||
209 | <addr name="DMA1_DST" addr="0x208"/> | ||
210 | <addr name="DMA2_DST" addr="0x308"/> | ||
211 | <addr name="DMA3_DST" addr="0x408"/> | ||
212 | <addr name="DMA4_DST" addr="0x508"/> | ||
213 | <addr name="DMA5_DST" addr="0x608"/> | ||
214 | <addr name="DMA6_DST" addr="0x708"/> | ||
215 | <addr name="DMA7_DST" addr="0x808"/> | ||
216 | </reg> | ||
217 | <reg name="DMA_CNT" desc=""> | ||
218 | <addr name="DMA0_CNT" addr="0x10c"/> | ||
219 | <addr name="DMA1_CNT" addr="0x20c"/> | ||
220 | <addr name="DMA2_CNT" addr="0x30c"/> | ||
221 | <addr name="DMA3_CNT" addr="0x40c"/> | ||
222 | <addr name="DMA4_CNT" addr="0x50c"/> | ||
223 | <addr name="DMA5_CNT" addr="0x60c"/> | ||
224 | <addr name="DMA6_CNT" addr="0x70c"/> | ||
225 | <addr name="DMA7_CNT" addr="0x80c"/> | ||
226 | </reg> | ||
227 | <reg name="DMA_REM" desc=""> | ||
228 | <addr name="DMA0_REM" addr="0x110"/> | ||
229 | <addr name="DMA1_REM" addr="0x210"/> | ||
230 | <addr name="DMA2_REM" addr="0x310"/> | ||
231 | <addr name="DMA3_REM" addr="0x410"/> | ||
232 | <addr name="DMA4_REM" addr="0x510"/> | ||
233 | <addr name="DMA5_REM" addr="0x610"/> | ||
234 | <addr name="DMA6_REM" addr="0x710"/> | ||
235 | <addr name="DMA7_REM" addr="0x810"/> | ||
236 | </reg> | ||
237 | <reg name="DMA_CMD" desc=""> | ||
238 | <addr name="DMA0_CMD" addr="0x114"/> | ||
239 | <addr name="DMA1_CMD" addr="0x214"/> | ||
240 | <addr name="DMA2_CMD" addr="0x314"/> | ||
241 | <addr name="DMA3_CMD" addr="0x414"/> | ||
242 | <addr name="DMA4_CMD" addr="0x514"/> | ||
243 | <addr name="DMA5_CMD" addr="0x614"/> | ||
244 | <addr name="DMA6_CMD" addr="0x714"/> | ||
245 | <addr name="DMA7_CMD" addr="0x814"/> | ||
246 | </reg> | ||
247 | </dev> | ||
248 | <dev name="DSP" long_name="Digital Signal Processor" desc="" version="1.0"> | ||
249 | <addr name="DSP" addr="0xb0050000"/> | ||
250 | <reg name="HDR" desc="HIP data registers"> | ||
251 | <addr name="HDR0" addr="0x0"/> | ||
252 | <addr name="HDR1" addr="0x4"/> | ||
253 | <addr name="HDR2" addr="0x8"/> | ||
254 | <addr name="HDR3" addr="0xc"/> | ||
255 | <addr name="HDR4" addr="0x10"/> | ||
256 | <addr name="HDR5" addr="0x14"/> | ||
257 | <addr name="HSR6" addr="0x18"/> | ||
258 | <addr name="HSR7" addr="0x1c"/> | ||
259 | </reg> | ||
260 | <reg name="CTL" desc=""> | ||
261 | <addr name="CTL" addr="0x20"/> | ||
262 | </reg> | ||
263 | </dev> | ||
264 | <dev name="GPIO" long_name="" desc="" version="1.0"> | ||
265 | <addr name="GPIO" addr="0xb01c0000"/> | ||
266 | </dev> | ||
267 | <dev name="I2C" long_name="" desc="" version="1.0"> | ||
268 | <addr name="I2C0" addr="0xb0180000"/> | ||
269 | <addr name="I2C1" addr="0xb0180020"/> | ||
270 | </dev> | ||
271 | <dev name="INTC" long_name="Interrupt Controller" desc="" version="1.0"> | ||
272 | <addr name="INTC" addr="0xb0020000"/> | ||
273 | <reg name="PD" desc=""> | ||
274 | <addr name="PD" addr="0x0"/> | ||
275 | </reg> | ||
276 | <reg name="MSK" desc=""> | ||
277 | <addr name="MSK" addr="0x4"/> | ||
278 | </reg> | ||
279 | <reg name="CFG" desc=""> | ||
280 | <addr name="CFG0" addr="0x8"/> | ||
281 | <addr name="CFG1" addr="0xc"/> | ||
282 | <addr name="CFG2" addr="0x10"/> | ||
283 | </reg> | ||
284 | <reg name="EXTCTL" desc=""> | ||
285 | <addr name="EXTCTL" addr="0x14"/> | ||
286 | </reg> | ||
287 | </dev> | ||
288 | <dev name="IR" long_name="" desc="" version="1.0"> | ||
289 | <addr name="IR" addr="0xb0160010"/> | ||
290 | </dev> | ||
291 | <dev name="KEY" long_name="" desc="" version="1.0"> | ||
292 | <addr name="KEY" addr="0xb01a0000"/> | ||
293 | </dev> | ||
294 | <dev name="MCA" long_name="Motion Compensation Accelerator" desc="" version="1.0"> | ||
295 | <addr name="MCA" addr="0xb0080000"/> | ||
296 | <reg name="CTL" desc=""> | ||
297 | <addr name="CTL" addr="0x0"/> | ||
298 | </reg> | ||
299 | </dev> | ||
300 | <dev name="MHA" long_name="Media Hardware Accelerator" desc="" version="1.0"> | ||
301 | <addr name="MHA" addr="0xb00c0000"/> | ||
302 | <reg name="CTL" desc=""> | ||
303 | <addr name="CTL" addr="0x0"/> | ||
304 | </reg> | ||
305 | <reg name="CFG" desc=""> | ||
306 | <addr name="CFG" addr="0x4"/> | ||
307 | </reg> | ||
308 | <reg name="DCSCLx" desc=""> | ||
309 | <addr name="DCSCL0" addr="0x10"/> | ||
310 | <addr name="DCSCL1" addr="0x14"/> | ||
311 | <addr name="DCSCL2" addr="0x18"/> | ||
312 | <addr name="DCSCL3" addr="0x1c"/> | ||
313 | </reg> | ||
314 | <reg name="QSCL" desc=""> | ||
315 | <addr name="QSCL" addr="0x20"/> | ||
316 | </reg> | ||
317 | </dev> | ||
318 | <dev name="NAND" long_name="NAND Flash Interface" desc="" version="1.0"> | ||
319 | <addr name="NAND" addr="0xb00a0000"/> | ||
320 | <reg name="CTL" desc=""> | ||
321 | <addr name="CTL" addr="0x0"/> | ||
322 | </reg> | ||
323 | <reg name="STATUS" desc=""> | ||
324 | <addr name="STATUS" addr="0x4"/> | ||
325 | </reg> | ||
326 | <reg name="FIFOTIM" desc=""> | ||
327 | <addr name="FIFOTIM" addr="0x8"/> | ||
328 | </reg> | ||
329 | <reg name="CLKCTL" desc=""> | ||
330 | <addr name="CLKCTL" addr="0xc"/> | ||
331 | </reg> | ||
332 | <reg name="BYTECNT" desc=""> | ||
333 | <addr name="BYTECNT" addr="0x10"/> | ||
334 | </reg> | ||
335 | <reg name="ADDR01" desc=""> | ||
336 | <addr name="ADDR01" addr="0x14"/> | ||
337 | </reg> | ||
338 | <reg name="ADDR23" desc=""> | ||
339 | <addr name="ADDR23" addr="0x18"/> | ||
340 | </reg> | ||
341 | <reg name="ADDR45" desc=""> | ||
342 | <addr name="ADDR45" addr="0x1c"/> | ||
343 | </reg> | ||
344 | <reg name="ADDR67" desc=""> | ||
345 | <addr name="ADDR67" addr="0x20"/> | ||
346 | </reg> | ||
347 | <reg name="BUF" desc=""> | ||
348 | <addr name="BUF0" addr="0x24"/> | ||
349 | <addr name="BUF1" addr="0x28"/> | ||
350 | </reg> | ||
351 | <reg name="CMD" desc=""> | ||
352 | <addr name="CMD" addr="0x2c"/> | ||
353 | </reg> | ||
354 | <reg name="ECCCTL" desc=""> | ||
355 | <addr name="ECCCTL" addr="0x30"/> | ||
356 | </reg> | ||
357 | <reg name="HAMECC" desc=""> | ||
358 | <addr name="HAMECC0" addr="0x34"/> | ||
359 | <addr name="HAMECC1" addr="0x38"/> | ||
360 | <addr name="HAMECC2" addr="0x3c"/> | ||
361 | </reg> | ||
362 | <reg name="HAMCEC" desc=""> | ||
363 | <addr name="HAMCEC" addr="0x40"/> | ||
364 | </reg> | ||
365 | <reg name="RSE" desc=""> | ||
366 | <addr name="RSE0" addr="0x44"/> | ||
367 | <addr name="RSE1" addr="0x48"/> | ||
368 | <addr name="RSE2" addr="0x4c"/> | ||
369 | <addr name="RSE3" addr="0x50"/> | ||
370 | </reg> | ||
371 | <reg name="RSPS" desc=""> | ||
372 | <addr name="RSPS0" addr="0x54"/> | ||
373 | <addr name="RSPS1" addr="0x58"/> | ||
374 | <addr name="RSPS2" addr="0x5c"/> | ||
375 | </reg> | ||
376 | <reg name="FIFODATA" desc=""> | ||
377 | <addr name="FIFODATA" addr="0x60"/> | ||
378 | </reg> | ||
379 | <reg name="DEBUG" desc=""> | ||
380 | <addr name="DEBUG" addr="0x70"/> | ||
381 | </reg> | ||
382 | </dev> | ||
383 | <dev name="PCM" long_name="" desc="" version="1.0"> | ||
384 | <addr name="PCM" addr="0xb0150000"/> | ||
385 | </dev> | ||
386 | <dev name="PCNT" long_name="Performance Counters" desc="The base address is not clear!" version="1.0"> | ||
387 | <addr name="PCNT" addr="0xb003c000"/> | ||
388 | <reg name="CTL" desc=""> | ||
389 | <addr name="CTL" addr="0x0"/> | ||
390 | </reg> | ||
391 | <reg name="PCx" desc=""> | ||
392 | <addr name="PC0" addr="0x4"/> | ||
393 | <addr name="PC1" addr="0x8"/> | ||
394 | </reg> | ||
395 | </dev> | ||
396 | <dev name="PMU" long_name="Power Management Unit" desc="" version="1.0"> | ||
397 | <addr name="PMU" addr="0xb0000000"/> | ||
398 | <reg name="CTL" desc=""> | ||
399 | <addr name="CTL" addr="0x0"/> | ||
400 | </reg> | ||
401 | <reg name="LRADC" desc=""> | ||
402 | <addr name="LRADC" addr="0x4"/> | ||
403 | </reg> | ||
404 | <reg name="CHG" desc=""> | ||
405 | <addr name="CHG" addr="0x8"/> | ||
406 | </reg> | ||
407 | </dev> | ||
408 | <dev name="RTCWDT" long_name="Real Time Clock, Timers and Watchdog" desc="" version="1.0"> | ||
409 | <addr name="RTC" addr="0xb0018000"/> | ||
410 | <reg name="CTL" desc=""> | ||
411 | <addr name="CTL" addr="0x0"/> | ||
412 | </reg> | ||
413 | <reg name="DHMS" desc=""> | ||
414 | <addr name="DHMS" addr="0x4"/> | ||
415 | </reg> | ||
416 | <reg name="YMD" desc=""> | ||
417 | <addr name="YMD" addr="0x8"/> | ||
418 | </reg> | ||
419 | <reg name="DHMSALM" desc=""> | ||
420 | <addr name="DHMSALM" addr="0xc"/> | ||
421 | </reg> | ||
422 | <reg name="YMDALM" desc=""> | ||
423 | <addr name="YMDALM" addr="0x10"/> | ||
424 | </reg> | ||
425 | <reg name="WDCTL" desc=""> | ||
426 | <addr name="WDCTL" addr="0x14"/> | ||
427 | </reg> | ||
428 | <reg name="TxCTL" desc=""> | ||
429 | <addr name="T0CTL" addr="0x18"/> | ||
430 | <addr name="T1CTL" addr="0x20"/> | ||
431 | </reg> | ||
432 | <reg name="Tx" desc=""> | ||
433 | <addr name="T0" addr="0x1c"/> | ||
434 | <addr name="T1" addr="0x24"/> | ||
435 | </reg> | ||
436 | </dev> | ||
437 | <dev name="SD" long_name="SD/MMC Interface" desc="" version=""> | ||
438 | <addr name="SD" addr="0xb00b0000"/> | ||
439 | <reg name="CTL" desc=""> | ||
440 | <addr name="CTL" addr="0x0"/> | ||
441 | </reg> | ||
442 | <reg name="CMDRSP" desc=""> | ||
443 | <addr name="CMDRSP" addr="0x4"/> | ||
444 | </reg> | ||
445 | <reg name="RW" desc=""> | ||
446 | <addr name="RW" addr="0x8"/> | ||
447 | </reg> | ||
448 | <reg name="FIFOCTL" desc=""> | ||
449 | <addr name="FIFOCTL" addr="0xc"/> | ||
450 | </reg> | ||
451 | <reg name="CMD" desc=""> | ||
452 | <addr name="CMD" addr="0x10"/> | ||
453 | </reg> | ||
454 | <reg name="ARG" desc=""> | ||
455 | <addr name="ARG" addr="0x14"/> | ||
456 | </reg> | ||
457 | <reg name="CRC7" desc=""> | ||
458 | <addr name="CRC7" addr="0x18"/> | ||
459 | </reg> | ||
460 | <reg name="RSPBUFx" desc=""> | ||
461 | <addr name="RSPBUF0" addr="0x1c"/> | ||
462 | <addr name="RSPBUF1" addr="0x20"/> | ||
463 | <addr name="RSPBUF2" addr="0x24"/> | ||
464 | <addr name="RSPBUF3" addr="0x28"/> | ||
465 | <addr name="RSPBUF4" addr="0x2c"/> | ||
466 | </reg> | ||
467 | <reg name="DAT" desc=""> | ||
468 | <addr name="DAT" addr="0x30"/> | ||
469 | </reg> | ||
470 | <reg name="CLK" desc=""> | ||
471 | <addr name="CLK" addr="0x34"/> | ||
472 | </reg> | ||
473 | <reg name="BYTECNT" desc=""> | ||
474 | <addr name="BYTECNT" addr="0x38"/> | ||
475 | </reg> | ||
476 | </dev> | ||
477 | <dev name="SDR" long_name="SDRAM Interface" desc="" version="1.0"> | ||
478 | <addr name="SDR" addr="0xb0070000"/> | ||
479 | <reg name="CTL" desc=""> | ||
480 | <addr name="CTL" addr="0x0"/> | ||
481 | </reg> | ||
482 | <reg name="ADDRCFG" desc=""> | ||
483 | <addr name="ADDRCFG" addr="0x4"/> | ||
484 | </reg> | ||
485 | <reg name="EN" desc=""> | ||
486 | <addr name="EN" addr="0x8"/> | ||
487 | </reg> | ||
488 | <reg name="CMD" desc=""> | ||
489 | <addr name="CMD" addr="0xc"/> | ||
490 | </reg> | ||
491 | <reg name="STAT" desc=""> | ||
492 | <addr name="STAT" addr="0x10"/> | ||
493 | </reg> | ||
494 | <reg name="RFSH" desc=""> | ||
495 | <addr name="RFSH" addr="0x14"/> | ||
496 | </reg> | ||
497 | <reg name="MODE" desc=""> | ||
498 | <addr name="MODE" addr="0x18"/> | ||
499 | </reg> | ||
500 | <reg name="MOBILE" desc=""> | ||
501 | <addr name="MOBILE" addr="0x1c"/> | ||
502 | </reg> | ||
503 | </dev> | ||
504 | <dev name="SPDIF" long_name="Sony Philips Digital Interface" desc="" version="1.0"> | ||
505 | <addr name="SPDIF" addr="0xb0140000"/> | ||
506 | </dev> | ||
507 | <dev name="SPI" long_name="" desc="" version="1.0"> | ||
508 | <addr name="SPI" addr="0xb0190000"/> | ||
509 | </dev> | ||
510 | <dev name="SRAMOC" long_name="SRAM on Chip" desc="" version="1.0"> | ||
511 | <addr name="SRAMOC" addr="0xb0030000"/> | ||
512 | <reg name="CTL" desc=""> | ||
513 | <addr name="CTL" addr="0x0"/> | ||
514 | </reg> | ||
515 | <reg name="STAT" desc=""> | ||
516 | <addr name="STAT" addr="0x4"/> | ||
517 | </reg> | ||
518 | </dev> | ||
519 | <dev name="TP" long_name="" desc="" version="1.0"> | ||
520 | <addr name="TP" addr="0xb0120000"/> | ||
521 | </dev> | ||
522 | <dev name="UART" long_name="" desc="" version="1.0"> | ||
523 | <addr name="UART0" addr="0xb0160000"/> | ||
524 | <addr name="UART1" addr="0xb0160020"/> | ||
525 | </dev> | ||
526 | <dev name="UDC" long_name="Usb Device Controller" desc="CAST cusb2-otg IP core" version="1.0"> | ||
527 | <addr name="UDC" addr="0xb00e0000"/> | ||
528 | <reg name="EP0BC" desc="ep0 byte count register"> | ||
529 | <addr name="OUT0BC" addr="0x0"/> | ||
530 | <addr name="IN0BC" addr="0x1"/> | ||
531 | <field name="RESERVED" desc="" bitrange="31:8"/> | ||
532 | <field name="BC" desc="" bitrange="7:0"/> | ||
533 | </reg> | ||
534 | <reg name="EP0CS" desc=""> | ||
535 | <addr name="EP0CS" addr="0x2"/> | ||
536 | <field name="RESERVED" desc="" bitrange="31:8"/> | ||
537 | <field name="OUT_BUSY" desc="" bitrange="3:3"/> | ||
538 | <field name="IN_BUSY" desc="" bitrange="2:2"/> | ||
539 | <field name="NAK" desc="Writing 1 clears" bitrange="1:1"/> | ||
540 | <field name="STALL" desc="" bitrange="0:0"/> | ||
541 | </reg> | ||
542 | <reg name="BCL" desc="Endpoint byte count LSB register"> | ||
543 | <addr name="OUT1BCL" addr="0x8"/> | ||
544 | <addr name="IN1BCL" addr="0xc"/> | ||
545 | <addr name="OUT2BCL" addr="0x10"/> | ||
546 | <addr name="IN2BCL" addr="0x14"/> | ||
547 | </reg> | ||
548 | <reg name="BCH" desc="Endpoint byte count MSB"> | ||
549 | <addr name="OUT1BCH" addr="0x9"/> | ||
550 | <addr name="IN1BCH" addr="0xd"/> | ||
551 | <addr name="OUT2BCH" addr="0x11"/> | ||
552 | <addr name="IN2BCH" addr="0x15"/> | ||
553 | </reg> | ||
554 | <reg name="CON" desc="Endpoint configuration register"> | ||
555 | <addr name="OUT1CON" addr="0xa"/> | ||
556 | <addr name="IN1CON" addr="0xe"/> | ||
557 | <addr name="OUT2CON" addr="0x12"/> | ||
558 | <addr name="IN2CON" addr="0x16"/> | ||
559 | <field name="EP_ENABLE" desc="" bitrange="7:7"/> | ||
560 | <field name="STALL" desc="" bitrange="6:6"/> | ||
561 | <field name="EP_TYPE" desc="" bitrange="3:2"> | ||
562 | <value name="RESERVED" value="0x0" desc=""/> | ||
563 | <value name="ISOCHRONOUS" value="0x1" desc=""/> | ||
564 | <value name="BULK" value="0x2" desc=""/> | ||
565 | <value name="INTERRUPT" value="0x3" desc=""/> | ||
566 | </field> | ||
567 | <field name="SUBFIFOS" desc="" bitrange="1:0"> | ||
568 | <value name="SINGLE" value="0x0" desc=""/> | ||
569 | <value name="DOUBLE" value="0x1" desc=""/> | ||
570 | <value name="TRIPLE" value="0x2" desc=""/> | ||
571 | <value name="QUAD" value="0x3" desc=""/> | ||
572 | </field> | ||
573 | </reg> | ||
574 | <reg name="CS" desc="Endpoint status register"> | ||
575 | <addr name="OUT1CS" addr="0xb"/> | ||
576 | <addr name="IN1CS" addr="0xf"/> | ||
577 | <addr name="OUT2CS" addr="0x13"/> | ||
578 | <addr name="IN2CS" addr="0x17"/> | ||
579 | <field name="AUTO" desc="" bitrange="4:4"/> | ||
580 | <field name="NPACK1" desc="" bitrange="3:3"/> | ||
581 | <field name="NPACK0" desc="" bitrange="2:2"/> | ||
582 | <field name="BUSY" desc="" bitrange="1:1"/> | ||
583 | <field name="ERROR" desc="" bitrange="0:0"/> | ||
584 | </reg> | ||
585 | <reg name="FIFODAT" desc="Endpoint FIFO"> | ||
586 | <addr name="FIFO1DAT" addr="0x84"/> | ||
587 | <addr name="FIFO2DAT" addr="0x88"/> | ||
588 | </reg> | ||
589 | <reg name="EP0DAT" desc="Endpoint 0 buffers each 64 bytes long."> | ||
590 | <addr name="EP0INDAT" addr="0x100"/> | ||
591 | <addr name="EP0OUTDAT" addr="0x140"/> | ||
592 | </reg> | ||
593 | <reg name="SETUPDAT" desc="SETUP packet buffer"> | ||
594 | <addr name="SETUPDAT" addr="0x180"/> | ||
595 | </reg> | ||
596 | <reg name="EPIRQ" desc="Endpoint irq flag register"> | ||
597 | <addr name="IN04IRQ" addr="0x188"/> | ||
598 | <addr name="OUT04IRQ" addr="0x18a"/> | ||
599 | <field name="EP_NUM" desc="" bitrange="2:0"/> | ||
600 | </reg> | ||
601 | <reg name="USBIRQ" desc="General usb core irq flags"> | ||
602 | <addr name="USBIRQ" addr="0x18c"/> | ||
603 | <field name="HS" desc="Enter high speed operation. Set by core on connection." bitrange="5:5"/> | ||
604 | <field name="RESET" desc="Asserted on usb reset." bitrange="4:4"/> | ||
605 | <field name="SUSPEND" desc="" bitrange="3:3"/> | ||
606 | <field name="SETUP_TOKEN" desc="" bitrange="2:2"/> | ||
607 | <field name="SOF" desc="" bitrange="1:1"/> | ||
608 | <field name="SETUP_DATA" desc="Setup data are ready to be accessed in SETUPDAT buffer." bitrange="0:0"/> | ||
609 | </reg> | ||
610 | <reg name="EPIEN" desc="Endpoint interrupt enable register"> | ||
611 | <addr name="IN04IEN" addr="0x194"/> | ||
612 | <addr name="OUT04IEN" addr="0x196"/> | ||
613 | <field name="EP_NUM" desc="" bitrange="2:0"/> | ||
614 | </reg> | ||
615 | <reg name="USBIEN" desc="General usb interrupts enable register"> | ||
616 | <addr name="USBIEN" addr="0x198"/> | ||
617 | <field name="HS" desc="" bitrange="5:5"/> | ||
618 | <field name="RESET" desc="" bitrange="4:4"/> | ||
619 | <field name="SUSPEND" desc="" bitrange="3:3"/> | ||
620 | <field name="SETUP_TOKEN" desc="" bitrange="2:2"/> | ||
621 | <field name="SOF" desc="" bitrange="1:1"/> | ||
622 | <field name="SETUP_DATA" desc="" bitrange="0:0"/> | ||
623 | </reg> | ||
624 | <reg name="IVECT" desc="Interrupt vector register known (guessed) values: 0x00 - SETUP 0x10 - RESET 0x14 - HS 0x28 - EPs 0xD8 - OTG"> | ||
625 | <addr name="IVECT" addr="0x1a0"/> | ||
626 | </reg> | ||
627 | <reg name="ENDPRST" desc="Endpoint reset register"> | ||
628 | <addr name="ENDPRST" addr="0x1a2"/> | ||
629 | <field name="FIFO_RESET" desc="" bitrange="6:6"/> | ||
630 | <field name="TOGGLE_RESET" desc="" bitrange="5:5"/> | ||
631 | <field name="DIR" desc="" bitrange="4:4"> | ||
632 | <value name="OUT" value="0x0" desc=""/> | ||
633 | <value name="IN" value="0x1" desc=""/> | ||
634 | </field> | ||
635 | <field name="EP_NUM" desc="" bitrange="2:0"/> | ||
636 | </reg> | ||
637 | <reg name="USBCS" desc=""> | ||
638 | <addr name="USBCS" addr="0x1a3"/> | ||
639 | <field name="SOFT_CONNECT" desc="" bitrange="6:6"/> | ||
640 | <field name="SIGRESUME" desc="" bitrange="5:5"/> | ||
641 | <field name="USBSPEED" desc="" bitrange="1:1"/> | ||
642 | <field name="HCLSMODE" desc="" bitrange="0:0"/> | ||
643 | </reg> | ||
644 | <reg name="FIFOCTRL" desc=""> | ||
645 | <addr name="FIFOCTRL" addr="0x1a8"/> | ||
646 | <field name="DMA" desc="" bitrange="31:0"/> | ||
647 | <field name="CPU_ACCESS" desc="" bitrange="7:7"/> | ||
648 | <field name="DIR" desc="" bitrange="4:4"> | ||
649 | <value name="OUT" value="0x0" desc=""/> | ||
650 | <value name="IN" value="0x1" desc=""/> | ||
651 | </field> | ||
652 | <field name="EP_NUM" desc="" bitrange="2:0"/> | ||
653 | </reg> | ||
654 | <reg name="OTGIRQ" desc=""> | ||
655 | <addr name="OTGIRQ" addr="0x1bc"/> | ||
656 | <field name="PERIPH" desc="" bitrange="4:4"/> | ||
657 | <field name="VBUSERR" desc="" bitrange="3:3"/> | ||
658 | <field name="LOCSOFT" desc="" bitrange="2:2"/> | ||
659 | <field name="SPRDET" desc="" bitrange="1:1"/> | ||
660 | <field name="OTG_IDLE" desc="" bitrange="0:0"/> | ||
661 | </reg> | ||
662 | <reg name="OTGSTATUS" desc=""> | ||
663 | <addr name="OTGSTATUS" addr="0x1bf"/> | ||
664 | </reg> | ||
665 | <reg name="OTGIEN" desc="OTG interrupt enable register"> | ||
666 | <addr name="OTGIEN" addr="0x1c0"/> | ||
667 | </reg> | ||
668 | <reg name="HCMAXPCKL" desc="High speed max packed size LSB"> | ||
669 | <addr name="HCIN1MAXPCKL" addr="0x1e2"/> | ||
670 | <addr name="HCOUT2MAXPCKL" addr="0x3e4"/> | ||
671 | </reg> | ||
672 | <reg name="STADDR" desc="Endpoint buffer start address"> | ||
673 | <addr name="OUT1STADDR " addr="0x304"/> | ||
674 | <addr name="IN2STADDR " addr="0x348"/> | ||
675 | </reg> | ||
676 | <reg name="USBEIRQ" desc="USB extended irq register"> | ||
677 | <addr name="USBEIRQ" addr="0x400"/> | ||
678 | <field name="USB" desc="" bitrange="7:7"/> | ||
679 | <field name="WAKEUP" desc="" bitrange="6:6"/> | ||
680 | <field name="RESUME" desc="" bitrange="5:5"/> | ||
681 | <field name="CONDISCON" desc="" bitrange="4:4"/> | ||
682 | <field name="USBIEN" desc="" bitrange="3:3"/> | ||
683 | <field name="WAKEUPIEN" desc="" bitrange="2:2"/> | ||
684 | <field name="RESUMEIEN" desc="" bitrange="1:1"/> | ||
685 | <field name="CONDISCONIEN" desc="" bitrange="0:0"/> | ||
686 | </reg> | ||
687 | <reg name="USBERST" desc=""> | ||
688 | <addr name="USBERST" addr="0x404"/> | ||
689 | </reg> | ||
690 | <reg name="DMAEPSEL" desc=""> | ||
691 | <addr name="DMAEPSEL" addr="0x40c"/> | ||
692 | <field name="EP_SEL" desc="" bitrange="31:0"> | ||
693 | <value name="UNKNOWN" value="0x0" desc=""/> | ||
694 | <value name="EP1_IN" value="0x1" desc=""/> | ||
695 | <value name="EP1_OUT" value="0x3" desc=""/> | ||
696 | <value name="EP2_IN" value="0x4" desc=""/> | ||
697 | <value name="EP2_OUT" value="0xc" desc=""/> | ||
698 | </field> | ||
699 | </reg> | ||
700 | </dev> | ||
701 | <dev name="YUV2RGB" long_name="Color Space Conversion Accelerator" desc="" version=""> | ||
702 | <addr name="YUV2RGB" addr="0xb00f0000"/> | ||
703 | <reg name="CTL" desc=""> | ||
704 | <addr name="CTL" addr="0x0"/> | ||
705 | <field name="RESERVED" desc="" bitrange="31:22"/> | ||
706 | <field name="RFBM" desc="Read fifo block mode." bitrange="21:21"/> | ||
707 | <field name="WFBM" desc="Write fifo block mode" bitrange="20:20"/> | ||
708 | <field name="EN" desc="RGB Decoder enable." bitrange="19:19"/> | ||
709 | <field name="FES" desc="Fifo empty status." bitrange="18:18"/> | ||
710 | <field name="WDCS" desc="Write Data/Command Select" bitrange="17:16"> | ||
711 | <value name="CMD" value="0x0" desc="Write LCD register address"/> | ||
712 | <value name="DATA" value="0x1" desc="Write LCD register data"/> | ||
713 | <value name="RGB" value="0x2" desc="RGB565 Data FrameBuffer Transfer"/> | ||
714 | <value name="YUV" value="0x3" desc="YCbCr/YUV Data FrameBuffer Transfer"/> | ||
715 | </field> | ||
716 | <field name="DEST" desc="RGB Decoder Destination." bitrange="15:15"/> | ||
717 | <field name="FORMATS" desc="RGB Format" bitrange="13:11"> | ||
718 | <value name="RGB565_1" value="0x0" desc="16bit (RGB 565 1transfer)"/> | ||
719 | <value name="RGB666_1" value="0x1" desc="18bit (RGB 666 1transfer)"/> | ||
720 | <value name="RGB565_2" value="0x2" desc="8bit (RGB 565 2transfers)"/> | ||
721 | <value name="RGB666_2" value="0x3" desc="9bit (RGB 666 2transfers)"/> | ||
722 | <value name="RGB888_3" value="0x4" desc="8bit (RGB 888 3transfers)"/> | ||
723 | <value name="RGB666_3" value="0x5" desc="6bit (RGB 666 3transfers)"/> | ||
724 | </field> | ||
725 | <field name="SEQ" desc="RGB Sequence" bitrange="10:10"> | ||
726 | <value name="RGB" value="0x0" desc=""/> | ||
727 | <value name="BGR" value="0x1" desc=""/> | ||
728 | </field> | ||
729 | <field name="FWCS" desc="FIFO write channel select." bitrange="9:9"> | ||
730 | <value name="SPECIAL" value="0x0" desc=""/> | ||
731 | <value name="AHB" value="0x1" desc=""/> | ||
732 | </field> | ||
733 | <field name="FRCS" desc="FIFO read channel select" bitrange="8:8"> | ||
734 | <value name="SPECIAL" value="0x0" desc=""/> | ||
735 | <value name="AHB" value="0x1" desc=""/> | ||
736 | </field> | ||
737 | <field name="EMDE" desc="FIFO Empty (Write) DRQ Enable." bitrange="7:7"/> | ||
738 | <field name="EMIE" desc="FIFO Empty (Write) IRQ Enable." bitrange="6:6"/> | ||
739 | <field name="FUDE" desc="FIFO Full (Read) DRQ Enable." bitrange="5:5"/> | ||
740 | <field name="FUIE" desc="FIFO Full (Read) IRQ Enable." bitrange="4:4"/> | ||
741 | <field name="EMCO" desc="FIFO Empty (Write) Condition." bitrange="3:3"> | ||
742 | <value name="EMPTY_4_8" value="0x0" desc=""/> | ||
743 | <value name="EMPTY_0_8" value="0x1" desc=""/> | ||
744 | </field> | ||
745 | <field name="EMIP" desc="FIFO Empty (Write) IRQ Pending Bit." bitrange="2:2"/> | ||
746 | <field name="FUIP" desc="FIFO Full (Read) IRQ Pending Bit." bitrange="1:1"/> | ||
747 | <field name="ERP" desc="FIFO Error Pending Bit. Write 1 to the bit to clear it and reset the FIFO." bitrange="0:0"/> | ||
748 | </reg> | ||
749 | <reg name="FIFODATA" desc=""> | ||
750 | <addr name="FIFODATA" addr="0x4"/> | ||
751 | </reg> | ||
752 | <reg name="CLKCTL" desc=""> | ||
753 | <addr name="CLKCTL" addr="0x8"/> | ||
754 | </reg> | ||
755 | <reg name="FRAMECOUNT" desc=""> | ||
756 | <addr name="FRAMECOUNT" addr="0xc"/> | ||
757 | </reg> | ||
758 | </dev> | ||
759 | </soc> | ||