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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2016-08-02 15:18:41 +0100 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2017-01-24 15:25:14 +0100 |
| commit | 56340f4cd0a6ab318a52d2a62ded36aad2946e1d (patch) | |
| tree | 32cb9a8380131b93249abd4ab68d2ebaf7dcc541 /utils/hwstub/tools/lua/jz | |
| parent | 83155f32bfa3e8f3641b81098744431f6fc59e56 (diff) | |
| download | rockbox-56340f4cd0a6ab318a52d2a62ded36aad2946e1d.tar.gz rockbox-56340f4cd0a6ab318a52d2a62ded36aad2946e1d.zip | |
hwstub: add the possibility to flush caches before exec
This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h
Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e
Diffstat (limited to 'utils/hwstub/tools/lua/jz')
0 files changed, 0 insertions, 0 deletions