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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-07-13 17:35:53 +0200 |
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committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-07-13 17:47:01 +0200 |
commit | 140783ef66eef379feedcfef5403c5729d38936a (patch) | |
tree | 0185a6a6ef80ab134150454674a1d7e1333b8757 /utils/hwstub/stub/usb_drv_arc.c | |
parent | 3dd5e983db8d83113cc76ee0f5c02e158380606a (diff) | |
download | rockbox-140783ef66eef379feedcfef5403c5729d38936a.tar.gz rockbox-140783ef66eef379feedcfef5403c5729d38936a.zip |
hwstub: split target specific code from the common part
Completely rewrite the Mafile, properly put the usb driver in its
own file and the target specific files in a subdirectory.
Change-Id: Iaeee0128e021d5dad76b4d6035a63e33e2d946c1
Diffstat (limited to 'utils/hwstub/stub/usb_drv_arc.c')
-rw-r--r-- | utils/hwstub/stub/usb_drv_arc.c | 364 |
1 files changed, 364 insertions, 0 deletions
diff --git a/utils/hwstub/stub/usb_drv_arc.c b/utils/hwstub/stub/usb_drv_arc.c new file mode 100644 index 0000000000..32275b6adb --- /dev/null +++ b/utils/hwstub/stub/usb_drv_arc.c | |||
@@ -0,0 +1,364 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Driver for ARC USBOTG Device Controller | ||
11 | * | ||
12 | * Copyright (C) 2007 by Björn Stenberg | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #include "usb_drv.h" | ||
24 | #include "config.h" | ||
25 | #include "memory.h" | ||
26 | |||
27 | #define MAX_PKT_SIZE 1024 | ||
28 | #define MAX_PKT_SIZE_EP0 64 | ||
29 | |||
30 | /* USB device mode registers (Little Endian) */ | ||
31 | #define REG_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140)) | ||
32 | #define REG_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154)) | ||
33 | #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158)) | ||
34 | #define REG_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184)) | ||
35 | #define REG_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8)) | ||
36 | #define REG_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac)) | ||
37 | #define REG_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0)) | ||
38 | #define REG_ENDPTSTATUS (*(volatile unsigned int *)(USB_BASE+0x1b8)) | ||
39 | #define REG_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc)) | ||
40 | #define REG_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0)) | ||
41 | #define REG_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4)) | ||
42 | #define REG_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8)) | ||
43 | #define REG_ENDPTCTRL(_x_) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_))) | ||
44 | |||
45 | /* USB CMD Register Bit Masks */ | ||
46 | #define USBCMD_RUN (0x00000001) | ||
47 | #define USBCMD_CTRL_RESET (0x00000002) | ||
48 | #define USBCMD_PERIODIC_SCHEDULE_EN (0x00000010) | ||
49 | #define USBCMD_ASYNC_SCHEDULE_EN (0x00000020) | ||
50 | #define USBCMD_INT_AA_DOORBELL (0x00000040) | ||
51 | #define USBCMD_ASP (0x00000300) | ||
52 | #define USBCMD_ASYNC_SCH_PARK_EN (0x00000800) | ||
53 | #define USBCMD_SUTW (0x00002000) | ||
54 | #define USBCMD_ATDTW (0x00004000) | ||
55 | #define USBCMD_ITC (0x00FF0000) | ||
56 | |||
57 | /* Device Address bit masks */ | ||
58 | #define USBDEVICEADDRESS_MASK (0xFE000000) | ||
59 | #define USBDEVICEADDRESS_BIT_POS (25) | ||
60 | |||
61 | /* Endpoint Setup Status bit masks */ | ||
62 | #define EPSETUP_STATUS_EP0 (0x00000001) | ||
63 | |||
64 | /* PORTSCX Register Bit Masks */ | ||
65 | #define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001) | ||
66 | #define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002) | ||
67 | #define PORTSCX_PORT_ENABLE (0x00000004) | ||
68 | #define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008) | ||
69 | #define PORTSCX_OVER_CURRENT_ACT (0x00000010) | ||
70 | #define PORTSCX_OVER_CURRENT_CHG (0x00000020) | ||
71 | #define PORTSCX_PORT_FORCE_RESUME (0x00000040) | ||
72 | #define PORTSCX_PORT_SUSPEND (0x00000080) | ||
73 | #define PORTSCX_PORT_RESET (0x00000100) | ||
74 | #define PORTSCX_LINE_STATUS_BITS (0x00000C00) | ||
75 | #define PORTSCX_PORT_POWER (0x00001000) | ||
76 | #define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000) | ||
77 | #define PORTSCX_PORT_TEST_CTRL (0x000F0000) | ||
78 | #define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000) | ||
79 | #define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000) | ||
80 | #define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000) | ||
81 | #define PORTSCX_PHY_LOW_POWER_SPD (0x00800000) | ||
82 | #define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000) | ||
83 | #define PORTSCX_PORT_SPEED_MASK (0x0C000000) | ||
84 | #define PORTSCX_PORT_WIDTH (0x10000000) | ||
85 | #define PORTSCX_PHY_TYPE_SEL (0xC0000000) | ||
86 | |||
87 | /* bit 11-10 are line status */ | ||
88 | #define PORTSCX_LINE_STATUS_SE0 (0x00000000) | ||
89 | #define PORTSCX_LINE_STATUS_JSTATE (0x00000400) | ||
90 | #define PORTSCX_LINE_STATUS_KSTATE (0x00000800) | ||
91 | #define PORTSCX_LINE_STATUS_UNDEF (0x00000C00) | ||
92 | #define PORTSCX_LINE_STATUS_BIT_POS (10) | ||
93 | |||
94 | /* bit 15-14 are port indicator control */ | ||
95 | #define PORTSCX_PIC_OFF (0x00000000) | ||
96 | #define PORTSCX_PIC_AMBER (0x00004000) | ||
97 | #define PORTSCX_PIC_GREEN (0x00008000) | ||
98 | #define PORTSCX_PIC_UNDEF (0x0000C000) | ||
99 | #define PORTSCX_PIC_BIT_POS (14) | ||
100 | |||
101 | /* bit 19-16 are port test control */ | ||
102 | #define PORTSCX_PTC_DISABLE (0x00000000) | ||
103 | #define PORTSCX_PTC_JSTATE (0x00010000) | ||
104 | #define PORTSCX_PTC_KSTATE (0x00020000) | ||
105 | #define PORTSCX_PTC_SE0NAK (0x00030000) | ||
106 | #define PORTSCX_PTC_PACKET (0x00040000) | ||
107 | #define PORTSCX_PTC_FORCE_EN (0x00050000) | ||
108 | #define PORTSCX_PTC_BIT_POS (16) | ||
109 | |||
110 | /* bit 27-26 are port speed */ | ||
111 | #define PORTSCX_PORT_SPEED_FULL (0x00000000) | ||
112 | #define PORTSCX_PORT_SPEED_LOW (0x04000000) | ||
113 | #define PORTSCX_PORT_SPEED_HIGH (0x08000000) | ||
114 | #define PORTSCX_PORT_SPEED_UNDEF (0x0C000000) | ||
115 | #define PORTSCX_SPEED_BIT_POS (26) | ||
116 | |||
117 | /* bit 28 is parallel transceiver width for UTMI interface */ | ||
118 | #define PORTSCX_PTW (0x10000000) | ||
119 | #define PORTSCX_PTW_8BIT (0x00000000) | ||
120 | #define PORTSCX_PTW_16BIT (0x10000000) | ||
121 | |||
122 | /* bit 31-30 are port transceiver select */ | ||
123 | #define PORTSCX_PTS_UTMI (0x00000000) | ||
124 | #define PORTSCX_PTS_CLASSIC (0x40000000) | ||
125 | #define PORTSCX_PTS_ULPI (0x80000000) | ||
126 | #define PORTSCX_PTS_FSLS (0xC0000000) | ||
127 | #define PORTSCX_PTS_BIT_POS (30) | ||
128 | |||
129 | /* USB MODE Register Bit Masks */ | ||
130 | #define USBMODE_CTRL_MODE_IDLE (0x00000000) | ||
131 | #define USBMODE_CTRL_MODE_DEVICE (0x00000002) | ||
132 | #define USBMODE_CTRL_MODE_HOST (0x00000003) | ||
133 | #define USBMODE_CTRL_MODE_RSV (0x00000001) | ||
134 | #define USBMODE_SETUP_LOCK_OFF (0x00000008) | ||
135 | #define USBMODE_STREAM_DISABLE (0x00000010) | ||
136 | |||
137 | /* ENDPOINTCTRLx Register Bit Masks */ | ||
138 | #define EPCTRL_TX_ENABLE (0x00800000) | ||
139 | #define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */ | ||
140 | #define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */ | ||
141 | #define EPCTRL_TX_TYPE (0x000C0000) | ||
142 | #define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */ | ||
143 | #define EPCTRL_TX_EP_STALL (0x00010000) | ||
144 | #define EPCTRL_RX_ENABLE (0x00000080) | ||
145 | #define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */ | ||
146 | #define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */ | ||
147 | #define EPCTRL_RX_TYPE (0x0000000C) | ||
148 | #define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */ | ||
149 | #define EPCTRL_RX_EP_STALL (0x00000001) | ||
150 | |||
151 | /* bit 19-18 and 3-2 are endpoint type */ | ||
152 | #define EPCTRL_TX_EP_TYPE_SHIFT (18) | ||
153 | #define EPCTRL_RX_EP_TYPE_SHIFT (2) | ||
154 | |||
155 | #define QH_MULT_POS (30) | ||
156 | #define QH_ZLT_SEL (0x20000000) | ||
157 | #define QH_MAX_PKT_LEN_POS (16) | ||
158 | #define QH_IOS (0x00008000) | ||
159 | #define QH_NEXT_TERMINATE (0x00000001) | ||
160 | #define QH_IOC (0x00008000) | ||
161 | #define QH_MULTO (0x00000C00) | ||
162 | #define QH_STATUS_HALT (0x00000040) | ||
163 | #define QH_STATUS_ACTIVE (0x00000080) | ||
164 | #define EP_QUEUE_CURRENT_OFFSET_MASK (0x00000FFF) | ||
165 | #define EP_QUEUE_HEAD_NEXT_POINTER_MASK (0xFFFFFFE0) | ||
166 | #define EP_QUEUE_FRINDEX_MASK (0x000007FF) | ||
167 | #define EP_MAX_LENGTH_TRANSFER (0x4000) | ||
168 | |||
169 | #define DTD_NEXT_TERMINATE (0x00000001) | ||
170 | #define DTD_IOC (0x00008000) | ||
171 | #define DTD_STATUS_ACTIVE (0x00000080) | ||
172 | #define DTD_STATUS_HALTED (0x00000040) | ||
173 | #define DTD_STATUS_DATA_BUFF_ERR (0x00000020) | ||
174 | #define DTD_STATUS_TRANSACTION_ERR (0x00000008) | ||
175 | #define DTD_RESERVED_FIELDS (0x80007300) | ||
176 | #define DTD_ADDR_MASK (0xFFFFFFE0) | ||
177 | #define DTD_PACKET_SIZE (0x7FFF0000) | ||
178 | #define DTD_LENGTH_BIT_POS (16) | ||
179 | #define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ | ||
180 | DTD_STATUS_DATA_BUFF_ERR | \ | ||
181 | DTD_STATUS_TRANSACTION_ERR) | ||
182 | /*-------------------------------------------------------------------------*/ | ||
183 | /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */ | ||
184 | struct transfer_descriptor { | ||
185 | unsigned int next_td_ptr; /* Next TD pointer(31-5), T(0) set | ||
186 | indicate invalid */ | ||
187 | unsigned int size_ioc_sts; /* Total bytes (30-16), IOC (15), | ||
188 | MultO(11-10), STS (7-0) */ | ||
189 | unsigned int buff_ptr0; /* Buffer pointer Page 0 */ | ||
190 | unsigned int buff_ptr1; /* Buffer pointer Page 1 */ | ||
191 | unsigned int buff_ptr2; /* Buffer pointer Page 2 */ | ||
192 | unsigned int buff_ptr3; /* Buffer pointer Page 3 */ | ||
193 | unsigned int buff_ptr4; /* Buffer pointer Page 4 */ | ||
194 | unsigned int reserved; | ||
195 | } __attribute__ ((packed)); | ||
196 | |||
197 | static struct transfer_descriptor td_array[USB_NUM_ENDPOINTS*2] | ||
198 | __attribute__((aligned(32))); | ||
199 | |||
200 | /* manual: 32.13.1 Endpoint Queue Head (dQH) */ | ||
201 | struct queue_head { | ||
202 | unsigned int max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len | ||
203 | and IOS(15) */ | ||
204 | unsigned int curr_dtd_ptr; /* Current dTD Pointer(31-5) */ | ||
205 | struct transfer_descriptor dtd; /* dTD overlay */ | ||
206 | unsigned int setup_buffer[2]; /* Setup data 8 bytes */ | ||
207 | unsigned int reserved; /* for software use, pointer to the first TD */ | ||
208 | unsigned int status; /* for software use, status of chain in progress */ | ||
209 | unsigned int length; /* for software use, transfered bytes of chain in progress */ | ||
210 | unsigned int wait; /* for softwate use, indicates if the transfer is blocking */ | ||
211 | } __attribute__((packed)); | ||
212 | |||
213 | static struct queue_head qh_array[USB_NUM_ENDPOINTS*2] __attribute__((aligned(2048))); | ||
214 | |||
215 | static const unsigned int pipe2mask[] = { | ||
216 | 0x01, 0x010000, | ||
217 | 0x02, 0x020000, | ||
218 | 0x04, 0x040000, | ||
219 | 0x08, 0x080000, | ||
220 | 0x10, 0x100000, | ||
221 | }; | ||
222 | |||
223 | /* return transfered size if wait=true */ | ||
224 | static int prime_transfer(int ep_num, void *ptr, int len, bool send, bool wait) | ||
225 | { | ||
226 | int pipe = ep_num * 2 + (send ? 1 : 0); | ||
227 | unsigned mask = pipe2mask[pipe]; | ||
228 | struct transfer_descriptor *td = &td_array[pipe]; | ||
229 | struct queue_head* qh = &qh_array[pipe]; | ||
230 | |||
231 | /* prepare TD */ | ||
232 | td->next_td_ptr = DTD_NEXT_TERMINATE; | ||
233 | td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE; | ||
234 | td->buff_ptr0 = (unsigned int)ptr; | ||
235 | td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000; | ||
236 | td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000; | ||
237 | td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000; | ||
238 | td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000; | ||
239 | td->reserved = 0; | ||
240 | /* prime */ | ||
241 | qh->dtd.next_td_ptr = (unsigned int)td; | ||
242 | qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE); | ||
243 | REG_ENDPTPRIME |= mask; | ||
244 | /* wait for priming to be taken into account */ | ||
245 | while(!(REG_ENDPTSTATUS & mask)); | ||
246 | /* wait for completion */ | ||
247 | if(wait) | ||
248 | { | ||
249 | while(!(REG_ENDPTCOMPLETE & mask)); | ||
250 | REG_ENDPTCOMPLETE = mask; | ||
251 | /* memory barrier */ | ||
252 | asm volatile("":::"memory"); | ||
253 | /* return transfered size */ | ||
254 | return len - (td->size_ioc_sts >> DTD_LENGTH_BIT_POS); | ||
255 | } | ||
256 | else | ||
257 | return 0; | ||
258 | } | ||
259 | |||
260 | void usb_drv_set_address(int address) | ||
261 | { | ||
262 | REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS; | ||
263 | } | ||
264 | |||
265 | /* endpoints */ | ||
266 | |||
267 | int usb_drv_send_nonblocking(int endpoint, void* ptr, int length) | ||
268 | { | ||
269 | return prime_transfer(EP_NUM(endpoint), ptr, length, true, false); | ||
270 | } | ||
271 | |||
272 | int usb_drv_send(int endpoint, void* ptr, int length) | ||
273 | { | ||
274 | return prime_transfer(EP_NUM(endpoint), ptr, length, true, true); | ||
275 | } | ||
276 | |||
277 | int usb_drv_recv(int endpoint, void* ptr, int length) | ||
278 | { | ||
279 | return prime_transfer(EP_NUM(endpoint), ptr, length, false, true); | ||
280 | } | ||
281 | |||
282 | int usb_drv_recv_nonblocking(int endpoint, void* ptr, int length) | ||
283 | { | ||
284 | return prime_transfer(EP_NUM(endpoint), ptr, length, false, false); | ||
285 | } | ||
286 | |||
287 | int usb_drv_port_speed(void) | ||
288 | { | ||
289 | return (REG_PORTSC1 & 0x08000000) ? 1 : 0; | ||
290 | } | ||
291 | |||
292 | void usb_drv_stall(int endpoint, bool stall, bool in) | ||
293 | { | ||
294 | int ep_num = EP_NUM(endpoint); | ||
295 | |||
296 | if(in) | ||
297 | { | ||
298 | if(stall) | ||
299 | REG_ENDPTCTRL(ep_num) |= EPCTRL_TX_EP_STALL; | ||
300 | else | ||
301 | REG_ENDPTCTRL(ep_num) &= ~EPCTRL_TX_EP_STALL; | ||
302 | } | ||
303 | else | ||
304 | { | ||
305 | if (stall) | ||
306 | REG_ENDPTCTRL(ep_num) |= EPCTRL_RX_EP_STALL; | ||
307 | else | ||
308 | REG_ENDPTCTRL(ep_num) &= ~EPCTRL_RX_EP_STALL; | ||
309 | } | ||
310 | } | ||
311 | |||
312 | void usb_drv_configure_endpoint(int ep_num, int type) | ||
313 | { | ||
314 | REG_ENDPTCTRL(ep_num) = | ||
315 | EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE | | ||
316 | EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE | | ||
317 | (type << EPCTRL_RX_EP_TYPE_SHIFT) | | ||
318 | (type << EPCTRL_TX_EP_TYPE_SHIFT); | ||
319 | } | ||
320 | |||
321 | void usb_drv_init(void) | ||
322 | { | ||
323 | /* we don't know if USB was connected or not. In USB recovery mode it will | ||
324 | * but in other cases it might not be. In doubt, disconnect */ | ||
325 | REG_USBCMD &= ~USBCMD_RUN; | ||
326 | /* reset the controller */ | ||
327 | REG_USBCMD |= USBCMD_CTRL_RESET; | ||
328 | while (REG_USBCMD & USBCMD_CTRL_RESET); | ||
329 | /* put it in device mode */ | ||
330 | REG_USBMODE = USBMODE_CTRL_MODE_DEVICE; | ||
331 | /* reset address */ | ||
332 | REG_DEVICEADDR = 0; | ||
333 | /* prepare qh array */ | ||
334 | qh_array[0].max_pkt_length = 1 << 29 | MAX_PKT_SIZE_EP0 << 16; | ||
335 | qh_array[1].max_pkt_length = 1 << 29 | MAX_PKT_SIZE_EP0 << 16; | ||
336 | qh_array[2].max_pkt_length = 1 << 29 | MAX_PKT_SIZE << 16; | ||
337 | qh_array[3].max_pkt_length = 1 << 29 | MAX_PKT_SIZE << 16; | ||
338 | /* setup qh */ | ||
339 | REG_ENDPOINTLISTADDR = (unsigned int)qh_array; | ||
340 | /* clear setup status */ | ||
341 | REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0; | ||
342 | /* run! */ | ||
343 | REG_USBCMD |= USBCMD_RUN; | ||
344 | } | ||
345 | |||
346 | void usb_drv_exit(void) | ||
347 | { | ||
348 | REG_USBCMD &= ~USBCMD_RUN; | ||
349 | REG_USBCMD |= USBCMD_CTRL_RESET; | ||
350 | } | ||
351 | |||
352 | int usb_drv_recv_setup(struct usb_ctrlrequest *req) | ||
353 | { | ||
354 | /* wait for setup */ | ||
355 | while(!(REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) | ||
356 | ; | ||
357 | /* clear setup status */ | ||
358 | REG_ENDPTSETUPSTAT = EPSETUP_STATUS_EP0; | ||
359 | /* check request */ | ||
360 | asm volatile("":::"memory"); | ||
361 | /* copy */ | ||
362 | memcpy(req, (void *)&qh_array[0].setup_buffer[0], sizeof(struct usb_ctrlrequest)); | ||
363 | return 0; | ||
364 | } | ||