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authorMarcin Bukat <marcin.bukat@gmail.com>2013-07-18 23:55:35 +0200
committerMarcin Bukat <marcin.bukat@gmail.com>2013-11-24 00:10:36 +0100
commit8e633385912494ff5e871ec4c264d3a7db46fb98 (patch)
treea8d6b23861969b7df72bb79695ad742082ce2b02 /utils/hwstub/stub/rk27xx
parent1ed57aaa5049d2bbe4e94bed6674bd405e98a4a5 (diff)
downloadrockbox-8e633385912494ff5e871ec4c264d3a7db46fb98.tar.gz
rockbox-8e633385912494ff5e871ec4c264d3a7db46fb98.zip
hwstub rk27xx port
Change-Id: I85ac57117911544b65ccd56eb16303e30be67cab
Diffstat (limited to 'utils/hwstub/stub/rk27xx')
-rw-r--r--utils/hwstub/stub/rk27xx/Makefile14
-rw-r--r--utils/hwstub/stub/rk27xx/convert_to_rkw.txt2
-rw-r--r--utils/hwstub/stub/rk27xx/crt0.S164
-rw-r--r--utils/hwstub/stub/rk27xx/hwstub.lds88
-rw-r--r--utils/hwstub/stub/rk27xx/rk27xx.h1158
-rw-r--r--utils/hwstub/stub/rk27xx/target-config.h9
-rw-r--r--utils/hwstub/stub/rk27xx/target.c172
-rw-r--r--utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c313
8 files changed, 1920 insertions, 0 deletions
diff --git a/utils/hwstub/stub/rk27xx/Makefile b/utils/hwstub/stub/rk27xx/Makefile
new file mode 100644
index 0000000000..937655327c
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/Makefile
@@ -0,0 +1,14 @@
1#
2# common
3#
4CC=arm-elf-eabi-gcc
5LD=arm-elf-eabi-gcc
6AS=arm-elf-eabi-gcc
7OC=arm-elf-eabi-objcopy
8DEFINES=
9INCLUDES=-I$(CURDIR)
10GCCOPTS=-march=armv5te
11BUILD_DIR=$(CURDIR)/build/
12ROOT_DIR=$(CURDIR)/..
13
14include ../hwstub.make
diff --git a/utils/hwstub/stub/rk27xx/convert_to_rkw.txt b/utils/hwstub/stub/rk27xx/convert_to_rkw.txt
new file mode 100644
index 0000000000..85d0d3cc71
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/convert_to_rkw.txt
@@ -0,0 +1,2 @@
1/home/wodz/rockbox-dev/bin/arm-elf-eabi-objcopy -O binary hwstub.elf hwstub.bin
2/home/wodz/rockbox/tools/scramble -rkw -modelnum=73 hwstub.bin hwstub.rkw
diff --git a/utils/hwstub/stub/rk27xx/crt0.S b/utils/hwstub/stub/rk27xx/crt0.S
new file mode 100644
index 0000000000..0c702eca91
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/crt0.S
@@ -0,0 +1,164 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 *
9 * Copyright (C) 2008 by Marcoen Hirschberg
10 * Copyright (C) 2008 by Denes Balatoni
11 * Copyright (C) 2010 by Marcin Bukat
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 *
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
20 *
21 ****************************************************************************/
22
23 .extern INT_UDC
24
25 .global start
26 .global entry_point
27
28 /* Exception vectors */
29 .section .intvect,"ax",%progbits
30 ldr pc, =start
31 ldr pc, =start
32 ldr pc, =start
33 ldr pc, =start
34 ldr pc, =start
35 ldr pc, =start
36 ldr pc, =irq_handler
37 ldr pc, =start
38 .ltorg
39
40 .section .text,"ax",%progbits
41start:
42 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
43
44 sub r4, pc, #12 /* copy running address, accomodate
45 * for prefetch (-8) and msr instr (-4)
46 */
47
48 ldr r0, =0xefff0000 /* cache controler base address */
49 ldrh r1, [r0]
50 strh r1, [r0] /* global cache disable */
51
52 ldr r2, =_relocstart
53 ldr r3, =_relocend
54
55 cmp r2, r4
56 beq entry_point /* skip copying if we are in place already */
571:
58 cmp r3, r2
59 ldrhi r1, [r4], #4
60 strhi r1, [r2], #4
61 bhi 1b
62
63entry_point_jmp:
64 ldr pc, =entry_point
65
66entry_point:
67 mov r0, #0x18000000
68 add r0, r0, #0x1c000
69
70 /* setup ARM core freq = 200MHz
71 * AHB bus freq (HCLK) = 100MHz
72 * APB bus freq (PCLK) = 50MHz
73 * Note: it seems there is no way to run AHB bus at ARM freq
74 * bit2 in DIVCON1 must have different meaning to what datasheet
75 * states. It influences SDRAM read speed but does not change
76 * APB freq
77 */
78 ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
79 bic r1, r1, #0x1f
80 orr r1, r1, #9 /* ((1<<3)|(1<<0)) ARM slow mode, HCLK:PCLK = 2:1 */
81 str r1, [r0,#0x14]
82
83 ldr r1,=0x1850310 /* ((1<<24)|(1<<23)|(5<<16)|(49<<4)) */
84 str r1, [r0,#0x08]
85
86 ldr r2,=0x40000
871:
88 ldr r1, [r0,#0x2c] /* SCU_STATUS */
89 tst r1, #1 /* ARM pll lock */
90 bne 1f
91 subs r2, r2, #1
92 bne 1b
931:
94 ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
95 bic r1, #1 /* leave ARM slow mode */
96 str r1, [r0,#0x14]
97
98 /* remap iram to 0x00000000 */
99 ldr r1,=0xdeadbeef
100 str r1, [r0, #4]
101
102 /* Copy interrupt vectors to iram */
103 ldr r2, =_intvectstart
104 ldr r3, =_intvectend
105 ldr r4, =_intvectcopy
1061:
107 cmp r3, r2
108 ldrhi r1, [r4], #4
109 strhi r1, [r2], #4
110 bhi 1b
111
112 /* Initialise bss section to zero */
113 ldr r2, =_edata
114 ldr r3, =_end
115 mov r4, #0
1161:
117 cmp r3, r2
118 strhi r4, [r2], #4
119 bhi 1b
120
121 /* Set up stack for IRQ mode */
122 msr cpsr_c, #0xd2
123 ldr sp, =_irqstackend
124
125 /* Set up stack for FIQ mode */
126 msr cpsr_c, #0xd1
127 ldr sp, =_fiqstackend
128
129 /* Let svc, abort and undefined modes use irq stack */
130 msr cpsr_c, #0xd3
131 ldr sp, =_irqstackend
132 msr cpsr_c, #0xd7
133 ldr sp, =_irqstackend
134 msr cpsr_c, #0xdb
135 ldr sp, =_irqstackend
136
137 /* Switch to sys mode */
138 msr cpsr_c, #0xdf
139
140 /* Set up some stack and munge it with 0xdeadbeef */
141 ldr sp, =stackend
142 ldr r2, =stackbegin
143 ldr r3, =0xdeadbeef
1441:
145 cmp sp, r2
146 strhi r3, [r2], #4
147 bhi 1b
148
149 /* Jump to C code */
150 b main
151
152/* copy from rockbox code - context save may be excessive but who cares */
153irq_handler:
154 stmfd sp!, {r0-r5, ip, lr} /* store context */
155 ldr r4, =0x18080000 /* INTC base */
156 ldr r5, [r4, #0x104] /* INTC_ISR */
157 and r5, r5, #0x1f /* irq_no = INTC_ISR & 0x1f */
158 cmp r5, #0x10 /* UDC irq */
159 bleq INT_UDC /* handle it */
160 mov r3, #1
161 lsl r5, r3, r5 /* clear interrupt */
162 str r5, [r4, #0x118] /* INTC_ICCR = (1<<irq_no) */
163 ldmfd sp!, {r0-r5, ip, lr} /* restore context */
164 subs pc, lr, #4
diff --git a/utils/hwstub/stub/rk27xx/hwstub.lds b/utils/hwstub/stub/rk27xx/hwstub.lds
new file mode 100644
index 0000000000..89b2b1961d
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/hwstub.lds
@@ -0,0 +1,88 @@
1ENTRY(start)
2OUTPUT_FORMAT(elf32-littlearm)
3OUTPUT_ARCH(arm)
4STARTUP(rk27xx/crt0.o)
5
6#define DRAMORIG 0x60000000
7#define DRAMSIZE (16 * 0x100000)
8#define DRAM_END_ADDRESS (DRAMORIG + DRAMSIZE)
9
10#define IRAMORIG 0x00000000
11#define IRAMSIZE 4K
12
13MEMORY
14{
15 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
16 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
17}
18
19SECTIONS
20{
21 .relocstart (NOLOAD) : {
22 _relocstart = .;
23 } > DRAM
24
25 .text : {
26 oc_codestart = .;
27 *(.init.text)
28 *(.text*)
29 *(.icode*)
30 *(.glue_7*)
31 } > DRAM
32
33 .intvect : {
34 _intvectstart = . ;
35 KEEP(*(.intvect))
36 _intvectend = . ;
37 } > IRAM AT > DRAM
38 _intvectcopy = LOADADDR(.intvect) ;
39
40 .rodata : {
41 *(.rodata*)
42 *(.irodata*)
43 . = ALIGN(0x4);
44 } > DRAM
45
46 .data : {
47 *(.data*)
48 *(.idata*)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .relocend (NOLOAD) : {
53 _relocend = .;
54 } > DRAM
55
56 .stack (NOLOAD) :
57 {
58 *(.stack)
59 oc_stackstart = .;
60 _stackbegin = .;
61 stackbegin = .;
62 . += 0x2000;
63 _stackend = .;
64 stackend = .;
65 _irqstackbegin = .;
66 . += 0x400;
67 _irqstackend = .;
68 _fiqstackbegin = .;
69 . += 0x400;
70 _fiqstackend = .;
71 oc_stackend = .;
72 } > DRAM
73
74 .bss (NOLOAD) : {
75 _edata = .;
76 *(.bss*);
77 *(.ibss);
78 *(COMMON);
79 . = ALIGN(0x4);
80 _end = .;
81 oc_codeend = .;
82 oc_bufferstart = .;
83 } > DRAM
84
85 .dramend DRAM_END_ADDRESS (NOLOAD) : {
86 oc_bufferend = .;
87 } > DRAM
88}
diff --git a/utils/hwstub/stub/rk27xx/rk27xx.h b/utils/hwstub/stub/rk27xx/rk27xx.h
new file mode 100644
index 0000000000..3c1c34529b
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/rk27xx.h
@@ -0,0 +1,1158 @@
1/* ARM part only for now */
2#define AHB_SRAM 0x00000000
3
4#define ARM_BUS0_BASE 0x18000000
5#define ARM_BUS1_BASE 0x18400000
6
7#define FLASH_BANK0 0x10000000
8#define FLASH_BANK1 0x11000000
9
10/* Timers */
11#define APB0_TIMER (ARM_BUS0_BASE + 0x00000000)
12#define TMR0LR (*(volatile unsigned long *)(APB0_TIMER + 0x00))
13#define TMR0CVR (*(volatile unsigned long *)(APB0_TIMER + 0x04))
14#define TMR0CON (*(volatile unsigned long *)(APB0_TIMER + 0x08))
15
16#define TMR1LR (*(volatile unsigned long *)(APB0_TIMER + 0x10))
17#define TMR1CVR (*(volatile unsigned long *)(APB0_TIMER + 0x14))
18#define TMR1CON (*(volatile unsigned long *)(APB0_TIMER + 0x18))
19
20#define TMR2LR (*(volatile unsigned long *)(APB0_TIMER + 0x20))
21#define TMR2CVR (*(volatile unsigned long *)(APB0_TIMER + 0x24))
22#define TMR2CON (*(volatile unsigned long *)(APB0_TIMER + 0x28))
23
24/* UART0 */
25#define APB0_UART0 (ARM_BUS0_BASE + 0x00004000)
26#define UART0_RBR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
27#define UART0_THR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
28#define UART0_DLL (*(volatile unsigned long *)(APB0_UART0 + 0x00))
29#define UART0_DLH (*(volatile unsigned long *)(APB0_UART0 + 0x04))
30#define UART0_IER (*(volatile unsigned long *)(APB0_UART0 + 0x04))
31#define UART0_IIR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
32#define UART0_FCR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
33#define UART0_LCR (*(volatile unsigned long *)(APB0_UART0 + 0x0C))
34#define UART0_MCR (*(volatile unsigned long *)(APB0_UART0 + 0x10))
35#define UART0_LSR (*(volatile unsigned long *)(APB0_UART0 + 0x14))
36#define UART0_MSR (*(volatile unsigned long *)(APB0_UART0 + 0x18))
37
38/* UART1 */
39#define APB0_UART1 (ARM_BUS0_BASE + 0x00008000)
40#define UART1_RBR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
41#define UART1_THR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
42#define UART1_DLL (*(volatile unsigned long *)(APB0_UART1 + 0x00))
43#define UART1_DLH (*(volatile unsigned long *)(APB0_UART1 + 0x04))
44#define UART1_IER (*(volatile unsigned long *)(APB0_UART1 + 0x04))
45#define UART1_IIR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
46#define UART1_FCR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
47#define UART1_LCR (*(volatile unsigned long *)(APB0_UART1 + 0x0C))
48#define UART1_MCR (*(volatile unsigned long *)(APB0_UART1 + 0x10))
49#define UART1_LSR (*(volatile unsigned long *)(APB0_UART1 + 0x14))
50#define UART1_MSR (*(volatile unsigned long *)(APB0_UART1 + 0x18))
51
52/* GPIO ports A,B,C,D */
53#define APB0_GPIO0 (ARM_BUS0_BASE + 0x0000C000)
54#define GPIO_PADR (*(volatile unsigned long *)(APB0_GPIO0 + 0x00))
55#define GPIO_PACON (*(volatile unsigned long *)(APB0_GPIO0 + 0x04))
56#define GPIO_PBDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x08))
57#define GPIO_PBCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x0C))
58#define GPIO_PCDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x10))
59#define GPIO_PCCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x14))
60#define GPIO_PDDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x18))
61#define GPIO_PDCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x1C))
62#define GPIO_TEST (*(volatile unsigned long *)(APB0_GPIO0 + 0x20))
63#define GPIO_IEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x24))
64#define GPIO_IEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x28))
65#define GPIO_IEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x2C))
66#define GPIO_IED (*(volatile unsigned long *)(APB0_GPIO0 + 0x30))
67#define GPIO_ISA (*(volatile unsigned long *)(APB0_GPIO0 + 0x34))
68#define GPIO_ISB (*(volatile unsigned long *)(APB0_GPIO0 + 0x38))
69#define GPIO_ISC (*(volatile unsigned long *)(APB0_GPIO0 + 0x3C))
70#define GPIO_ISD (*(volatile unsigned long *)(APB0_GPIO0 + 0x40))
71#define GPIO_IBEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x44))
72#define GPIO_IBEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x48))
73#define GPIO_IBEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x4C))
74#define GPIO_IBED (*(volatile unsigned long *)(APB0_GPIO0 + 0x50))
75#define GPIO_IEVA (*(volatile unsigned long *)(APB0_GPIO0 + 0x54))
76#define GPIO_IEVB (*(volatile unsigned long *)(APB0_GPIO0 + 0x58))
77#define GPIO_IEVC (*(volatile unsigned long *)(APB0_GPIO0 + 0x5C))
78#define GPIO_IEVD (*(volatile unsigned long *)(APB0_GPIO0 + 0x60))
79#define GPIO_ICA (*(volatile unsigned long *)(APB0_GPIO0 + 0x64))
80#define GPIO_ICB (*(volatile unsigned long *)(APB0_GPIO0 + 0x68))
81#define GPIO_ICC (*(volatile unsigned long *)(APB0_GPIO0 + 0x6C))
82#define GPIO_ICD (*(volatile unsigned long *)(APB0_GPIO0 + 0x70))
83#define GPIO_ISR (*(volatile unsigned long *)(APB0_GPIO0 + 0x74))
84
85/* Watchdog */
86#define APB0_WDT (ARM_BUS0_BASE + 0x00010000)
87#define WDTLR (*(volatile unsigned long *)(APB0_WDT + 0x00))
88#define WDTCVR (*(volatile unsigned long *)(APB0_WDT + 0x04))
89#define WDTCON (*(volatile unsigned long *)(APB0_WDT + 0x08))
90
91/* RTC module documentation missing */
92#define APB0_RTC (ARM_BUS0_BASE + 0x00014000)
93#define RTC_TIME (*(volatile unsigned long *)(APB0_RTC + 0x00))
94#define RTC_DATE (*(volatile unsigned long *)(APB0_RTC + 0x04))
95#define RTC_TALARM (*(volatile unsigned long *)(APB0_RTC + 0x08))
96#define RTC_DALARM (*(volatile unsigned long *)(APB0_RTC + 0x0C))
97#define RTC_CTRL (*(volatile unsigned long *)(APB0_RTC + 0x10))
98#define RTC_RESET (*(volatile unsigned long *)(APB0_RTC + 0x14))
99#define RTC_PWOFF (*(volatile unsigned long *)(APB0_RTC + 0x18))
100#define RTC_PWFAIL (*(volatile unsigned long *)(APB0_RTC + 0x1C))
101
102/* SPI */
103#define APB0_SPI (ARM_BUS0_BASE + 0x00018000)
104#define SPI_TXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
105#define SPI_RXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
106#define SPI_IER (*(volatile unsigned long *)(APB0_SPI + 0x04))
107#define SPI_FCR (*(volatile unsigned long *)(APB0_SPI + 0x08))
108#define SPI_FWCR (*(volatile unsigned long *)(APB0_SPI + 0x0C))
109#define SPI_DLYCR (*(volatile unsigned long *)(APB0_SPI + 0x10))
110#define SPI_TXCR (*(volatile unsigned long *)(APB0_SPI + 0x14))
111#define SPI_RXCR (*(volatile unsigned long *)(APB0_SPI + 0x18))
112#define SPI_SSCR (*(volatile unsigned long *)(APB0_SPI + 0x1C))
113#define SPI_ISR (*(volatile unsigned long *)(APB0_SPI + 0x20))
114
115/* SCU module */
116#define APB0_SCU (ARM_BUS0_BASE + 0x0001C000)
117#define SCU_ID (*(volatile unsigned long *)(APB0_SCU + 0x00))
118#define SCU_REMAP (*(volatile unsigned long *)(APB0_SCU + 0x04))
119#define SCU_PLLCON1 (*(volatile unsigned long *)(APB0_SCU + 0x08))
120#define SCU_PLLCON2 (*(volatile unsigned long *)(APB0_SCU + 0x0C))
121#define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10))
122#define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14))
123#define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18))
124#define CLKCFG_OTP (1<<0)
125#define CLKCFG_DSP (1<<1)
126#define CLKCFG_SDRAM (1<<2)
127#define CLKCFG_HDMA (1<<3)
128#define CLKCFG_DWDMA (1<<4)
129#define CLKCFG_UHC (1<<5)
130#define CLKCFG_UDC (1<<6)
131/* 7 - 8 reserved */
132#define CLKCFG_NAND (1<<9)
133#define CLKCFG_A2A (1<<10)
134#define CLKCFG_SRAM (1<<11)
135#define CLKCFG_HCLK_LCDC (1<<12)
136#define CLKCFG_LCDC (1<<13)
137#define CLKCFG_HCLK_VIP (1<<14)
138#define CLKCFG_VIP (1<<15)
139#define CLKCFG_I2S (1<<16)
140#define CLKCFG_PCLK_I2S (1<<17)
141#define CLKCFG_UART0 (1<<18)
142#define CLKCFG_UART1 (1<<19)
143#define CLKCFG_I2C (1<<20)
144#define CLKCFG_SPI (1<<21)
145#define CLKCFG_SD (1<<22)
146#define CLKCFG_PCLK_LSADC (1<<23)
147#define CLKCFG_LSADC (1<<24)
148#define CLKCFG_HCLK_HSADC (1<<25)
149#define CLKCFG_HSADC (1<<26)
150#define CLKCFG_GPIO (1<<27)
151#define CLKCFG_TIMER (1<<28)
152#define CLKCFG_PWM (1<<29)
153#define CLKCFG_RTC (1<<30)
154#define CLKCFG_WDT (1<<31)
155
156#define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C))
157#define RSTCFG_UHC (1<<0)
158#define RSTCFG_UDC (1<<1)
159#define RSTCFG_LCDC (1<<2)
160#define RSTCFG_VIP (1<<3)
161#define RSTCFG_DSP_CORE (1<<4)
162#define RSTCFG_DSP_PERI (1<<5)
163#define RSTCFG_CODEC (1<<6)
164#define RSTCFG_LSADC (1<<7)
165#define RSTCFG_HSADC (1<<8)
166#define RSTCFG_SD (1<<9)
167#define RSTCFG_MAILBOX (1<<10)
168#define RSTCFG_ECT (1<<11)
169#define RSTCFG_ARM_CORE (1<<12)
170/* 13 - 31 reserved */
171
172#define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20))
173#define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24))
174#define SCU_CHIPCFG (*(volatile unsigned long *)(APB0_SCU + 0x28))
175#define SCU_STATUS (*(volatile unsigned long *)(APB0_SCU + 0x2C))
176#define SCU_IOMUXA_CON (*(volatile unsigned long *)(APB0_SCU + 0x30))
177/* 20 - 31 reserved */
178#define IOMUX_I2S_PAD (1<<19)
179#define IOMUX_I2S_CODEC (0<<19)
180#define IOMUX_I2C_PAD (1<<18)
181#define IOMUX_I2C_CODEC (0<<18)
182#define IOMUX_GPIO_B7 (2<<16)
183#define IOMUX_NAND_CS3 (1<<16)
184#define IOMUX_I2C_SDA (0<<16)
185#define IOMUX_GPIO_B6 (2<<14)
186#define IOMUX_NAND_CS2 (1<<14)
187#define IOMUX_I2C_SCL (0<<14)
188#define IOMUX_SPI (2<<12)
189#define IOMUX_SD (1<<12)
190#define IOMUX_GPIO_B05 (0<<12)
191#define IOMUX_LCD_VSYNC (1<<11)
192#define IOMUX_GPIO_A7 (0<<11)
193#define IOMUX_LCD_DEN (1<<10)
194#define IOMUX_GPIO_A6 (0<<10)
195#define IOMUX_NAND_CS1 (1<<9)
196#define IOMUX_GPIO_A5 (0<<9)
197#define IOMUX_LCD_D22 (1<<8)
198#define IOMUX_GPIO_A4 (0<<8)
199#define IOMUX_UART0_NRTS (2<<6)
200#define IOMUX_LCD_D20 (1<<6)
201#define IOMUX_GPIO_A3 (0<<6)
202#define IOMUX_UART0_NCTS (2<<4)
203#define IOMUX_LCD_D18 (1<<4)
204#define IOMUX_GPIO_A2 (0<<4)
205#define IOMUX_UART0_TXD (2<<2)
206#define IOMUX_LCD_D17 (1<<2)
207#define IOMUX_GPIO_A1 (0<<2)
208#define IOMUX_UART0_RXD (2<<0)
209#define IOMUX_LCD_D16 (1<<0)
210#define IOMUX_GPIO_A0 (0<<0)
211
212#define SCU_IOMUXB_CON (*(volatile unsigned long *)(APB0_SCU + 0x34))
213/* bits 31 - 23 reserved */
214#define IOMUX_HADC (1<<22)
215#define IOMUX_VIP (0<<22)
216#define IOMUX_SDRAM_CKE (1<<21)
217#define IOMUX_GPIO_D3 (0<<21)
218#define IOMUX_UHC_VBUS (1<<20)
219#define IOMUX_GPIO_F4 (0<<20)
220#define IOMUX_UHC_OCUR (1<<19)
221#define IOMUX_GPIO_F3 (0<<19)
222#define IOMUX_GPIO_F2 (1<<18)
223#define IOMUX_SDRAM_A12 (0<<18)
224#define IOMUX_GPIO_F1 (1<<17)
225#define IOMUX_SDRAM_A11 (0<<17)
226#define IOMUX_VIP_CLK (1<<16)
227#define IOMUX_GPIO_F0 (0<<16)
228#define IOMUX_LCD_D815 (1<<15)
229#define IOMUX_GPIO_E07 (0<<15)
230#define IOMUX_PWM3 (1<<14)
231#define IOMUX_GPIO_D7 (0<<14)
232#define IOMUX_PWM2 (1<<13)
233#define IOMUX_GPIO_D6 (0<<13)
234#define IOMUX_PWM1 (1<<12)
235#define IOMUX_GPIO_D5 (0<<12)
236#define IOMUX_PWM0 (1<<11)
237#define IOMUX_GPIO_D4 (0<<11)
238#define IOMUX_SD_WPA (1<<10)
239#define IOMUX_GPIO_D2 (0<<10)
240#define IOMUX_UART1_RXD (2<<8)
241#define IOMUX_SD_CDA (1<<8)
242#define IOMUX_GPIO_D1 (0<<8)
243#define IOMUX_UART1_TXD (2<<6)
244#define IOMUX_SD_PCA (1<<6)
245#define IOMUX_GPIO_D0 (0<<6)
246#define IOMUX_STMEM_CS1 (1<<5)
247#define IOMUX_GPIO_C7 (0<<5)
248#define IOMUX_I2S_CLK (1<<4)
249#define IOMUX_GPIO_C6 (0<<4)
250#define IOMUX_I2S_SDO (1<<3)
251#define IOMUX_GPIO_C5 (0<<3)
252#define IOMUX_I2S_SDI (1<<2)
253#define IOMUX_GPIO_C4 (0<<2)
254#define IOMUX_I2S_LRCK (1<<1)
255#define IOMUX_GPIO_C3 (0<<1)
256#define IOMUX_I2S_SCLK (1<<0)
257#define IOMUX_GPIO_C2 (0<<0)
258
259#define SCU_GPIOUPCON (*(volatile unsigned long *)(APB0_SCU + 0x38))
260#define SCU_DIVCON2 (*(volatile unsigned long *)(APB0_SCU + 0x3C))
261
262/* I2C controller */
263#define APB0_I2C (ARM_BUS0_BASE + 0x00020000)
264#define I2C_MTXR (*(volatile unsigned long *)(APB0_I2C + 0x00))
265#define I2C_MRXR (*(volatile unsigned long *)(APB0_I2C + 0x04))
266#define I2C_STXR (*(volatile unsigned long *)(APB0_I2C + 0x08))
267#define I2C_SRXR (*(volatile unsigned long *)(APB0_I2C + 0x0C))
268#define I2C_SADDR (*(volatile unsigned long *)(APB0_I2C + 0x10))
269#define I2C_IER (*(volatile unsigned long *)(APB0_I2C + 0x14))
270#define I2C_ISR (*(volatile unsigned long *)(APB0_I2C + 0x18))
271#define I2C_LCMR (*(volatile unsigned long *)(APB0_I2C + 0x1C))
272#define I2C_LSR (*(volatile unsigned long *)(APB0_I2C + 0x20))
273#define I2C_CONR (*(volatile unsigned long *)(APB0_I2C + 0x24))
274#define I2C_OPR (*(volatile unsigned long *)(APB0_I2C + 0x28))
275
276/* SD card controller */
277#define APB0_SD (ARM_BUS0_BASE + 0x00024000)
278#define MMU_CTRL (*(volatile unsigned long *)(APB0_SD + 0x00))
279#define MMU_BIG_ENDIAN (1<<12)
280#define MMU_DMA_START (1<<11)
281#define MMU_DMA_WRITE (1<<10)
282#define MMU_MMU0_BUFI (0<<9)
283#define MMU_MMU0_BUFII (1<<9)
284#define MMU_CPU_BUFI (0<<8)
285#define MMU_CPU_BUFII (1<<8)
286#define MMU_BUFII_RESET (1<<7)
287#define MMU_BUFII_END (1<<6)
288#define MMU_BUFII_BYTE (0<<4)
289#define MMU_BUFII_HALFWORD (1<<4)
290#define MMU_BUFII_WORD (3<<4)
291#define MMU_BUFI_RESET (1<<3)
292#define MMU_BUFI_END (1<<2)
293#define MMU_BUFI_BYTE (0<<0)
294#define MMU_BUFI_HALFWORD (1<<0)
295#define MMU_BUFI_WORD (3<<0)
296
297#define MMU_PNRI (*(volatile unsigned long *)(APB0_SD + 0x04))
298#define CUR_PNRI (*(volatile unsigned long *)(APB0_SD + 0x08))
299#define MMU_PNRII (*(volatile unsigned long *)(APB0_SD + 0x0C))
300#define CUR_PNRII (*(volatile unsigned long *)(APB0_SD + 0x10))
301#define MMU_ADDR (*(volatile unsigned long *)(APB0_SD + 0x14))
302#define CUR_ADDR (*(volatile unsigned long *)(APB0_SD + 0x18))
303#define MMU_DATA (*(volatile unsigned long *)(APB0_SD + 0x1C))
304
305#define SD_CTRL (*(volatile unsigned long *)(APB0_SD + 0x20))
306#define SD_PWR_CD (1<<13)
307#define SD_PWR_CPU (0<<13)
308#define SD_DETECT_CDDAT3 (1<<12)
309#define SD_DETECT_MECH (0<<12)
310#define SD_CLOCK_DIS (1<<11)
311#define SD_CLOCK_EN (0<<11)
312#define SD_DIV(x) ((x)&0x7ff)
313
314#define SD_INT (*(volatile unsigned long *)(APB0_SD + 0x24))
315#define CMD_RES_STAT (1<<6)
316#define DATA_XFER_STAT (1<<5)
317#define CD_DETECT_STAT (1<<4)
318#define CMD_RES_INT_EN (1<<2)
319#define DATA_XFER_INT_EN (1<<1)
320#define CD_DETECT_IN_EN (1<<0)
321
322#define SD_CARD (*(volatile unsigned long *)(APB0_SD + 0x28))
323#define SD_CARD_SELECT (1<<7)
324#define SD_CARD_PWR_EN (1<<6)
325#define SD_CARD_DETECT_INT_EN (1<<5)
326#define SD_CARD_BSY (1<<2)
327#define SD_CARD_WRITE_PROTECT (1<<1)
328#define SD_CARD_DETECT (1<<0)
329
330#define SD_CMDREST (*(volatile unsigned long *)(APB0_SD + 0x30))
331#define CMD_XFER_START (1<<13)
332#define CMD_XFER_END (0<<13)
333#define RES_XFER_START (1<<12)
334#define RES_XFER_END (0<<12)
335#define RES_R1 (0<<9)
336#define RES_R1b (1<<9)
337#define RES_R2 (2<<9)
338#define RES_R3 (3<<9)
339#define RES_R6 (6<<9)
340#define CMD_RES_ERROR (1<<8)
341/* bits 0-5 cmd index */
342
343#define SD_CMDRES (*(volatile unsigned long *)(APB0_SD + 0x34))
344#define STAT_CMD_XFER_START (1<<8)
345#define STAT_RES_XFER_START (1<<7)
346#define STAT_CMD_RES_ERR (1<<6)
347#define STAT_CMD_RES_BUS_ERR (1<<5)
348#define STAT_RES_TIMEOUT_ERR (1<<4)
349#define STAT_RES_STARTBIT_ERR (1<<3)
350#define STAT_RES_INDEX_ERR (1<<2)
351#define STAT_RES_CRC_ERR (1<<1)
352#define STAT_RES_ENDBIT_ERR (1<<0)
353
354#define SD_DATAT (*(volatile unsigned long *)(APB0_SD + 0x3C))
355#define DATA_XFER_START (1<<13)
356#define DATA_XFER_WRITE (1<<12)
357#define DATA_XFER_READ (0<<12)
358#define DATA_BUS_4LINES (1<<11) /* rk2705/6/8 does not support this mode */
359#define DATA_BUS_1LINE (0<<11)
360#define DATA_XFER_DMA_EN (1<<10)
361#define DATA_XFER_DMA_DIS (0<<10)
362#define DATA_XFER_MULTI (1<<9)
363#define DATA_XFER_SINGLE (0<<9)
364#define DATA_XFER_ERR (1<<8)
365#define DATA_BUS_ERR (1<<7)
366#define DATA_TIMEOUT_ERR (1<<6)
367#define DATA_CRC_ERR (1<<5)
368#define READ_DAT_STARTBIT_ERR (1<<4)
369#define READ_DAT_ENDBIT_ERR (1<<3)
370#define WRITE_DAT_NOERR (2<<0)
371#define WRITE_DAT_CRC_ERR (5<<0)
372#define WRITE_DAT_NO_RES (7<<0)
373
374#define SD_CMD (*(volatile unsigned long *)(APB0_SD + 0x40))
375#define SD_RES3 (*(volatile unsigned long *)(APB0_SD + 0x44))
376#define SD_RES2 (*(volatile unsigned long *)(APB0_SD + 0x48))
377#define SD_RES1 (*(volatile unsigned long *)(APB0_SD + 0x4C))
378#define SD_RES0 (*(volatile unsigned long *)(APB0_SD + 0x50))
379
380/* I2S controller */
381#define APB0_I2S (ARM_BUS0_BASE + 0x00028000)
382#define I2S_OPR (*(volatile unsigned long *)(APB0_I2S + 0x00))
383#define I2S_TXR (*(volatile unsigned long *)(APB0_I2S + 0x04))
384#define I2S_RXR (*(volatile unsigned long *)(APB0_I2S + 0x08))
385#define I2S_TXCTL (*(volatile unsigned long *)(APB0_I2S + 0x0C))
386#define I2S_RXCTL (*(volatile unsigned long *)(APB0_I2S + 0x10))
387#define I2S_FIFOSTS (*(volatile unsigned long *)(APB0_I2S + 0x14))
388#define I2S_IER (*(volatile unsigned long *)(APB0_I2S + 0x18))
389#define I2S_ISR (*(volatile unsigned long *)(APB0_I2S + 0x1C))
390
391/* PWM timer */
392#define APB0_PWM (ARM_BUS0_BASE + 0x0002C000)
393#define PWMT0_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x00))
394#define PWMT0_HRC (*(volatile unsigned long *)(APB0_PWM + 0x04))
395#define PWMT0_LRC (*(volatile unsigned long *)(APB0_PWM + 0x08))
396#define PWMT0_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x0C))
397#define PWMT1_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x10))
398#define PWMT1_HRC (*(volatile unsigned long *)(APB0_PWM + 0x14))
399#define PWMT1_LRC (*(volatile unsigned long *)(APB0_PWM + 0x18))
400#define PWMT1_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x1C))
401#define PWMT2_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x20))
402#define PWMT2_HRC (*(volatile unsigned long *)(APB0_PWM + 0x24))
403#define PWMT2_LRC (*(volatile unsigned long *)(APB0_PWM + 0x28))
404#define PWMT2_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x2C))
405#define PWMT3_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x30))
406#define PWMT3_HRC (*(volatile unsigned long *)(APB0_PWM + 0x34))
407#define PWMT3_LRC (*(volatile unsigned long *)(APB0_PWM + 0x38))
408#define PWMT3_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x3C))
409
410/* ADC converter */
411#define APB0_ADC0 (ARM_BUS0_BASE + 0x00030000)
412#define ADC_DATA (*(volatile unsigned long *)(APB0_ADC0 + 0x00))
413#define ADC_STAT (*(volatile unsigned long *)(APB0_ADC0 + 0x04))
414#define ADC_CTRL (*(volatile unsigned long *)(APB0_ADC0 + 0x08))
415
416/* 0x18034000 - 0x18038000 reserved */
417
418/* GPIO ports E,F */
419#define APB0_GPIO1 (ARM_BUS0_BASE + 0x00038000)
420#define GPIO_PEDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x00))
421#define GPIO_PECON (*(volatile unsigned long *)(APB0_GPIO1 + 0x04))
422#define GPIO_PFDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x08))
423#define GPIO_PFCON (*(volatile unsigned long *)(APB0_GPIO1 + 0x0C))
424
425#define GPIO1_TEST (*(volatile unsigned long *)(APB0_GPIO1 + 0x20))
426#define GPIO_IEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x24))
427#define GPIO_IEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x28))
428
429#define GPIO_ISE (*(volatile unsigned long *)(APB0_GPIO1 + 0x34))
430#define GPIO_ISF (*(volatile unsigned long *)(APB0_GPIO1 + 0x38))
431
432#define GPIO_IBEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x44))
433#define GPIO_IBEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x48))
434
435#define GPIO_IEVE (*(volatile unsigned long *)(APB0_GPIO1 + 0x54))
436#define GPIO_IEVF (*(volatile unsigned long *)(APB0_GPIO1 + 0x58))
437
438#define GPIO_ICE (*(volatile unsigned long *)(APB0_GPIO1 + 0x64))
439#define GPIO_ICF (*(volatile unsigned long *)(APB0_GPIO1 + 0x68))
440
441#define GPIO1_ISR (*(volatile unsigned long *)(APB0_GPIO1 + 0x74))
442
443
444/* 0x1803C000 - 0x18080000 reserved */
445
446/* Interrupt controller */
447#define AHB0_INTC (ARM_BUS0_BASE + 0x00080000)
448#define INTC_SCR0 (*(volatile unsigned long *)(AHB0_INTC + 0x00))
449#define INTC_SCR1 (*(volatile unsigned long *)(AHB0_INTC + 0x04))
450#define INTC_SCR2 (*(volatile unsigned long *)(AHB0_INTC + 0x08))
451#define INTC_SCR3 (*(volatile unsigned long *)(AHB0_INTC + 0x0C))
452#define INTC_SCR4 (*(volatile unsigned long *)(AHB0_INTC + 0x10))
453#define INTC_SCR5 (*(volatile unsigned long *)(AHB0_INTC + 0x14))
454#define INTC_SCR6 (*(volatile unsigned long *)(AHB0_INTC + 0x18))
455#define INTC_SCR7 (*(volatile unsigned long *)(AHB0_INTC + 0x1C))
456#define INTC_SCR8 (*(volatile unsigned long *)(AHB0_INTC + 0x20))
457#define INTC_SCR9 (*(volatile unsigned long *)(AHB0_INTC + 0x24))
458#define INTC_SCR10 (*(volatile unsigned long *)(AHB0_INTC + 0x28))
459#define INTC_SCR11 (*(volatile unsigned long *)(AHB0_INTC + 0x2C))
460#define INTC_SCR12 (*(volatile unsigned long *)(AHB0_INTC + 0x30))
461#define INTC_SCR13 (*(volatile unsigned long *)(AHB0_INTC + 0x34))
462#define INTC_SCR14 (*(volatile unsigned long *)(AHB0_INTC + 0x38))
463#define INTC_SCR15 (*(volatile unsigned long *)(AHB0_INTC + 0x3C))
464#define INTC_SCR16 (*(volatile unsigned long *)(AHB0_INTC + 0x40))
465#define INTC_SCR17 (*(volatile unsigned long *)(AHB0_INTC + 0x44))
466#define INTC_SCR18 (*(volatile unsigned long *)(AHB0_INTC + 0x48))
467#define INTC_SCR19 (*(volatile unsigned long *)(AHB0_INTC + 0x4C))
468#define INTC_SCR20 (*(volatile unsigned long *)(AHB0_INTC + 0x50))
469#define INTC_SCR21 (*(volatile unsigned long *)(AHB0_INTC + 0x54))
470#define INTC_SCR22 (*(volatile unsigned long *)(AHB0_INTC + 0x58))
471#define INTC_SCR23 (*(volatile unsigned long *)(AHB0_INTC + 0x5C))
472#define INTC_SCR24 (*(volatile unsigned long *)(AHB0_INTC + 0x60))
473#define INTC_SCR25 (*(volatile unsigned long *)(AHB0_INTC + 0x64))
474#define INTC_SCR26 (*(volatile unsigned long *)(AHB0_INTC + 0x68))
475#define INTC_SCR27 (*(volatile unsigned long *)(AHB0_INTC + 0x6C))
476#define INTC_SCR28 (*(volatile unsigned long *)(AHB0_INTC + 0x70))
477#define INTC_SCR29 (*(volatile unsigned long *)(AHB0_INTC + 0x74))
478#define INTC_SCR30 (*(volatile unsigned long *)(AHB0_INTC + 0x78))
479#define INTC_SCR31 (*(volatile unsigned long *)(AHB0_INTC + 0x7C))
480
481#define INTC_ISR (*(volatile unsigned long *)(AHB0_INTC + 0x104))
482#define INTC_IPR (*(volatile unsigned long *)(AHB0_INTC + 0x108))
483#define INTC_IMR (*(volatile unsigned long *)(AHB0_INTC + 0x10C))
484
485#define INTC_IECR (*(volatile unsigned long *)(AHB0_INTC + 0x114))
486#define INTC_ICCR (*(volatile unsigned long *)(AHB0_INTC + 0x118))
487#define INTC_ISCR (*(volatile unsigned long *)(AHB0_INTC + 0x11C))
488
489#define IRQ_ARM_UART0 (1<<0)
490#define IRQ_ARM_UART1 (1<<1)
491#define IRQ_ARM_TIMER0 (1<<2)
492#define IRQ_ARM_TIMER1 (1<<3)
493#define IRQ_ARM_TIMER2 (1<<4)
494#define IRQ_ARM_GPIO0 (1<<5)
495#define IRQ_ARM_SW (1<<6)
496#define IRQ_ARM_MAILBOX (1<<7)
497#define IRQ_ARM_RTC (1<<8)
498#define IRQ_ARM_SCU (1<<9)
499#define IRQ_ARM_SD (1<<10)
500#define IRQ_ARM_SPI (1<<11)
501#define IRQ_ARM_HDMA (1<<12)
502#define IRQ_ARM_A2A (1<<13)
503#define IRQ_ARM_I2C (1<<14)
504#define IRQ_ARM_I2S (1<<15)
505#define IRQ_ARM_UDC (1<<16)
506#define IRQ_ARM_UHC (1<<17)
507#define IRQ_ARM_PWM0 (1<<18)
508#define IRQ_ARM_PWM1 (1<<19)
509#define IRQ_ARM_PWM2 (1<<20)
510#define IRQ_ARM_PWM3 (1<<21)
511#define IRQ_ARM_ADC (1<<22)
512#define IRQ_ARM_GPIO1 (1<<23)
513#define IRQ_ARM_VIP (1<<24)
514#define IRQ_ARM_DWDMA (1<<25)
515#define IRQ_ARM_NANDC (1<<26)
516#define IRQ_ARM_LCDC (1<<27)
517#define IRQ_ARM_DSP (1<<28)
518#define IRQ_ARM_SW1 (1<<29)
519#define IRQ_ARM_SW2 (1<<30)
520#define IRQ_ARM_SW3 (1<<31)
521
522#define INTC_TEST (*(volatile unsigned long *)(AHB0_INTC + 0x124))
523
524/* Bus arbiter module */
525#define AHB0_ARBITER (ARM_BUS0_BASE + 0x00084000)
526#define ARB_MODE (*(volatile unsigned long *)(AHB0_ARBITER + 0x00))
527#define ARB_PRIO1 (*(volatile unsigned long *)(AHB0_ARBITER + 0x04))
528#define ARB_PRIO2 (*(volatile unsigned long *)(AHB0_ARBITER + 0x08))
529#define ARB_PRIO3 (*(volatile unsigned long *)(AHB0_ARBITER + 0x0C))
530#define ARB_PRIO4 (*(volatile unsigned long *)(AHB0_ARBITER + 0x10))
531#define ARB_PRIO5 (*(volatile unsigned long *)(AHB0_ARBITER + 0x14))
532#define ARB_PRIO6 (*(volatile unsigned long *)(AHB0_ARBITER + 0x18))
533#define ARB_PRIO7 (*(volatile unsigned long *)(AHB0_ARBITER + 0x1C))
534#define ARB_PRIO8 (*(volatile unsigned long *)(AHB0_ARBITER + 0x20))
535#define ARB_PRIO9 (*(volatile unsigned long *)(AHB0_ARBITER + 0x24))
536#define ARB_PRIO10 (*(volatile unsigned long *)(AHB0_ARBITER + 0x28))
537#define ARB_PRIO11 (*(volatile unsigned long *)(AHB0_ARBITER + 0x2C))
538#define ARB_PRIO12 (*(volatile unsigned long *)(AHB0_ARBITER + 0x30))
539#define ARB_PRIO13 (*(volatile unsigned long *)(AHB0_ARBITER + 0x34))
540#define ARB_PRIO14 (*(volatile unsigned long *)(AHB0_ARBITER + 0x38))
541#define ARB_PRIO15 (*(volatile unsigned long *)(AHB0_ARBITER + 0x3C))
542
543/* Interprocessor communication module */
544#define AHB0_CPU_MAILBOX (ARM_BUS0_BASE + 0x00088000)
545#define MAILBOX_ID (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x00))
546#define H2C_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x10))
547#define H2C0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x20))
548#define H2C0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
549#define H2C1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x28))
550#define H2C1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x2C))
551#define H2C2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x30))
552#define H2C2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
553#define H2C3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x38))
554#define H2C3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x3C))
555
556#define C2H_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x40))
557#define C2H0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x50))
558#define C2H0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x54))
559#define C2H1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x58))
560#define C2H1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x5C))
561#define C2H2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x60))
562#define C2H2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x64))
563#define C2H3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x68))
564#define C2H3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x6C))
565
566/* Debug module */
567#define AHB0_CPU_DEBUGIF (ARM_BUS0_BASE + 0x0008C000)
568
569/* AHB DMA */
570#define AHB0_HDMA (ARM_BUS0_BASE + 0x00090000)
571#define HDMA_CON0 (*(volatile unsigned long *)(AHB0_HDMA + 0x00))
572#define HDMA_CON1 (*(volatile unsigned long *)(AHB0_HDMA + 0x04))
573#define HDMA_ISRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x08))
574#define HDMA_IDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x0C))
575#define HDMA_ICNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x10))
576#define HDMA_ISRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x14))
577#define HDMA_IDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x18))
578#define HDMA_ICNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x1C))
579#define HDMA_CSRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x20))
580#define HDMA_CDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x24))
581#define HDMA_CCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x28))
582#define HDMA_CSRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x2C))
583#define HDMA_CDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x30))
584#define HDMA_CCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x34))
585#define HDMA_ISR (*(volatile unsigned long *)(AHB0_HDMA + 0x38))
586#define HDMA_DSR (*(volatile unsigned long *)(AHB0_HDMA + 0x3C))
587#define HDMA_ISCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x40))
588#define HDMA_IPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x44))
589#define HDMA_IADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x48))
590#define HDMA_ISCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x4C))
591#define HDMA_IPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x50))
592#define HDMA_IADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x54))
593#define HDMA_CSCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x58))
594#define HDMA_CPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x5C))
595#define HDMA_CADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x60))
596#define HDMA_CSCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x64))
597#define HDMA_CPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x68))
598#define HDMA_CADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x6C))
599#define HDMA_PACNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x70))
600#define HDMA_PACNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x74))
601
602/* AHB-to-AHB bridge controller */
603#define AHB0_A2A_DMA (ARM_BUS0_BASE + 0x00094000)
604#define A2A_CON0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x00))
605#define A2A_ISRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x04))
606#define A2A_IDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x08))
607#define A2A_ICNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x0C))
608#define A2A_CSRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x10))
609#define A2A_CDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x14))
610#define A2A_CCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x18))
611#define A2A_CON1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x1C))
612#define A2A_ISRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x20))
613#define A2A_IDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x24))
614#define A2A_ICNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x28))
615#define A2A_CSRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x2C))
616#define A2A_CDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x30))
617#define A2A_CCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x34))
618#define A2A_INT_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x38))
619#define A2A_DMA_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x3C))
620#define A2A_ERR_ADR0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x40))
621#define A2A_ERR_OP0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x44))
622#define A2A_ERR_ADR1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x48))
623#define A2A_ERR_OP1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x4C))
624#define A2A_LCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x50))
625#define A2A_LCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x54))
626#define A2A_DOMAIN (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x58))
627
628/* 0x18098000 - 0x180A000 reserved */
629
630/* USB device controller */
631#define AHB0_UDC (ARM_BUS0_BASE + 0x000A0000)
632#define PHY_TEST_EN (*(volatile unsigned long *)(AHB0_UDC + 0x00))
633#define PHY_TEST (*(volatile unsigned long *)(AHB0_UDC + 0x04))
634#define DEV_CTL (*(volatile unsigned long *)(AHB0_UDC + 0x08))
635#define DEV_RMTWKP (1<<2)
636#define DEV_SELF_PWR (1<<3)
637#define DEV_SOFT_CN (1<<4)
638#define DEV_RESUME (1<<5)
639#define DEV_PHY16BIT (1<<6)
640#define SOFT_POR (1<<7)
641#define CSR_DONE (1<<8)
642
643#define DEV_INFO (*(volatile unsigned long *)(AHB0_UDC + 0x10))
644#define DEV_EN (1<<7)
645#define VBUS_STS (1<<20)
646#define DEV_SPEED (3<<21)
647
648#define EN_INT (*(volatile unsigned long *)(AHB0_UDC + 0x14))
649#define EN_SOF_INTR (1<<0)
650#define EN_SETUP_INTR (1<<1)
651#define EN_IN0_INTR (1<<2)
652#define EN_OUT0_INTR (1<<3)
653#define EN_USBRST_INTR (1<<4)
654#define EN_RESUME_INTR (1<<5)
655#define EN_SUSP_INTR (1<<6)
656/* bit 7 reserved */
657#define EN_BOUT1_INTR (1<<8)
658#define EN_BIN2_INTR (1<<9)
659#define EN_IIN3_INTR (1<<10)
660#define EN_BOUT4_INTR (1<<11)
661#define EN_BIN5_INTR (1<<12)
662#define EN_IIN6_INTR (1<<13)
663#define EN_BOUT7_INTR (1<<14)
664#define EN_BIN8_INTR (1<<15)
665#define EN_IIN9_INTR (1<<16)
666#define EN_BOUT10_INTR (1<<17)
667#define EN_BIN11_INTR (1<<18)
668#define EN_IIN12_INTR (1<<19)
669#define EN_BOUT13_INTR (1<<20)
670#define EN_BIN14_INTR (1<<21)
671#define EN_IIN15_INTR (1<<22)
672/* bits 23-26 TEST */
673/* bits 27-31 reserved */
674
675#define INT2FLAG (*(volatile unsigned long *)(AHB0_UDC + 0x18))
676#define SOF_INTR (1<<0)
677#define SETUP_INTR (1<<1)
678#define IN0_INTR (1<<2)
679#define OUT0_INTR (1<<3)
680#define USBRST_INTR (1<<4)
681#define RESUME_INTR (1<<5)
682#define SUSP_INTR (1<<6)
683#define CONN_INTR (1<<7) /* marked as reserved in DS */
684#define BOUT1_INTR (1<<8)
685#define BIN2_INTR (1<<9)
686#define IIN3_INTR (1<<10)
687#define BOUT4_INTR (1<<11)
688#define BIN5_INTR (1<<12)
689#define IIN6_INTR (1<<13)
690#define BOUT7_INTR (1<<14)
691#define BIN8_INTR (1<<15)
692#define IIN9_INTR (1<<16)
693#define BOUT10_INTR (1<<17)
694#define BIN11_INTR (1<<18)
695#define IIN12_INTR (1<<19)
696#define BOUT13_INTR (1<<20)
697#define BIN14_INTR (1<<21)
698#define IIN15_INTR (1<<22)
699/* bits 23-26 TEST */
700/* bits 27-31 reserved */
701
702#define INTCON (*(volatile unsigned long *)(AHB0_UDC + 0x1C))
703#define UDC_INTEN (1<<0)
704#define UDC_INTEDGE_TRIG (1<<1)
705#define UDC_INTHIGH_ACT (1<<2)
706
707#define SETUP1 (*(volatile unsigned long *)(AHB0_UDC + 0x20))
708#define SETUP2 (*(volatile unsigned long *)(AHB0_UDC + 0x24))
709#define AHBCON (*(volatile unsigned long *)(AHB0_UDC + 0x28))
710#define RX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x30))
711#define RX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x34))
712#define RX0DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x38))
713#define RX0DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x3C))
714#define TX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x40))
715#define TX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x44))
716#define TX0BUF (*(volatile unsigned long *)(AHB0_UDC + 0x48))
717#define TX0DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x4C))
718#define TX0DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x50))
719#define RX1STAT (*(volatile unsigned long *)(AHB0_UDC + 0x54))
720#define RX1CON (*(volatile unsigned long *)(AHB0_UDC + 0x58))
721#define RX1DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x5C))
722#define RX1DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x60))
723#define TX2STAT (*(volatile unsigned long *)(AHB0_UDC + 0x64))
724#define TX2CON (*(volatile unsigned long *)(AHB0_UDC + 0x68))
725#define TX2BUF (*(volatile unsigned long *)(AHB0_UDC + 0x6C))
726#define TX2DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x70))
727#define TX2DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x74))
728#define TX3STAT (*(volatile unsigned long *)(AHB0_UDC + 0x78))
729#define TX3CON (*(volatile unsigned long *)(AHB0_UDC + 0x7C))
730#define TX3BUF (*(volatile unsigned long *)(AHB0_UDC + 0x80))
731#define TX3DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x84))
732#define TX3DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x88))
733#define RX4STAT (*(volatile unsigned long *)(AHB0_UDC + 0x8C))
734#define RX4CON (*(volatile unsigned long *)(AHB0_UDC + 0x90))
735#define RX4DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x94))
736#define RX4DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x98))
737#define TX5STAT (*(volatile unsigned long *)(AHB0_UDC + 0x9C))
738#define TX5CON (*(volatile unsigned long *)(AHB0_UDC + 0xA0))
739#define TX5BUF (*(volatile unsigned long *)(AHB0_UDC + 0xA4))
740#define TX5DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xA8))
741#define TX5DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xAC))
742#define TX6STAT (*(volatile unsigned long *)(AHB0_UDC + 0xB0))
743#define TX6CON (*(volatile unsigned long *)(AHB0_UDC + 0xB4))
744#define TX6BUF (*(volatile unsigned long *)(AHB0_UDC + 0xB8))
745#define TX6DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xBC))
746#define TX6DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xC0))
747#define RX7STAT (*(volatile unsigned long *)(AHB0_UDC + 0xC4))
748#define RX7CON (*(volatile unsigned long *)(AHB0_UDC + 0xC8))
749#define RX7DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0xCC))
750#define RX7DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0xD0))
751#define TX8STAT (*(volatile unsigned long *)(AHB0_UDC + 0xD4))
752#define TX8CON (*(volatile unsigned long *)(AHB0_UDC + 0xD8))
753#define TX8BUF (*(volatile unsigned long *)(AHB0_UDC + 0xDC))
754#define TX8DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xE0))
755#define TX8DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xE4))
756#define TX9STAT (*(volatile unsigned long *)(AHB0_UDC + 0xE8))
757#define TX9CON (*(volatile unsigned long *)(AHB0_UDC + 0xEC))
758#define TX9BUF (*(volatile unsigned long *)(AHB0_UDC + 0xF0))
759#define TX9DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xF4))
760#define TX9DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xF8))
761#define RX10STAT (*(volatile unsigned long *)(AHB0_UDC + 0xFC))
762#define RX10CON (*(volatile unsigned long *)(AHB0_UDC + 0x100))
763#define RX10DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x104))
764#define RX10DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x108))
765#define TX11STAT (*(volatile unsigned long *)(AHB0_UDC + 0x10C))
766#define TX11CON (*(volatile unsigned long *)(AHB0_UDC + 0x110))
767#define TX11BUF (*(volatile unsigned long *)(AHB0_UDC + 0x114))
768#define TX11DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x118))
769#define TX11DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x11C))
770#define TX12STAT (*(volatile unsigned long *)(AHB0_UDC + 0x120))
771#define TX12CON (*(volatile unsigned long *)(AHB0_UDC + 0x124))
772#define TX12BUF (*(volatile unsigned long *)(AHB0_UDC + 0x128))
773#define TX12DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x12C))
774#define TX12DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x130))
775#define RX13STAT (*(volatile unsigned long *)(AHB0_UDC + 0x134))
776#define RX13CON (*(volatile unsigned long *)(AHB0_UDC + 0x138))
777#define RX13DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x13C))
778#define RX13DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x140))
779#define TX14STAT (*(volatile unsigned long *)(AHB0_UDC + 0x144))
780#define TX14CON (*(volatile unsigned long *)(AHB0_UDC + 0x148))
781#define TX14BUF (*(volatile unsigned long *)(AHB0_UDC + 0x14C))
782#define TX14DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x150))
783#define TX14DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x154))
784#define TX15STAT (*(volatile unsigned long *)(AHB0_UDC + 0x158))
785#define TX15CON (*(volatile unsigned long *)(AHB0_UDC + 0x15C))
786#define TX15BUF (*(volatile unsigned long *)(AHB0_UDC + 0x160))
787#define TX15DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x164))
788#define TX15DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x168))
789
790/* RXnSTAT bits */
791/* bits 10:0 RXLEN */
792/* bits 15:11 reserved */
793#define RXVOID (1<<16)
794#define RXERR (1<<17)
795#define RXACK (1<<18)
796#define RXCFINT (1<<19) /* reserved for EP0 */
797/* bits 23:20 reserved */
798#define RXFULL (1<<24)
799#define RXOVF (1<<25)
800/* bits 31:26 reserved */
801
802/* RXnCON bits */
803#define RXFFRC (1<<0)
804#define RXCLR (1<<1)
805#define RXSTALL (1<<2)
806#define RXNAK (1<<3)
807#define RXEPEN (1<<4)
808#define RXVOIDINTEN (1<<5)
809#define RXERRINTEN (1<<6)
810#define RXACKINTEN (1<<7)
811/* bits 31:8 reserved for EP0 */
812/* bits 31:14 reserved for others */
813
814/* TxnSTAT */
815/* bits 10:0 TXLEN */
816/* bits 15:11 reserved */
817#define TXVOID (1<<16)
818#define TXERR (1<<17)
819#define TXACK (1<<18)
820#define TXDMADN (1<<19) /* reserved for EP0 */
821#define TXCFINT (1<<20) /* reserved for EP0 */
822/* bits 31:21 reserved */
823
824/* TXnCON bits */
825#define TXCLR (1<<0)
826#define TXSTALL (1<<1)
827#define TXNAK (1<<2)
828#define TXEPEN (1<<3) /* reserved for EP0 */
829#define TXVOIDINTEN (1<<4)
830#define TXERRINTEN (1<<5)
831#define TXACKINTEN (1<<6)
832#define TXDMADNEN (1<<7) /* reserved for EP0 */
833/* bits 31:8 reserved */
834
835/* TXnBUF bits */
836#define TXFULL (1<<0)
837#define TXURF (1<<1)
838#define TXDS0 (1<<2) /* reserved for EP0 */
839#define TXDS1 (1<<3) /* reserved for EP0 */
840/* bits 31:4 reserved */
841
842/* DMA bits */
843#define DMA_START (1<<0)
844/* bits 31:1 reserved */
845
846/* USB host controller */
847#define AHB0_UHC (ARM_BUS0_BASE + 0x000A4000)
848/* documentation missing */
849
850/* 0x180A8000 - 0x180B0000 reserved */
851
852/* Static/SDRAM memory controller */
853#define AHB0_SDRSTMC (ARM_BUS0_BASE + 0x000B0000)
854#define MCSDR_MODE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x100))
855#define MCSDR_ADDMAP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x104))
856#define MCSDR_ADDCFG (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x108))
857#define MCSDR_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x10C))
858#define MCSDR_T_REF (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x110))
859#define MCSDR_T_RFC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x114))
860#define MCSDR_T_MRD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x118))
861#define MCSDR_T_RP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x120))
862#define MCSDR_T_RCD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x124))
863
864#define MCST0_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x200))
865#define MCST0_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x204))
866#define MCST0_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x208))
867#define MCST0_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x20C))
868#define MCST0_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x210))
869#define MCST0_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x214))
870#define MCST0_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x218))
871#define MCST0_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x21C))
872#define MCST0_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x220))
873
874#define MCST1_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x300))
875#define MCST1_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x304))
876#define MCST1_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x308))
877#define MCST1_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x30C))
878#define MCST1_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x310))
879#define MCST1_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x314))
880#define MCST1_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x318))
881#define MCST1_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x31C))
882#define MCST1_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x320))
883
884/* 0x180B4000 - 0x180C000 reserved */
885
886/* VIP - video input processor */
887#define AHB0_VIP (ARM_BUS0_BASE + 0x000C0000)
888
889/* 0x180C4000 - 0x180E8000 reserved */
890
891/* NAND flash controller */
892#define AHB0_NANDC (ARM_BUS0_BASE + 0x000E8000)
893
894#define FMCTL (*(volatile unsigned long *)(AHB0_NANDC))
895#define FM_RDY (1<<5) /* status of line R/B# */
896#define FM_PROTECT (1<<4) /* WP# line (active low) */
897/* bits 0-3 are chip selects */
898
899#define FMWAIT (*(volatile unsigned long *)(AHB0_NANDC + 0x04))
900#define FLCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x08))
901#define FL_RDY (1<<12)
902#define FL_COR_EN (1<<11)
903#define FL_INT_EN (1<<10)
904#define FL_XFER_EN (1<<9)
905#define FL_INTCLR_EN (1<<8)
906/* bits 3-7 unknown */
907#define FL_START (1<<2)
908#define FL_WR (1<<1)
909#define FL_RST (1<<0)
910
911#define BCHCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x0C))
912/* bit 13 is used but unknown */
913/* bit 12 is used but unknown */
914#define BCH_WR (1<<1)
915#define BCH_RST (1<<0)
916
917#define BCHST (*(volatile unsigned long *)(AHB0_NANDC + 0xD0))
918/* bit 2 ERR ?? */
919/* bit 0 ?? */
920
921#define FLASH_DATA(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x200 + (n<<9)))
922#define FLASH_ADDR(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x204 + (n<<9)))
923#define FLASH_CMD(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x208 + (n<<9)))
924
925#define PAGE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0xA00))
926#define SPARE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0x1200))
927
928#define AHB0_ROM (ARM_BUS0_BASE + 0x000EC000)
929#define AHB0_ES3 (ARM_BUS0_BASE + 0x000F4000)
930#define AHB0_ES4 (ARM_BUS0_BASE + 0x000F8000)
931#define AHB0_ES5 (ARM_BUS0_BASE + 0x000FC000)
932#define AHB0_ES6 (ARM_BUS0_BASE + 0x00100000)
933#define AHB0_EMD_SRAM (ARM_BUS0_BASE + 0x00200000)
934
935/* 0x18204000 - 0x1840000 reserved */
936
937/* 0x18400000 - 0x18484000 reserved*/
938
939#define AHB1_ARBITER 0x18484000
940/* 0x18488000 - 0x186E8000 reserved*/
941
942/* LCD controller */
943#define AHB1_LCDC 0x186E8000
944#define LCDC_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x00))
945/* bits 14-31 reserved */
946#define ALPHA24B (1<<13)
947#define UVBUFEXCH (1<<12)
948#define ALPHA(x) (((x)&0x07)<<9)
949#define Y_MIX (1<<8)
950#define LCDC_MCU (1<<7)
951#define RGB24B (1<<6)
952#define START_EVEN (1<<5)
953#define EVEN_EN (1<<4)
954#define RGB_DUMMY(x) (((x)&0x03)<<2)
955#define LCDC_EN (1<<1)
956#define LCDC_STOP (1<<0)
957#define MCU_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x04))
958
959#define ALPHA_BASE(x) (((x)&0x3f)<<8)
960#define MCU_CTRL_FIFO_EN (1<<6)
961#define MCU_CTRL_RS_HIGH (1<<5)
962#define MCU_CTRL_BUFF_WRITE (1<<2)
963#define MCU_CTRL_BUFF_START (1<<1)
964#define MCU_CTRL_BYPASS (1<<0)
965
966#define HOR_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x08))
967#define VERT_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x0C))
968#define HOR_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x10))
969#define VERT_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x14))
970#define HOR_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x18))
971#define VERT_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x1C))
972#define HOR_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x20))
973#define VERT_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x24))
974#define LINE0_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x28))
975#define LINE_ALPHA_EN (1<<14)
976#define LINE_SCALE_EN (1<<13)
977#define LINE_GBR (1<<12)
978#define LINE_RGB (0<<12)
979#define LINE_YUV_SRC (1<<11)
980#define LINE_RGB_SRC (0<<11)
981/* bits 0-10 Y_BASE */
982
983#define LINE0_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x2C))
984#define LINE1_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x30))
985#define LINE1_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x34))
986#define LINE2_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x38))
987#define LINE2_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x3C))
988#define LINE3_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x40))
989#define LINE3_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x44))
990#define START_X (*(volatile unsigned long *)(AHB1_LCDC + 0x48))
991#define START_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x4C))
992#define DELTA_X (*(volatile unsigned long *)(AHB1_LCDC + 0x50))
993#define DELTA_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x54))
994#define LCDC_INTR_MASK (*(volatile unsigned long *)(AHB1_LCDC + 0x58))
995#define INTR_MASK_LINE (1<<3)
996#define INTR_MASK_EVENLINE (0<<3)
997#define INTR_MASK_BUFF (1<<2)
998#define INTR_MASK_VERT (1<<1)
999#define INTR_MASK_HOR (1<<0)
1000
1001#define ALPHA_ALX (*(volatile unsigned long *)(AHB1_LCDC + 0x5C))
1002#define ALPHA_ATY (*(volatile unsigned long *)(AHB1_LCDC + 0x60))
1003#define ALPHA_ARX (*(volatile unsigned long *)(AHB1_LCDC + 0x64))
1004#define ALPHA_ABY (*(volatile unsigned long *)(AHB1_LCDC + 0x68))
1005
1006#define ALPHA_BLX (*(volatile unsigned long *)(AHB1_LCDC + 0x6C))
1007#define ALPHA_BTY (*(volatile unsigned long *)(AHB1_LCDC + 0x70))
1008#define ALPHA_BRX (*(volatile unsigned long *)(AHB1_LCDC + 0x74))
1009#define ALPHA_BBY (*(volatile unsigned long *)(AHB1_LCDC + 0x78))
1010
1011#define LCDC_STA (*(volatile unsigned long *)(AHB1_LCDC + 0x7C))
1012#define LCDC_MCU_IDLE (1<<12)
1013
1014#define LCD_COMMAND (*(volatile unsigned long *)(AHB1_LCDC + 0x1000))
1015#define LCD_DATA (*(volatile unsigned long *)(AHB1_LCDC + 0x1004))
1016
1017#define LCD_BUFF ((volatile void *)(AHB1_LCDC + 0x2000))
1018/* High speed ADC interface */
1019#define AHB1_HS_ADC 0x186EC000
1020#define HSADC_DATA (*(volatile unsigned long *)(AHB1_HS_ADC + 0x00))
1021#define HSADC_CTRL (*(volatile unsigned long *)(AHB1_HS_ADC + 0x04))
1022#define HSADC_IER (*(volatile unsigned long *)(AHB1_HS_ADC + 0x08))
1023#define HSADC_ISR (*(volatile unsigned long *)(AHB1_HS_ADC + 0x0C))
1024
1025/* AHB-to-AHB DMA controller */
1026#define AHB1_DWDMA 0x186F0000
1027#define DWDMA_SAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x00 + 0x58*n))
1028#define DWDMA_DAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x08 + 0x58*n))
1029#define DWDMA_LLP(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x10 + 0x58*n))
1030#define DWDMA_CTL_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x18 + 0x58*n))
1031#define CTLL_LLP_SRC_EN (1<<28)
1032#define CTLL_LLP_DST_EN (1<<27)
1033#define CTLL_SMS_M2 (1<<25)
1034#define CTLL_SMS_M1 (0<<25)
1035#define CTLL_DMS_M2 (1<<23)
1036#define CTLL_DMS_M1 (0<<23)
1037#define CTLL_FC_PER2PER (3<<20)
1038#define CTLL_FC_PER2MEM (2<<20)
1039#define CTLL_FC_MEM2PER (1<<20)
1040#define CTLL_FC_MEM2MEM (0<<20)
1041/* bit 19 reserved */
1042#define CTLL_DST_SCATTER_EN (1<<18)
1043#define CTLL_SRC_GATHER_EN (1<<17)
1044#define CTLL_SRC_MSIZE_32 (4<<14)
1045#define CTLL_SRC_MSIZE_16 (3<<14)
1046#define CTLL_SRC_MSIZE_8 (2<<14)
1047#define CTLL_SRC_MSIZE_4 (1<<14)
1048#define CTLL_SRC_MSIZE_1 (0<<14)
1049#define CTLL_DST_MSIZE_32 (4<<11)
1050#define CTLL_DST_MSIZE_16 (3<<11)
1051#define CTLL_DST_MSIZE_8 (2<<11)
1052#define CTLL_DST_MSIZE_4 (1<<11)
1053#define CTLL_DST_MSIZE_1 (0<<11)
1054#define CTLL_SINC_NO (2<<9)
1055#define CTLL_SINC_DEC (1<<9)
1056#define CTLL_SINC_INC (0<<9)
1057#define CTLL_DINC_NO (2<<7)
1058#define CTLL_DINC_DEC (1<<7)
1059#define CTLL_DINC_INC (0<<7)
1060#define CTLL_SRC_TR_WIDTH_32 (2<<4)
1061#define CTLL_SRC_TR_WIDTH_16 (1<<4)
1062#define CTLL_SRC_TR_WIDTH_8 (0<<4)
1063#define CTLL_DST_TR_WIDTH_32 (2<<1)
1064#define CTLL_DST_TR_WIDTH_16 (1<<1)
1065#define CTLL_DST_TR_WIDTH_8 (0<<1)
1066#define CTLL_INT_EN (1<<0)
1067
1068#define DWDMA_CTL_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x1C + 0x58*n))
1069#define DWDMA_SSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x20 + 0x58*n))
1070#define DWDMA_DSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x28 + 0x58*n))
1071#define DWDMA_SSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x30 + 0x58*n))
1072#define DWDMA_DSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x38 + 0x58*n))
1073#define DWDMA_CFG_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x40 + 0x58*n))
1074#define CFGL_RELOAD_DST (1<<31)
1075#define CFGL_RELOAD_SRC (1<<30)
1076#define CFGL_MAX_ABRST(n) ((n)<<20)
1077#define CFGL_SRC_HS_POL_LOW (1<<19)
1078#define CFGL_DST_HS_POL_LOW (1<<18)
1079#define CFGL_LOCK_B (1<<17)
1080#define CFGL_LOCK_CH (1<<16)
1081#define CFGL_LOCK_B_L(n) (((n)&0x03)<<14)
1082#define CFGL_LOCK_CH_L(n) (((n)&0x03)<<12)
1083#define CFGL_HS_SEL_SRC (1<<11)
1084#define CFGL_HS_SEL_DST (1<<10)
1085#define CFGL_FIFO_EMPTY (1<<9)
1086#define CFGL_CH_SUSP (1<<8)
1087#define CFGL_CH_PRIOR(n) (((n) & 0x03)<<5)
1088/* bits 0-4 reserved */
1089#define DWDMA_CFG_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x44 + 0x58*n))
1090#define CFGH_DST_PER(n) (((n)&0x0F)<<11)
1091#define CFGH_SRC_PER(n) (((n)&0x0F)<<7)
1092#define CFGH_SRC_UPD_EN (1<<6)
1093#define CFGH_DST_UPD_EN (1<<5)
1094#define CFGH_PROTCTL(n) (((n)&0x07)<<2)
1095#define CFGH_FIFO_MODE (1<<1)
1096#define CFGH_FC_MODE (1<<0)
1097
1098#define DWDMA_SGR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x48 + 0x58*n))
1099#define DWDMA_DSR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x50 + 0x58*n))
1100
1101#define DWDMA_RAW_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C0))
1102#define DWDMA_RAW_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C8))
1103#define DWDMA_RAW_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D0))
1104#define DWDMA_RAW_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D8))
1105#define DWDMA_RAW_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E0))
1106
1107#define DWDMA_STATUS_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E8))
1108#define DWDMA_STATUS_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F0))
1109#define DWDMA_STATUS_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F8))
1110#define DWDMA_STATUS_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x300))
1111#define DWDMA_STATUS_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x308))
1112
1113#define DWDMA_MASK_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x310))
1114#define DWDMA_MASK_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x318))
1115#define DWDMA_MASK_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x320))
1116#define DWDMA_MASK_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x328))
1117#define DWDMA_MASK_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x330))
1118
1119#define DWDMA_CLEAR_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x338))
1120#define DWDMA_CLEAR_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x340))
1121#define DWDMA_CLEAR_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x348))
1122#define DWDMA_CLEAR_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x350))
1123#define DWDMA_CLEAR_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x358))
1124
1125#define DWDMA_STATUS_INT (*(volatile unsigned long *)(AHB1_DWDMA + 0x360))
1126
1127#define DWDMA_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x368))
1128#define DWDMA_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x370))
1129#define DWDMA_S_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x378))
1130#define DWDMA_S_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x380))
1131#define DWDMA_L_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x388))
1132#define DWDMA_L_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x390))
1133
1134#define DWDMA_DMA_CFG (*(volatile unsigned long *)(AHB1_DWDMA + 0x398))
1135#define GLOB_EN (1<<0)
1136#define DWDMA_DMA_CHEN (*(volatile unsigned long *)(AHB1_DWDMA + 0x3A0))
1137#define DMACHEN_CH0 (0x101<<0)
1138#define DMACHEN_CH1 (0x101<<1)
1139#define DMACHEN_CH2 (0x101<<2)
1140#define DMACHEN_CH3 (0x101<<3)
1141
1142/* ARM7 cache controller */
1143#define ARM_CACHE_CTRL 0xEFFF0000
1144#define DEVID (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x00))
1145#define CACHEOP (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x04))
1146#define CACHELKDN (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x08))
1147
1148#define MEMMAPA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x10))
1149#define MEMMAPB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x14))
1150#define MEMMAPC (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x18))
1151#define MEMMAPD (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x1C))
1152#define PFCNTRA_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x20))
1153#define PFCNTRA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x24))
1154#define PFCNTRB_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x28))
1155#define PFCNTRB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x2C))
1156
1157/* Timer frequency */
1158#define TIMER_FREQ 50000000
diff --git a/utils/hwstub/stub/rk27xx/target-config.h b/utils/hwstub/stub/rk27xx/target-config.h
new file mode 100644
index 0000000000..6af214efaf
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/target-config.h
@@ -0,0 +1,9 @@
1#define CONFIG_RK27XX
2#define IRAM_ORIG 0x60000000
3#define IRAM_SIZE 0x8000
4#define DRAM_ORIG 0x60000000
5#define DRAM_SIZE (MEMORYSIZE * 0x100000)
6#define CPU_ARM
7#define ARM_ARCH 5
8#define USB_BASE 0x180A000
9#define USB_NUM_ENDPOINTS 2
diff --git a/utils/hwstub/stub/rk27xx/target.c b/utils/hwstub/stub/rk27xx/target.c
new file mode 100644
index 0000000000..f9efccaef0
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/target.c
@@ -0,0 +1,172 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 *
9 * Copyright (C) 2013 by Marcin Bukat
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
17 * KIND, either express or implied.
18 *
19 ****************************************************************************/
20#include "stddef.h"
21#include "target.h"
22#include "system.h"
23#include "logf.h"
24#include "rk27xx.h"
25
26#define HZ 1000000
27
28enum rk27xx_family_t
29{
30 UNKNOWN,
31 REV_A,
32 REV_B,
33};
34
35static enum rk27xx_family_t g_rk27xx_family = UNKNOWN;
36static int g_atexit = HWSTUB_ATEXIT_OFF;
37
38static void _enable_irq(void)
39{
40 asm volatile ("mrs r0, cpsr\n"
41 "bic r0, r0, #0x80\n"
42 "msr cpsr_c, r0\n"
43 );
44}
45
46static void power_off(void)
47{
48 GPIO_PCCON &= ~(1<<0);
49 while(1);
50}
51
52static void rk27xx_reset(void)
53{
54 /* use Watchdog to reset */
55 SCU_CLKCFG &= ~CLKCFG_WDT;
56 WDTLR = 1;
57 WDTCON = (1<<4) | (1<<3);
58
59 /* Wait for reboot to kick in */
60 while(1);
61}
62
63/* us may be at most 2^31/200 (~10 seconds) for 200MHz max cpu freq */
64void target_udelay(int us)
65{
66 unsigned cycles_per_us;
67 unsigned delay;
68
69 cycles_per_us = (200000000 + 999999) / 1000000;
70
71 delay = (us * cycles_per_us) / 5;
72
73 asm volatile(
74 "1: subs %0, %0, #1 \n" /* 1 cycle */
75 " nop \n" /* 1 cycle */
76 " bne 1b \n" /* 3 cycles */
77 : : "r"(delay)
78 );
79}
80
81void target_mdelay(int ms)
82{
83 return target_udelay(ms * 1000);
84}
85
86void target_init(void)
87{
88 /* ungate all clocks */
89 SCU_CLKCFG = 0;
90
91 /* keep act line */
92 GPIO_PCDR |= (1<<0);
93 GPIO_PCCON |= (1<<0);
94
95 /* disable watchdog */
96 WDTCON &= ~(1<<3);
97
98 /* enable UDC interrupt */
99 INTC_IMR = (1<<16);
100 INTC_IECR = (1<<16);
101
102 EN_INT = EN_SUSP_INTR | /* Enable Suspend Interrupt */
103 EN_RESUME_INTR | /* Enable Resume Interrupt */
104 EN_USBRST_INTR | /* Enable USB Reset Interrupt */
105 EN_OUT0_INTR | /* Enable OUT Token receive Interrupt EP0 */
106 EN_IN0_INTR | /* Enable IN Token transmits Interrupt EP0 */
107 EN_SETUP_INTR; /* Enable SETUP Packet Receive Interrupt */
108
109 /* 6. configure INTCON */
110 INTCON = UDC_INTHIGH_ACT | /* interrupt high active */
111 UDC_INTEN; /* enable EP0 interrupts */
112
113 /* enable irq */
114 _enable_irq();
115
116 /* detect revision */
117 uint32_t rk27xx_id = SCU_ID;
118
119 if(rk27xx_id == 0xa1000604)
120 {
121 logf("identified rk27xx REV_A \n");
122 g_rk27xx_family = REV_A;
123 }
124 else if(rk27xx_id == 0xa100027b)
125 {
126 logf("identified rk27xx REV_B \n");
127 g_rk27xx_family = REV_B;
128 }
129 else
130 {
131 logf("unknown rk27xx revision \n");
132 }
133}
134
135static struct usb_resp_info_target_t g_target =
136{
137 .id = HWSTUB_TARGET_RK27,
138 .name = "Rockchip RK27XX"
139};
140
141int target_get_info(int info, void **buffer)
142{
143 if(info == HWSTUB_INFO_TARGET)
144 {
145 *buffer = &g_target;
146 return sizeof(g_target);
147 }
148 else
149 return -1;
150}
151
152int target_atexit(int method)
153{
154 g_atexit = method;
155 return 0;
156}
157
158void target_exit(void)
159{
160 switch(g_atexit)
161 {
162 case HWSTUB_ATEXIT_OFF:
163 power_off();
164 // fallthrough in case of return
165 case HWSTUB_ATEXIT_REBOOT:
166 rk27xx_reset();
167 // fallthrough in case of return
168 case HWSTUB_ATEXIT_NOP:
169 default:
170 return;
171 }
172}
diff --git a/utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c b/utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c
new file mode 100644
index 0000000000..6a9293334a
--- /dev/null
+++ b/utils/hwstub/stub/rk27xx/usb_drv_rk27xx.c
@@ -0,0 +1,313 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 *
9 * Copyright (C) 2011 by Marcin Bukat
10 * Copyright (C) 2012 by Amaury Pouly
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#include "usb_drv.h"
23#include "config.h"
24#include "memory.h"
25#include "target.h"
26#include "rk27xx.h"
27
28typedef volatile uint32_t reg32;
29
30#define USB_FULL_SPEED 0
31#define USB_HIGH_SPEED 1
32
33/* max allowed packet size definitions */
34#define CTL_MAX_SIZE 64
35
36struct endpoint_t {
37 const int type; /* EP type */
38 const int dir; /* DIR_IN/DIR_OUT */
39 const unsigned int intr_mask;
40 bool allocated; /* flag to mark EPs taken */
41 volatile void *buf; /* tx/rx buffer address */
42 volatile int len; /* size of the transfer (bytes) */
43 volatile int cnt; /* number of bytes transfered/received */
44};
45
46static struct endpoint_t ctrlep[2] = {
47 {USB_ENDPOINT_XFER_CONTROL, DIR_OUT, 0, true, NULL, 0, 0},
48 {USB_ENDPOINT_XFER_CONTROL, DIR_IN, 0, true, NULL, 0, 0}
49};
50
51volatile bool setup_data_valid = false;
52static volatile uint32_t setup_data[2];
53
54static volatile bool usb_drv_send_done = false;
55
56void usb_drv_configure_endpoint(int ep_num, int type)
57{
58 /* not needed as we use EP0 only */
59 (void)ep_num;
60 (void)type;
61}
62
63int usb_drv_recv_setup(struct usb_ctrlrequest *req)
64{
65 while (!setup_data_valid)
66 ;
67
68 memcpy(req, (void *)setup_data, sizeof(struct usb_ctrlrequest));
69 setup_data_valid = false;
70 return 0;
71}
72
73static void setup_irq_handler(void)
74{
75 /* copy setup data from packet */
76 setup_data[0] = SETUP1;
77 setup_data[1] = SETUP2;
78
79 /* ack upper layer we have setup data */
80 setup_data_valid = true;
81}
82
83/* service ep0 IN transaction */
84static void ctr_write(void)
85{
86 int xfer_size = MIN(ctrlep[DIR_IN].cnt, CTL_MAX_SIZE);
87
88 while (TX0BUF & TXFULL) /* TX0FULL flag */
89 ;
90
91 TX0STAT = xfer_size; /* size of the transfer */
92 TX0DMALM_IADDR = (uint32_t)ctrlep[DIR_IN].buf; /* local buffer address */
93 TX0DMAINCTL = DMA_START; /* start DMA */
94 TX0CON &= ~TXNAK; /* clear NAK */
95
96 /* Decrement by max packet size is intentional.
97 * This way if we have final packet short one we will get negative len
98 * after transfer, which in turn indicates we *don't* need to send
99 * zero length packet. If the final packet is max sized packet we will
100 * get zero len after transfer which indicates we need to send
101 * zero length packet to signal host end of the transfer.
102 */
103 ctrlep[DIR_IN].cnt -= CTL_MAX_SIZE;
104 ctrlep[DIR_IN].buf += xfer_size;
105}
106
107static void ctr_read(void)
108{
109 int xfer_size = RX0STAT & 0xffff;
110
111 /* clear NAK bit */
112 RX0CON &= ~RXNAK;
113
114 ctrlep[DIR_OUT].cnt -= xfer_size;
115 ctrlep[DIR_OUT].buf += xfer_size;
116
117 RX0DMAOUTLMADDR = (uint32_t)ctrlep[DIR_OUT].buf; /* buffer address */
118 RX0DMACTLO = DMA_START; /* start DMA */
119}
120
121static void udc_phy_reset(void)
122{
123 DEV_CTL |= SOFT_POR;
124 target_mdelay(10); /* min 10ms */
125 DEV_CTL &= ~SOFT_POR;
126}
127
128static void udc_soft_connect(void)
129{
130 DEV_CTL |= CSR_DONE |
131 DEV_SOFT_CN |
132 DEV_SELF_PWR;
133}
134
135/* return port speed */
136int usb_drv_port_speed(void)
137{
138 return ((DEV_INFO & DEV_SPEED) ? USB_FULL_SPEED : USB_HIGH_SPEED);
139}
140
141/* Set the address (usually it's in a register).
142 * There is a problem here: some controller want the address to be set between
143 * control out and ack and some want to wait for the end of the transaction.
144 * In the first case, you need to write some code special code when getting
145 * setup packets and ignore this function (have a look at other drives)
146 */
147void usb_drv_set_address(int address)
148{
149 (void)address;
150 /* UDC sets this automaticaly */
151}
152
153int usb_drv_send(int endpoint, void *ptr, int length)
154{
155 (void)endpoint;
156 struct endpoint_t *ep = &ctrlep[DIR_IN];
157
158 ep->buf = ptr;
159 ep->len = ep->cnt = length;
160
161 ctr_write();
162
163 /* wait for transfer to end */
164 while(!usb_drv_send_done)
165 ;
166
167 usb_drv_send_done = false;
168
169 return 0;
170}
171
172/* Setup a receive transfer. (non blocking) */
173int usb_drv_recv(int endpoint, void* ptr, int length)
174{
175 (void)endpoint;
176 struct endpoint_t *ep = &ctrlep[DIR_OUT];
177
178 ep->buf = ptr;
179 ep->len = ep->cnt = length;
180
181 /* clear NAK bit */
182 RX0CON &= ~RXNAK;
183 RX0DMAOUTLMADDR = (uint32_t)ptr; /* buffer address */
184 RX0DMACTLO = DMA_START; /* start DMA */
185
186 return 0;
187}
188
189/* Stall the endpoint. Usually set a flag in the controller */
190void usb_drv_stall(int endpoint, bool stall, bool in)
191{
192 /* ctrl only anyway */
193 (void)endpoint;
194
195 if(in)
196 {
197 if(stall)
198 TX0CON |= TXSTALL;
199 else
200 TX0CON &= ~TXSTALL;
201 }
202 else
203 {
204 if (stall)
205 RX0CON |= RXSTALL;
206 else
207 RX0CON &= ~RXSTALL; /* doc says Auto clear by UDC 2.0 */
208 }
209}
210
211/* one time init (once per connection) - basicaly enable usb core */
212void usb_drv_init(void)
213{
214 udc_phy_reset();
215 target_mdelay(10); /* wait at least 10ms */
216 udc_soft_connect();
217
218 EN_INT = EN_SUSP_INTR | /* Enable Suspend Irq */
219 EN_RESUME_INTR | /* Enable Resume Irq */
220 EN_USBRST_INTR | /* Enable USB Reset Irq */
221 EN_OUT0_INTR | /* Enable OUT Token receive Irq EP0 */
222 EN_IN0_INTR | /* Enable IN Token transmit Irq EP0 */
223 EN_SETUP_INTR; /* Enable SETUP Packet Receive Irq */
224
225 INTCON = UDC_INTHIGH_ACT | /* interrupt high active */
226 UDC_INTEN; /* enable EP0 irqs */
227}
228
229/* turn off usb core */
230void usb_drv_exit(void)
231{
232 /* udc module reset */
233 SCU_RSTCFG |= (1<<1);
234 target_udelay(10);
235 SCU_RSTCFG &= ~(1<<1);
236}
237
238/* UDC ISR function */
239void INT_UDC(void)
240{
241 uint32_t txstat, rxstat;
242
243 /* read what caused UDC irq */
244 uint32_t intsrc = INT2FLAG & 0x7fffff;
245
246 if (intsrc & USBRST_INTR) /* usb reset */
247 {
248 EN_INT = EN_SUSP_INTR | /* Enable Suspend Irq */
249 EN_RESUME_INTR | /* Enable Resume Irq */
250 EN_USBRST_INTR | /* Enable USB Reset Irq */
251 EN_OUT0_INTR | /* Enable OUT Token receive Irq EP0 */
252 EN_IN0_INTR | /* Enable IN Token transmit Irq EP0 */
253 EN_SETUP_INTR; /* Enable SETUP Packet Receive Irq */
254
255 TX0CON = TXACKINTEN | /* Set as one to enable the EP0 tx irq */
256 TXNAK; /* Set as one to response NAK handshake */
257
258 RX0CON = RXACKINTEN |
259 RXEPEN | /* Endpoint 0 Enable. When cleared the
260 * endpoint does not respond to an SETUP
261 * or OUT token */
262 RXNAK; /* Set as one to response NAK handshake */
263 }
264
265 if (intsrc & SETUP_INTR) /* setup interrupt */
266 {
267 setup_irq_handler();
268 }
269
270 if (intsrc & IN0_INTR) /* ep0 in interrupt */
271 {
272 txstat = TX0STAT; /* read clears flags */
273
274 /* TODO handle errors */
275 if (txstat & TXACK) /* check TxACK flag */
276 {
277 if (ctrlep[DIR_IN].cnt > 0)
278 {
279 /* we still have data to send */
280 ctr_write();
281 }
282 else
283 {
284 if (ctrlep[DIR_IN].cnt == 0)
285 ctr_write();
286
287 /* final ack received */
288 usb_drv_send_done = true;
289 }
290 }
291 }
292
293 if (intsrc & OUT0_INTR) /* ep0 out interrupt */
294 {
295 rxstat = RX0STAT;
296
297 /* TODO handle errors */
298 if (rxstat & RXACK) /* RxACK */
299 {
300 if (ctrlep[DIR_OUT].cnt > 0)
301 ctr_read();
302 }
303 }
304
305 if (intsrc & RESUME_INTR) /* usb resume */
306 {
307 TX0CON |= TXCLR; /* TxClr */
308 TX0CON &= ~TXCLR;
309
310 RX0CON |= RXCLR; /* RxClr */
311 RX0CON &= ~RXCLR;
312 }
313}
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 15:31:38 +0000