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authorAmaury Pouly <amaury.pouly@gmail.com>2017-01-18 14:36:27 +0100
committerAmaury Pouly <amaury.pouly@gmail.com>2017-01-24 15:34:19 +0100
commit9bb6050d40b9936beda5cb1cd15040f6c1b07179 (patch)
tree03fa1ad2b5d20db4cae1d8f7b75deb4d98fbdeee /utils/hwstub/stub/mips-archdefs.h
parentf3cce72269703e983e4a4e6ec8dc9217b0c2b6fe (diff)
downloadrockbox-9bb6050d40b9936beda5cb1cd15040f6c1b07179.tar.gz
rockbox-9bb6050d40b9936beda5cb1cd15040f6c1b07179.zip
hwstub: rewrite exception catching
Since we can catch exceptions like data aborts on read/write, it takes very little to also catch exceptions in calls. When extending this with the catching of illegal instructions, the call instruction now becomes much more robust and also for address and instruction probing. Since we can catch several types of exception, rename set_data_abort_jmp to set_exception_jmp. At the same time, simplify the logic in read/write request handlers. Also fix a bug in ARM jump code: it was using stmia r1, {..., pc} as if pc would get current pc + 8 but this is actually implementation defined on older ARMs (typically pc + 12) and deprecated on newer ARMs, so rewrite the code avoid that. The set_exception_jmp() function now also reports the exception type. Change-Id: Icd0dd52d2456b361b27c4776be09c3d13528ed93
Diffstat (limited to 'utils/hwstub/stub/mips-archdefs.h')
-rw-r--r--utils/hwstub/stub/mips-archdefs.h2358
1 files changed, 2358 insertions, 0 deletions
diff --git a/utils/hwstub/stub/mips-archdefs.h b/utils/hwstub/stub/mips-archdefs.h
new file mode 100644
index 0000000000..79995479c4
--- /dev/null
+++ b/utils/hwstub/stub/mips-archdefs.h
@@ -0,0 +1,2358 @@
1/**************************************************************************
2* *
3* PROJECT : MIPS port for uC/OS-II *
4* *
5* MODULE : ARCHDEFS.h *
6* *
7* AUTHOR : Michael Anburaj *
8* URL : http://geocities.com/michaelanburaj/ *
9* EMAIL: michaelanburaj@hotmail.com *
10* *
11* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
12* *
13* TOOL-CHAIN : SDE & Cygnus *
14* *
15* DESCRIPTION : *
16* Architecture definitions. *
17* *
18**************************************************************************/
19
20
21#ifndef __ARCHDEFS_H__
22#define __ARCHDEFS_H__
23
24
25/* ********************************************************************* */
26/* Module configuration */
27
28
29/* ********************************************************************* */
30/* Interface macro & data definition */
31
32/*
33 * Utility defines for cross platform handling of 64bit constants.
34 */
35
36#if !defined(Append)
37 #define Append(c,s) (c##s)
38#endif
39
40#if !defined(__assembler) && !defined(MIPSAVPENV)
41 #if defined(NT)
42 #if !defined(UNS64Const)
43 #define UNS64Const(c) Append(c,ui64)
44 #endif
45
46 #if !defined(INT64Const)
47 #define INT64Const(c) Append(c,i64)
48 #endif
49 #else
50 #if !defined(UNS64Const)
51 #define UNS64Const(c) Append(c,ull)
52 #endif
53
54 #if !defined(INT64Const)
55 #define INT64Const(c) Append(c,ll)
56 #endif
57 #endif
58#else /* Not C or C++ */
59 #if !defined(UNS64Const)
60 #define UNS64Const(c) c
61 #endif
62
63 #if !defined(INT64Const)
64 #define INT64Const(c) c
65 #endif
66#endif /* C or C++ */
67
68
69/*
70 ************************************************************************
71 * I N S T R U C T I O N F O R M A T S *
72 ************************************************************************
73 *
74 * The following definitions describe each field in an instruction. There
75 * is one diagram for each type of instruction, with field definitions
76 * following the diagram for that instruction. Note that if a field of
77 * the same name and position is defined in an earlier diagram, it is
78 * not defined again in the subsequent diagram. Only new fields are
79 * defined for each diagram.
80 *
81 * R-Type (operate)
82 *
83 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
84 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
85 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
86 * | | rs | rt | rd | sa | |
87 * | Opcode | | | Tcode | func |
88 * | | Bcode | | sel |
89 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
90 */
91
92#define S_InstnOpcode 26
93#define M_InstnOpcode (0x3f << S_InstnOpcode)
94#define S_InstnRS 21
95#define M_InstnRS (0x1f << S_InstnRS)
96#define S_InstnRT 16
97#define M_InstnRT (0x1f << S_InstnRT)
98#define S_InstnRD 11
99#define M_InstnRD (0x1f << S_InstnRD)
100#define S_InstnSA 6
101#define M_InstnSA (0x1f << S_InstnSA)
102#define S_InstnTcode 6
103#define M_InstnTcode (0x3ff << S_InstnTcode)
104#define S_InstnBcode 6
105#define M_InstnBcode (0xfffff << S_InstnBcode)
106#define S_InstnFunc 0
107#define M_InstnFunc (0x3f << S_InstnFunc)
108#define S_InstnSel 0
109#define M_InstnSel (0x7 << S_InstnSel)
110
111/*
112 * I-Type (load, store, branch, immediate)
113 *
114 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
115 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
116 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
117 * | Opcode | rs | rt | Offset |
118 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
119 */
120
121#define S_InstnOffset 0
122#define M_InstnOffset (0xffff << S_InstnOffset)
123
124/*
125 * I-Type (pref)
126 *
127 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
128 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
129 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
130 * | Opcode | rs | hint | Offset |
131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
132 */
133
134#define S_InstnHint S_InstnRT
135#define M_InstnHint M_InstnRT
136
137/*
138 * J-Type (jump)
139 *
140 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
141 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
143 * | Opcode | JIndex |
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 */
146
147#define S_InstnJIndex 0
148#define M_InstnJIndex (0x03ffffff << S_InstnJIndex)
149
150/*
151 * FP R-Type (operate)
152 *
153 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
154 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
155 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
156 * | Opcode | fmt | ft | fs | fd | func |
157 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
158 */
159
160#define S_InstnFmt S_InstnRS
161#define M_InstnFmt M_InstnRS
162#define S_InstnFT S_InstnRT
163#define M_InstnFT M_InstnRT
164#define S_InstnFS S_InstnRD
165#define M_InstnFS M_InstnRD
166#define S_InstnFD S_InstnSA
167#define M_InstnFD M_InstnSA
168
169/*
170 * FP R-Type (cpu <-> cpu data movement))
171 *
172 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
173 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
174 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
175 * | Opcode | sub | rt | fs | 0 |
176 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
177 */
178
179#define S_InstnSub S_InstnRS
180#define M_InstnSub M_InstnRS
181
182/*
183 * FP R-Type (compare)
184 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
185 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
186 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
187 * | | | | | | |C| |
188 * | Opcode | fmt | ft | fs | cc |0|A| func |
189 * | | | | | | |B| |
190 * | | | | | | |S| |
191 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
192 */
193
194#define S_InstnCCcmp 8
195#define M_InstnCCcmp (0x7 << S_InstnCCcmp)
196#define S_InstnCABS 6
197#define M_InstnCABS (0x1 << S_InstnCABS)
198
199/*
200 * FP R-Type (FPR conditional move on FP cc)
201 *
202 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
203 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
204 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
205 * | Opcode | fmt | cc |n|t| fs | fd | func |
206 * | | | |d|f| | | |
207 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
208 */
209
210#define S_InstnCC 18
211#define M_InstnCC (0x7 << S_InstnCC)
212#define S_InstnND 17
213#define M_InstnND (0x1 << S_InstnND)
214#define S_InstnTF 16
215#define M_InstnTF (0x1 << S_InstnTF)
216
217/*
218 * FP R-Type (3-operand operate)
219 *
220 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
221 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
222 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
223 * | Opcode | fr | ft | fs | fd | op4 | fmt3|
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 */
226
227#define S_InstnFR S_InstnRS
228#define M_InstnFR M_InstnRS
229#define S_InstnOp4 3
230#define M_InstnOp4 (0x7 << S_InstnOp4)
231#define S_InstnFmt3 0
232#define M_InstnFmt3 (0x7 << S_InstnFmt3)
233
234/*
235 * FP R-Type (Indexed load, store)
236 *
237 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
238 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
239 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
240 * | Opcode | rs | rt | 0 | fd | func |
241 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
242 */
243/*
244 * FP R-Type (prefx)
245 *
246 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
247 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
248 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
249 * | Opcode | rs | rt | hint | 0 | func |
250 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
251 */
252
253#define S_InstnHintX S_InstnRD
254#define M_InstnHintX M_InstnRD
255
256/*
257 * FP R-Type (GPR conditional move on FP cc)
258 *
259 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
260 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
261 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
262 * | Opcode | rs | cc |n|t| rd | 0 | func |
263 * | | | |d|f| | | |
264 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
265 */
266
267/*
268 * FP I-Type (load, store)
269 *
270 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
271 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
272 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
273 * | Opcode | rs | ft | Offset |
274 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
275 */
276
277/*
278 * FP I-Type (branch)
279 *
280 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
281 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
282 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
283 * | Opcode | fmt | cc |n|t| Offset |
284 * | | | |d|f| |
285 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
286 */
287
288
289/*
290 *************************************************************************
291 * V I R T U A L A D D R E S S D E F I N I T I O N S *
292 *************************************************************************
293 */
294
295#ifdef MIPSADDR64
296#define A_K0BASE UNS64Const(0xffffffff80000000)
297#define A_K1BASE UNS64Const(0xffffffffa0000000)
298#define A_K2BASE UNS64Const(0xffffffffc0000000)
299#define A_K3BASE UNS64Const(0xffffffffe0000000)
300#define A_REGION UNS64Const(0xc000000000000000)
301#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000)
302#else
303#define A_K0BASE 0x80000000
304#define A_K1BASE 0xa0000000
305#define A_K2BASE 0xc0000000
306#define A_K3BASE 0xe0000000
307#endif
308#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */
309
310
311#ifdef MIPS_Model64
312
313#define S_VMAP64 62
314#define M_VMAP64 UNS64Const(0xc000000000000000)
315
316#define K_VMode11 3
317#define K_VMode10 2
318#define K_VMode01 1
319#define K_VMode00 0
320
321#define S_KSEG3 29
322#define M_KSEG3 (0x7 << S_KSEG3)
323#define K_KSEG3 7
324
325#define S_SSEG 29
326#define M_SSEG (0x7 << S_KSEG3)
327#define K_SSEG 6
328
329#define S_KSSEG 29
330#define M_KSSEG (0x7 << S_KSEG3)
331#define K_KSSEG 6
332
333#define S_KSEG1 29
334#define M_KSEG1 (0x7 << S_KSEG3)
335#define K_KSEG1 5
336
337#define S_KSEG0 29
338#define M_KSEG0 (0x7 << S_KSEG3)
339#define K_KSEG0 4
340
341#define S_XKSEG 29
342#define M_XKSEG (0x7 << S_KSEG3)
343#define K_XKSEG 3
344
345#define S_USEG 31
346#define M_USEG (0x1 << S_USEG)
347#define K_USEG 0
348
349#define S_EjtagProbeMem 20
350#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem)
351#define K_EjtagProbeMem 0
352
353
354
355#else
356
357#define S_KSEG3 29
358#define M_KSEG3 (0x7 << S_KSEG3)
359#define K_KSEG3 7
360
361#define S_KSSEG 29
362#define M_KSSEG (0x7 << S_KSSEG)
363#define K_KSSEG 6
364
365#define S_SSEG 29
366#define M_SSEG (0x7 << S_SSEG)
367#define K_SSEG 6
368
369#define S_KSEG1 29
370#define M_KSEG1 (0x7 << S_KSEG1)
371#define K_KSEG1 5
372
373#define S_KSEG0 29
374#define M_KSEG0 (0x7 << S_KSEG0)
375#define K_KSEG0 4
376
377#define S_KUSEG 31
378#define M_KUSEG (0x1 << S_KUSEG)
379#define K_KUSEG 0
380
381#define S_SUSEG 31
382#define M_SUSEG (0x1 << S_SUSEG)
383#define K_SUSEG 0
384
385#define S_USEG 31
386#define M_USEG (0x1 << S_USEG)
387#define K_USEG 0
388
389#define K_EjtagLower 0xff200000
390#define K_EjtagUpper 0xff3fffff
391
392#define S_EjtagProbeMem 20
393#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem)
394#define K_EjtagProbeMem 0
395
396#endif
397
398
399
400/*
401 *************************************************************************
402 * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S *
403 *************************************************************************
404 */
405
406/*
407 * Cache encodings
408 */
409#define K_CachePriI 0 /* Primary Icache */
410#define K_CachePriD 1 /* Primary Dcache */
411#define K_CachePriU 1 /* Unified primary */
412#define K_CacheTerU 2 /* Unified Tertiary */
413#define K_CacheSecU 3 /* Unified secondary */
414
415
416/*
417 * Function encodings
418 */
419#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */
420#define K_CacheIndexInv 0 /* Index invalidate */
421#define K_CacheIndexWBInv 0 /* Index writeback invalidate */
422#define K_CacheIndexLdTag 1 /* Index load tag */
423#define K_CacheIndexStTag 2 /* Index store tag */
424#define K_CacheHitInv 4 /* Hit Invalidate */
425#define K_CacheFill 5 /* Fill (Icache only) */
426#define K_CacheHitWBInv 5 /* Hit writeback invalidate */
427#define K_CacheHitWB 6 /* Hit writeback */
428#define K_CacheFetchLock 7 /* Fetch and lock */
429
430#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
431#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
432#define DCIndexInv DCIndexWBInv
433#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
434#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
435#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
436#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
437#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
438#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
439#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI)
440#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
441#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
442#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
443#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
444
445
446/*
447 *************************************************************************
448 * P R E F E T C H I N S T R U C T I O N H I N T S *
449 *************************************************************************
450 */
451
452#define PrefLoad 0
453#define PrefStore 1
454#define PrefLoadStreamed 4
455#define PrefStoreStreamed 5
456#define PrefLoadRetained 6
457#define PrefStoreRetained 7
458#define PrefWBInval 25
459#define PrefNudge 25
460
461
462/*
463 *************************************************************************
464 * C P U R E G I S T E R D E F I N I T I O N S *
465 *************************************************************************
466 */
467
468
469/*
470 *************************************************************************
471 * S O F T W A R E G P R N A M E S *
472 *************************************************************************
473 */
474
475#define zero $0
476#define AT $1
477#define v0 $2
478#define v1 $3
479#define a0 $4
480#define a1 $5
481#define a2 $6
482#define a3 $7
483#define t0 $8
484#define t1 $9
485#define t2 $10
486#define t3 $11
487#define t4 $12
488#define t5 $13
489#define t6 $14
490#define t7 $15
491#define s0 $16
492#define s1 $17
493#define s2 $18
494#define s3 $19
495#define s4 $20
496#define s5 $21
497#define s6 $22
498#define s7 $23
499#define t8 $24
500#define t9 $25
501#define k0 $26
502#define k1 $27
503#define gp $28
504#define sp $29
505#define fp $30
506#define ra $31
507
508/*
509 * The following registers are used by the AVP environment and
510 * are not part of the normal software definitions.
511 */
512
513#ifdef MIPSAVPENV
514#define repc $25 /* Expected exception PC */
515#define tid $30 /* Current test case address */
516#endif
517
518
519/*
520 *************************************************************************
521 * H A R D W A R E G P R N A M E S *
522 *************************************************************************
523 *
524 * In the AVP environment, several of the `r' names are removed from the
525 * name space because they are used by the kernel for special purposes.
526 * Removing them causes assembly rather than runtime errors for tests that
527 * use the `r' names.
528 *
529 * - r25 (repc) is used as the expected PC on an exception
530 * - r26-r27 (k0, k1) are used in the exception handler
531 * - r30 (tid) is used as the current test address
532 */
533
534#define r0 $0
535#define r1 $1
536#define r2 $2
537#define r3 $3
538#define r4 $4
539#define r5 $5
540#define r6 $6
541#define r7 $7
542#define r8 $8
543#define r9 $9
544#define r10 $10
545#define r11 $11
546#define r12 $12
547#define r13 $13
548#define r14 $14
549#define r15 $15
550#define r16 $16
551#define r17 $17
552#define r18 $18
553#define r19 $19
554#define r20 $20
555#define r21 $21
556#define r22 $22
557#define r23 $23
558#define r24 $24
559#ifdef MIPSAVPENV
560#define r25 r25_unknown
561#define r26 r26_unknown
562#define r27 r27_unknown
563#else
564#define r25 $25
565#define r26 $26
566#define r27 $27
567#endif
568#define r28 $28
569#define r29 $29
570#ifdef MIPSAVPENV
571#define r30 r30_unknown
572#else
573#define r30 $30
574#endif
575#define r31 $31
576
577
578/*
579 *************************************************************************
580 * H A R D W A R E G P R I N D I C E S *
581 *************************************************************************
582 *
583 * These definitions provide the index (number) of the GPR, as opposed
584 * to the assembler register name ($n).
585 */
586
587#define R_r0 0
588#define R_r1 1
589#define R_r2 2
590#define R_r3 3
591#define R_r4 4
592#define R_r5 5
593#define R_r6 6
594#define R_r7 7
595#define R_r8 8
596#define R_r9 9
597#define R_r10 10
598#define R_r11 11
599#define R_r12 12
600#define R_r13 13
601#define R_r14 14
602#define R_r15 15
603#define R_r16 16
604#define R_r17 17
605#define R_r18 18
606#define R_r19 19
607#define R_r20 20
608#define R_r21 21
609#define R_r22 22
610#define R_r23 23
611#define R_r24 24
612#define R_r25 25
613#define R_r26 26
614#define R_r27 27
615#define R_r28 28
616#define R_r29 29
617#define R_r30 30
618#define R_r31 31
619#define R_hi 32 /* Hi register */
620#define R_lo 33 /* Lo register */
621
622
623/*
624 *************************************************************************
625 * S O F T W A R E G P R M A S K S *
626 *************************************************************************
627 *
628 * These definitions provide the bit mask corresponding to the GPR number
629 */
630
631#define M_AT (1<<1)
632#define M_v0 (1<<2)
633#define M_v1 (1<<3)
634#define M_a0 (1<<4)
635#define M_a1 (1<<5)
636#define M_a2 (1<<6)
637#define M_a3 (1<<7)
638#define M_t0 (1<<8)
639#define M_t1 (1<<9)
640#define M_t2 (1<<10)
641#define M_t3 (1<<11)
642#define M_t4 (1<<12)
643#define M_t5 (1<<13)
644#define M_t6 (1<<14)
645#define M_t7 (1<<15)
646#define M_s0 (1<<16)
647#define M_s1 (1<<17)
648#define M_s2 (1<<18)
649#define M_s3 (1<<19)
650#define M_s4 (1<<20)
651#define M_s5 (1<<21)
652#define M_s6 (1<<22)
653#define M_s7 (1<<23)
654#define M_t8 (1<<24)
655#define M_t9 (1<<25)
656#define M_k0 (1<<26)
657#define M_k1 (1<<27)
658#define M_gp (1<<28)
659#define M_sp (1<<29)
660#define M_fp (1<<30)
661#define M_ra (1<<31)
662
663
664/*
665 *************************************************************************
666 * C P 0 R E G I S T E R D E F I N I T I O N S *
667 *************************************************************************
668 * Each register has the following definitions:
669 *
670 * C0_rrr The register number (as a $n value)
671 * R_C0_rrr The register index (as an integer corresponding
672 * to the register number)
673 *
674 * Each field in a register has the following definitions:
675 *
676 * S_rrrfff The shift count required to right-justify
677 * the field. This corresponds to the bit
678 * number of the right-most bit in the field.
679 * M_rrrfff The Mask required to isolate the field.
680 *
681 * Register diagrams included below as comments correspond to the
682 * MIPS32 and MIPS64 architecture specifications. Refer to other
683 * sources for register diagrams for older architectures.
684 */
685
686
687/*
688 ************************************************************************
689 * I N D E X R E G I S T E R ( 0 ) *
690 ************************************************************************
691 *
692 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
693 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
694 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
695 * |P| 0 | Index | Index
696 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
697 */
698
699#define C0_Index $0
700#define R_C0_Index 0
701#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */
702
703#define S_IndexP 31 /* Probe failure (R)*/
704#define M_IndexP (0x1 << S_IndexP)
705
706#define S_IndexIndex 0 /* TLB index (R/W)*/
707#define M_IndexIndex (0x3f << S_IndexIndex)
708
709#define M_Index0Fields 0x7fffffc0
710#define M_IndexRFields 0x80000000
711
712
713/*
714 ************************************************************************
715 * R A N D O M R E G I S T E R ( 1 ) *
716 ************************************************************************
717 *
718 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
719 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
720 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
721 * | 0 | Index | Random
722 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
723 */
724
725#define C0_Random $1
726#define R_C0_Random 1
727#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */
728
729#define S_RandomIndex 0 /* TLB random index (R)*/
730#define M_RandomIndex (0x3f << S_RandomIndex)
731
732#define M_Random0Fields 0xffffffc0
733#define M_RandomRFields 0x0000003f
734
735
736/*
737 ************************************************************************
738 * E N T R Y L O 0 R E G I S T E R ( 2 ) *
739 ************************************************************************
740 *
741 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
742 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
743 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
744 * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0
745 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
746 */
747
748#define C0_EntryLo0 $2
749#define R_C0_EntryLo0 2
750#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */
751
752#define S_EntryLoPFN 6 /* PFN (R/W) */
753#define M_EntryLoPFN (0xffffff << S_EntryLoPFN)
754#define S_EntryLoC 3 /* Coherency attribute (R/W) */
755#define M_EntryLoC (0x7 << S_EntryLoC)
756#define S_EntryLoD 2 /* Dirty (R/W) */
757#define M_EntryLoD (0x1 << S_EntryLoD)
758#define S_EntryLoV 1 /* Valid (R/W) */
759#define M_EntryLoV (0x1 << S_EntryLoV)
760#define S_EntryLoG 0 /* Global (R/W) */
761#define M_EntryLoG (0x1 << S_EntryLoG)
762#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */
763#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */
764#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */
765
766#define M_EntryLo0Fields 0x00000000
767#define M_EntryLoRFields 0xc0000000
768#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000)
769#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000)
770
771/*
772 * Cache attribute values in the C field of EntryLo and the
773 * K0 field of Config
774 */
775#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */
776#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */
777#define K_CacheAttrU 2 /* Uncached */
778#define K_CacheAttrC 3 /* Cacheable */
779#define K_CacheAttrCN 3 /* Cacheable, non-coherent */
780#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */
781#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */
782#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */
783#define K_CacheAttrUA 7 /* Uncached accelerated */
784
785
786/*
787 ************************************************************************
788 * E N T R Y L O 1 R E G I S T E R ( 3 ) *
789 ************************************************************************
790 *
791 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
792 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
793 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
794 * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1
795 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
796 */
797
798#define C0_EntryLo1 $3
799#define R_C0_EntryLo1 3
800#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */
801
802/*
803 * Field definitions are as given for EntryLo0 above
804 */
805
806
807/*
808 ************************************************************************
809 * C O N T E X T R E G I S T E R ( 4 ) *
810 ************************************************************************
811 *
812 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
813 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
814 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
815 * | // PTEBase | BadVPN<31:13> | 0 | Context
816 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
817 */
818
819#define C0_Context $4
820#define R_C0_Context 4
821#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */
822
823#define S_ContextPTEBase 23 /* PTE base (R/W) */
824#define M_ContextPTEBase (0x1ff << S_ContextPTEBase)
825#define S_ContextBadVPN 4 /* BadVPN2 (R) */
826#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN)
827#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */
828#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */
829
830#define M_Context0Fields 0x0000000f
831#define M_ContextRFields 0x007ffff0
832#define M_Context0Fields64 UNS64Const(0x000000000000000f)
833#define M_ContextRFields64 UNS64Const(0x00000000007ffff0)
834
835
836/*
837 ************************************************************************
838 * P A G E M A S K R E G I S T E R ( 5 ) *
839 ************************************************************************
840 *
841 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
842 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
843 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
844 * | 0 | Mask | 0 | PageMask
845 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
846 */
847
848#define C0_PageMask $5
849#define R_C0_PageMask 5 /* Mask (R/W) */
850#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */
851
852#define S_PageMaskMask 13
853#define M_PageMaskMask (0xfff << S_PageMaskMask)
854
855#define M_PageMask0Fields 0xfe001fff
856#define M_PageMaskRFields 0x00000000
857
858/*
859 * Values in the Mask field
860 */
861#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */
862#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */
863#define K_PageMask64K 0x00f
864#define K_PageMask256K 0x03f
865#define K_PageMask1M 0x0ff
866#define K_PageMask4M 0x3ff
867#define K_PageMask16M 0xfff
868
869#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
870#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
871#define M_PageMask64K (K_PageMask64K << S_PageMaskMask)
872#define M_PageMask256K (K_PageMask256K << S_PageMaskMask)
873#define M_PageMask1M (K_PageMask1M << S_PageMaskMask)
874#define M_PageMask4M (K_PageMask4M << S_PageMaskMask)
875#define M_PageMask16M (K_PageMask16M << S_PageMaskMask)
876
877
878/*
879 ************************************************************************
880 * W I R E D R E G I S T E R ( 6 ) *
881 ************************************************************************
882 *
883 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
884 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
885 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
886 * | 0 | Index | Wired
887 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
888 */
889
890#define C0_Wired $6
891#define R_C0_Wired 6
892#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */
893
894#define S_WiredIndex 0 /* TLB wired boundary (R/W) */
895#define M_WiredIndex (0x3f << S_WiredIndex)
896
897#define M_Wired0Fields 0xffffffc0
898#define M_WiredRFields 0x00000000
899
900
901/*
902 ************************************************************************
903 * B A D V A D D R R E G I S T E R ( 8 ) *
904 ************************************************************************
905 *
906 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
907 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
908 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
909 * | // Bad Virtual Address | BadVAddr
910 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
911 */
912
913#define C0_BadVAddr $8
914#define R_C0_BadVAddr 8
915#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
916
917#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */
918
919#define M_BadVAddr0Fields 0x00000000
920#define M_BadVAddrRFields 0xffffffff
921#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000)
922#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff)
923
924/*
925 ************************************************************************
926 * C O U N T R E G I S T E R ( 9 ) *
927 ************************************************************************
928 *
929 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
930 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
931 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
932 * | Count Value | Count
933 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
934 */
935
936#define C0_Count $9
937#define R_C0_Count 9
938#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */
939
940#define M_Count0Fields 0x00000000
941#define M_CountRFields 0x00000000
942
943
944/*
945 ************************************************************************
946 * E N T R Y H I R E G I S T E R ( 1 0 ) *
947 ************************************************************************
948 *
949 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
950 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
951 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
952 * | R | Fill // VPN2 | 0 | ASID | EntryHi
953 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
954 */
955
956#define C0_EntryHi $10
957#define R_C0_EntryHi 10
958#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */
959
960#define S_EntryHiR64 62 /* Region (R/W) */
961#define M_EntryHiR64 UNS64Const(0xc000000000000000)
962#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */
963#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2)
964#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000)
965#define S_EntryHiASID 0 /* ASID (R/W) */
966#define M_EntryHiASID (0xff << S_EntryHiASID)
967#define S_EntryHiVPN_Shf S_EntryHiVPN2
968
969#define M_EntryHi0Fields 0x00001f00
970#define M_EntryHiRFields 0x00000000
971#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00)
972#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000)
973
974
975/*
976 ************************************************************************
977 * C O M P A R E R E G I S T E R ( 1 1 ) *
978 ************************************************************************
979 *
980 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
981 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
982 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
983 * | Compare Value | Compare
984 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
985 */
986
987#define C0_Compare $11
988#define R_C0_Compare 11
989#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */
990
991#define M_Compare0Fields 0x00000000
992#define M_CompareRFields 0x00000000
993
994
995/*
996 ************************************************************************
997 * S T A T U S R E G I S T E R ( 1 2 ) *
998 ************************************************************************
999 *
1000 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1001 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1002 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1003 * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I|
1004 * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status
1005 * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| |
1006 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1007 */
1008
1009#define C0_Status $12
1010#define R_C0_Status 12
1011#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */
1012
1013#define S_StatusCU 28 /* Coprocessor enable (R/W) */
1014#define M_StatusCU (0xf << S_StatusCU)
1015#define S_StatusCU3 31
1016#define M_StatusCU3 (0x1 << S_StatusCU3)
1017#define S_StatusCU2 30
1018#define M_StatusCU2 (0x1 << S_StatusCU2)
1019#define S_StatusCU1 29
1020#define M_StatusCU1 (0x1 << S_StatusCU1)
1021#define S_StatusCU0 28
1022#define M_StatusCU0 (0x1 << S_StatusCU0)
1023#define S_StatusRP 27 /* Enable reduced power mode (R/W) */
1024#define M_StatusRP (0x1 << S_StatusRP)
1025#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */
1026#define M_StatusFR (0x1 << S_StatusFR)
1027#define S_StatusRE 25 /* Enable reverse endian (R/W) */
1028#define M_StatusRE (0x1 << S_StatusRE)
1029#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */
1030#define M_StatusMX (0x1 << S_StatusMX)
1031#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
1032#define M_StatusPX (0x1 << S_StatusPX)
1033#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */
1034#define M_StatusBEV (0x1 << S_StatusBEV)
1035#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */
1036#define M_StatusTS (0x1 << S_StatusTS)
1037#define S_StatusSR 20 /* Denote soft reset (R/W) */
1038#define M_StatusSR (0x1 << S_StatusSR)
1039#define S_StatusNMI 19
1040#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */
1041#define S_StatusIM 8 /* Interrupt mask (R/W) */
1042#define M_StatusIM (0xff << S_StatusIM)
1043#define S_StatusIM7 15
1044#define M_StatusIM7 (0x1 << S_StatusIM7)
1045#define S_StatusIM6 14
1046#define M_StatusIM6 (0x1 << S_StatusIM6)
1047#define S_StatusIM5 13
1048#define M_StatusIM5 (0x1 << S_StatusIM5)
1049#define S_StatusIM4 12
1050#define M_StatusIM4 (0x1 << S_StatusIM4)
1051#define S_StatusIM3 11
1052#define M_StatusIM3 (0x1 << S_StatusIM3)
1053#define S_StatusIM2 10
1054#define M_StatusIM2 (0x1 << S_StatusIM2)
1055#define S_StatusIM1 9
1056#define M_StatusIM1 (0x1 << S_StatusIM1)
1057#define S_StatusIM0 8
1058#define M_StatusIM0 (0x1 << S_StatusIM0)
1059#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
1060#define M_StatusKX (0x1 << S_StatusKX)
1061#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
1062#define M_StatusSX (0x1 << S_StatusSX)
1063#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */
1064#define M_StatusUX (0x1 << S_StatusUX)
1065#define S_StatusKSU 3 /* Two-bit current mode (R/W) */
1066#define M_StatusKSU (0x3 << S_StatusKSU)
1067#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */
1068#define M_StatusUM (0x1 << S_StatusUM)
1069#define S_StatusSM 3 /* Supervisor mode (R/W) */
1070#define M_StatusSM (0x1 << S_StatusSM)
1071#define S_StatusERL 2 /* Denotes error level (R/W) */
1072#define M_StatusERL (0x1 << S_StatusERL)
1073#define S_StatusEXL 1 /* Denotes exception level (R/W) */
1074#define M_StatusEXL (0x1 << S_StatusEXL)
1075#define S_StatusIE 0 /* Enables interrupts (R/W) */
1076#define M_StatusIE (0x1 << S_StatusIE)
1077
1078#define M_Status0Fields 0x00040000
1079#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */
1080#define M_Status0Fields64 0x00040000
1081#define M_StatusRFields64 0x00000000
1082
1083/*
1084 * Values in the KSU field
1085 */
1086#define K_StatusKSU_U 2 /* User mode in KSU field */
1087#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */
1088#define K_StatusKSU_K 0 /* Kernel mode in KSU field */
1089
1090#define C0_INTCTL $12,1
1091/*
1092 ************************************************************************
1093 * C A U S E R E G I S T E R ( 1 3 ) *
1094 ************************************************************************
1095 *
1096 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1097 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1098 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1099 * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R |
1100 * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause
1101 * | | | | | | | |7|6|5|4|3|2|1|0| | | v |
1102 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1103 */
1104
1105#define C0_Cause $13
1106#define R_C0_Cause 13
1107#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */
1108
1109#define S_CauseBD 31
1110#define M_CauseBD (0x1 << S_CauseBD)
1111#define S_CauseCE 28
1112#define M_CauseCE (0x3<< S_CauseCE)
1113#define S_CauseIV 23
1114#define M_CauseIV (0x1 << S_CauseIV)
1115#define S_CauseWP 22
1116#define M_CauseWP (0x1 << S_CauseWP)
1117#define S_CauseIP 8
1118#define M_CauseIP (0xff << S_CauseIP)
1119#define S_CauseIPEXT 10
1120#define M_CauseIPEXT (0x3f << S_CauseIPEXT)
1121#define S_CauseIP7 15
1122#define M_CauseIP7 (0x1 << S_CauseIP7)
1123#define S_CauseIP6 14
1124#define M_CauseIP6 (0x1 << S_CauseIP6)
1125#define S_CauseIP5 13
1126#define M_CauseIP5 (0x1 << S_CauseIP5)
1127#define S_CauseIP4 12
1128#define M_CauseIP4 (0x1 << S_CauseIP4)
1129#define S_CauseIP3 11
1130#define M_CauseIP3 (0x1 << S_CauseIP3)
1131#define S_CauseIP2 10
1132#define M_CauseIP2 (0x1 << S_CauseIP2)
1133#define S_CauseIP1 9
1134#define M_CauseIP1 (0x1 << S_CauseIP1)
1135#define S_CauseIP0 8
1136#define M_CauseIP0 (0x1 << S_CauseIP0)
1137#define S_CauseExcCode 2
1138#define M_CauseExcCode (0x1f << S_CauseExcCode)
1139
1140#define M_Cause0Fields 0x4f3f0083
1141#define M_CauseRFields 0xb000fc7c
1142
1143/*
1144 * Values in the CE field
1145 */
1146#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */
1147#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */
1148#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */
1149#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */
1150
1151/*
1152 * Values in the ExcCode field
1153 */
1154#define EX_INT 0 /* Interrupt */
1155#define EXC_INT (EX_INT << S_CauseExcCode)
1156#define EX_MOD 1 /* TLB modified */
1157#define EXC_MOD (EX_MOD << S_CauseExcCode)
1158#define EX_TLBL 2 /* TLB exception (load or ifetch) */
1159#define EXC_TLBL (EX_TLBL << S_CauseExcCode)
1160#define EX_TLBS 3 /* TLB exception (store) */
1161#define EXC_TLBS (EX_TLBS << S_CauseExcCode)
1162#define EX_ADEL 4 /* Address error (load or ifetch) */
1163#define EXC_ADEL (EX_ADEL << S_CauseExcCode)
1164#define EX_ADES 5 /* Address error (store) */
1165#define EXC_ADES (EX_ADES << S_CauseExcCode)
1166#define EX_IBE 6 /* Instruction Bus Error */
1167#define EXC_IBE (EX_IBE << S_CauseExcCode)
1168#define EX_DBE 7 /* Data Bus Error */
1169#define EXC_DBE (EX_DBE << S_CauseExcCode)
1170#define EX_SYS 8 /* Syscall */
1171#define EXC_SYS (EX_SYS << S_CauseExcCode)
1172#define EX_SYSCALL EX_SYS
1173#define EXC_SYSCALL EXC_SYS
1174#define EX_BP 9 /* Breakpoint */
1175#define EXC_BP (EX_BP << S_CauseExcCode)
1176#define EX_BREAK EX_BP
1177#define EXC_BREAK EXC_BP
1178#define EX_RI 10 /* Reserved instruction */
1179#define EXC_RI (EX_RI << S_CauseExcCode)
1180#define EX_CPU 11 /* CoProcessor Unusable */
1181#define EXC_CPU (EX_CPU << S_CauseExcCode)
1182#define EX_OV 12 /* OVerflow */
1183#define EXC_OV (EX_OV << S_CauseExcCode)
1184#define EX_TR 13 /* Trap instruction */
1185#define EXC_TR (EX_TR << S_CauseExcCode)
1186#define EX_TRAP EX_TR
1187#define EXC_TRAP EXC_TR
1188#define EX_FPE 15 /* floating point exception */
1189#define EXC_FPE (EX_FPE << S_CauseExcCode)
1190#define EX_C2E 18 /* COP2 exception */
1191#define EXC_C2E (EX_C2E << S_CauseExcCode)
1192#define EX_MDMX 22 /* MDMX exception */
1193#define EXC_MDMX (EX_MDMX << S_CauseExcCode)
1194#define EX_WATCH 23 /* Watch exception */
1195#define EXC_WATCH (EX_WATCH << S_CauseExcCode)
1196#define EX_MCHECK 24 /* Machine check exception */
1197#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode)
1198#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */
1199#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode)
1200
1201
1202/*
1203 ************************************************************************
1204 * E P C R E G I S T E R ( 1 4 ) *
1205 ************************************************************************
1206 *
1207 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1208 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1209 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1210 * | // Exception PC | EPC
1211 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1212 */
1213
1214#define C0_EPC $14
1215#define R_C0_EPC 14
1216
1217#define M_EPC0Fields 0x00000000
1218#define M_EPCRFields 0x00000000
1219#define M_EPC0Fields64 UNS64Const(0x0000000000000000)
1220#define M_EPCRFields64 UNS64Const(0x0000000000000000)
1221
1222/*
1223 ************************************************************************
1224 * P R I D R E G I S T E R ( 1 5 ) *
1225 ************************************************************************
1226 *
1227 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1228 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1229 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1230 * | Company Opts | Company ID | Procesor ID | Revision | PRId
1231 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1232 */
1233
1234#define C0_PRId $15
1235#define R_C0_PRId 15
1236#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */
1237
1238#define S_PRIdCoOpt 24 /* Company options (R) */
1239#define M_PRIdCoOpt (0xff << S_PRIdCoOpt)
1240#define S_PRIdCoID 16 /* Company ID (R) */
1241#define M_PRIdCoID (0xff << S_PRIdCoID)
1242#define S_PRIdImp 8 /* Implementation ID (R) */
1243#define M_PRIdImp (0xff << S_PRIdImp)
1244#define S_PRIdRev 0 /* Revision (R) */
1245#define M_PRIdRev (0xff << S_PRIdRev)
1246
1247#define M_PRId0Fields 0x00000000
1248#define M_PRIdRFields 0xffffffff
1249/*
1250 * Values in the Company ID field
1251 */
1252#define K_PRIdCoID_MIPS 1
1253#define K_PRIdCoID_Broadcom 2
1254#define K_PRIdCoID_Alchemy 3
1255#define K_PRIdCoID_SiByte 4
1256#define K_PRIdCoID_SandCraft 5
1257#define K_PRIdCoID_Philips 6
1258#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */
1259
1260
1261/*
1262 * Values in the implementation number field
1263 */
1264#define K_PRIdImp_Jade 0x80
1265#define K_PRIdImp_Opal 0x81
1266#define K_PRIdImp_Ruby 0x82
1267#define K_PRIdImp_JadeLite 0x83
1268#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */
1269#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */
1270#define K_PRIdImp_4KSc 0x86 /* Coral */
1271
1272#define K_PRIdImp_R3000 0x01
1273#define K_PRIdImp_R4000 0x04
1274#define K_PRIdImp_R10000 0x09
1275#define K_PRIdImp_R4300 0x0b
1276#define K_PRIdImp_R5000 0x23
1277#define K_PRIdImp_R5200 0x28
1278#define K_PRIdImp_R5400 0x54
1279
1280#define C0_EBase $15,1
1281#define C0_EBASE C0_EBase
1282/*
1283 ************************************************************************
1284 * C O N F I G R E G I S T E R ( 1 6 ) *
1285 ************************************************************************
1286 *
1287 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1288 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1289 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1290 * |M| |B| A | A | | K | Config
1291 * | | Reserved for Implementations|E| T | R | Reserved | 0 |
1292 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1293 */
1294
1295#define C0_Config $16
1296#define R_C0_Config 16
1297#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */
1298
1299#define S_ConfigMore 31 /* Additional config registers present (R) */
1300#define M_ConfigMore (0x1 << S_ConfigMore)
1301#define S_ConfigImpl 16 /* Implementation-specific fields */
1302#define M_ConfigImpl (0x7fff << S_ConfigImpl)
1303#define S_ConfigBE 15 /* Denotes big-endian operation (R) */
1304#define M_ConfigBE (0x1 << S_ConfigBE)
1305#define S_ConfigAT 13 /* Architecture type (R) */
1306#define M_ConfigAT (0x3 << S_ConfigAT)
1307#define S_ConfigAR 10 /* Architecture revision (R) */
1308#define M_ConfigAR (0x7 << S_ConfigAR)
1309#define S_ConfigMT 7 /* MMU Type (R) */
1310#define M_ConfigMT (0x7 << S_ConfigMT)
1311#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */
1312#define M_ConfigK0 (0x7 << S_ConfigK0)
1313
1314/*
1315 * The following definitions are technically part of the "reserved for
1316 * implementations" field, but are the semi-standard definition used in
1317 * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3
1318 * references. For that reason, they are included here, but may be
1319 * overridden by true implementation-specific definitions
1320 */
1321#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
1322#define M_ConfigK23 (0x7 << S_ConfigK23)
1323#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */
1324#define M_ConfigKU (0x7 << S_ConfigKU)
1325
1326#define M_Config0Fields 0x00000078
1327#define M_ConfigRFields 0x8000ff80
1328
1329/*
1330 * Values in the AT field
1331 */
1332#define K_ConfigAT_MIPS32 0 /* MIPS32 */
1333#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */
1334#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */
1335
1336/*
1337 * Values in the MT field
1338 */
1339#define K_ConfigMT_NoMMU 0 /* No MMU */
1340#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */
1341#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */
1342#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */
1343
1344
1345/*
1346 ************************************************************************
1347 * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
1348 ************************************************************************
1349 *
1350 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1351 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1352 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1353 * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1
1354 * | | | | | | | | |2|D|C|R|A|P|P|
1355 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1356 */
1357
1358#define C0_Config1 $16,1
1359#define R_C0_Config1 16
1360
1361#define S_Config1More 31 /* Additional Config registers present (R) */
1362#define M_Config1More (0x1 << S_Config1More)
1363#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */
1364#define M_Config1MMUSize (0x3f << S_Config1MMUSize)
1365#define S_Config1IS 22 /* Icache sets per way (R) */
1366#define M_Config1IS (0x7 << S_Config1IS)
1367#define S_Config1IL 19 /* Icache line size (R) */
1368#define M_Config1IL (0x7 << S_Config1IL)
1369#define S_Config1IA 16 /* Icache associativity - 1 (R) */
1370#define M_Config1IA (0x7 << S_Config1IA)
1371#define S_Config1DS 13 /* Dcache sets per way (R) */
1372#define M_Config1DS (0x7 << S_Config1DS)
1373#define S_Config1DL 10 /* Dcache line size (R) */
1374#define M_Config1DL (0x7 << S_Config1DL)
1375#define S_Config1DA 7 /* Dcache associativity (R) */
1376#define M_Config1DA (0x7 << S_Config1DA)
1377#define S_Config1C2 6 /* Coprocessor 2 present (R) */
1378#define M_Config1C2 (0x1 << S_Config1C2)
1379#define S_Config1MD 5 /* Denotes MDMX present (R) */
1380#define M_Config1MD (0x1 << S_Config1MD)
1381#define S_Config1PC 4 /* Denotes performance counters present (R) */
1382#define M_Config1PC (0x1 << S_Config1PC)
1383#define S_Config1WR 3 /* Denotes watch registers present (R) */
1384#define M_Config1WR (0x1 << S_Config1WR)
1385#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */
1386#define M_Config1CA (0x1 << S_Config1CA)
1387#define S_Config1EP 1 /* Denotes EJTAG present (R) */
1388#define M_Config1EP (0x1 << S_Config1EP)
1389#define S_Config1FP 0 /* Denotes floating point present (R) */
1390#define M_Config1FP (0x1 << S_Config1FP)
1391
1392#define M_Config10Fields 0x00000060
1393#define M_Config1RFields 0x7fffff9f
1394
1395/*
1396 * The following macro generates a table that is indexed
1397 * by the Icache or Dcache sets field in Config1 and
1398 * contains the decoded value of sets per way
1399 */
1400#define Config1CacheSets() \
1401 HALF(64); \
1402 HALF(128); \
1403 HALF(256); \
1404 HALF(512); \
1405 HALF(1024); \
1406 HALF(2048); \
1407 HALF(4096); \
1408 HALF(8192);
1409
1410/*
1411 * The following macro generates a table that is indexed
1412 * by the Icache or Dcache line size field in Config1 and
1413 * contains the decoded value of the cache line size, in bytes
1414 */
1415#define Config1CacheLineSize() \
1416 HALF(0); \
1417 HALF(4); \
1418 HALF(8); \
1419 HALF(16); \
1420 HALF(32); \
1421 HALF(64); \
1422 HALF(128); \
1423 HALF(256);
1424
1425
1426/*
1427 ************************************************************************
1428 * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
1429 ************************************************************************
1430 *
1431 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1432 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1433 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1434 * |M| | | | | | | | | | | | |S|T| Config1
1435 * | | | | | | | | | | | | | |M|L|
1436 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1437 */
1438
1439#define C0_Config2 $16,2
1440#define R_C0_Config2 16
1441
1442#define S_Config2More 31 /* Additional Config registers present (R) */
1443#define M_Config2More (0x1 << S_Config2More)
1444#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */
1445#define M_Config2SM (0x1 << S_Config2SM)
1446#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */
1447#define M_Config2TL (0x1 << S_Config2TL)
1448
1449#define M_Config20Fields 0xfffffffc
1450#define M_Config2RFields 0x00000003
1451
1452/*
1453 ************************************************************************
1454 * L L A D D R R E G I S T E R ( 1 7 ) *
1455 ************************************************************************
1456 *
1457 * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1458 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1459 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1460 * | // LL Physical Address | LLAddr
1461 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1462 */
1463
1464#define C0_LLAddr $17
1465#define R_C0_LLAddr 17
1466#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
1467
1468#define M_LLAddr0Fields 0x00000000
1469#define M_LLAddrRFields 0x00000000
1470#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000)
1471#define M_LLAddrRFields64 UNS64Const(0x0000000000000000)
1472
1473
1474/*
1475 ************************************************************************
1476 * W A T C H L O R E G I S T E R ( 1 8 ) *
1477 ************************************************************************
1478 *
1479 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1480 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1481 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1482 * | // Watch Virtual Address |I|R|W| WatchLo
1483 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1484 */
1485
1486#define C0_WatchLo $18
1487#define R_C0_WatchLo 18
1488#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */
1489
1490#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */
1491#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr)
1492#define S_WatchLoI 2 /* Enable Istream watch (R/W) */
1493#define M_WatchLoI (0x1 << S_WatchLoI)
1494#define S_WatchLoR 1 /* Enable data read watch (R/W) */
1495#define M_WatchLoR (0x1 << S_WatchLoR)
1496#define S_WatchLoW 0 /* Enable data write watch (R/W) */
1497#define M_WatchLoW (0x1 << S_WatchLoW)
1498
1499#define M_WatchLo0Fields 0x00000000
1500#define M_WatchLoRFields 0x00000000
1501#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000)
1502#define M_WatchLoRFields64 UNS64Const(0x0000000000000000)
1503
1504#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW)
1505
1506
1507/*
1508 ************************************************************************
1509 * W A T C H H I R E G I S T E R ( 1 9 ) *
1510 ************************************************************************
1511 *
1512 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1513 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1514 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1515 * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi
1516 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1517 */
1518
1519#define C0_WatchHi $19
1520#define R_C0_WatchHi 19
1521#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */
1522
1523#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */
1524#define M_WatchHiM (0x1 << S_WatchHiM)
1525#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */
1526#define M_WatchHiG (0x1 << S_WatchHiG)
1527#define S_WatchHiASID 16 /* ASID value to match (R/W) */
1528#define M_WatchHiASID (0xff << S_WatchHiASID)
1529#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */
1530#define M_WatchHiMask (0x1ff << S_WatchHiMask)
1531
1532#define M_WatchHi0Fields 0x3f00f007
1533#define M_WatchHiRFields 0x80000000
1534
1535
1536/*
1537 ************************************************************************
1538 * X C O N T E X T R E G I S T E R ( 2 0 ) *
1539 ************************************************************************
1540 *
1541 * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1542 * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1543 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1544 * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext
1545 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1546 */
1547
1548#define C0_XContext $20
1549#define R_C0_XContext 20
1550#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */
1551
1552#define S_XContextBadVPN2 4 /* BadVPN2 (R) */
1553#define S_XContextBadVPN S_XContextBadVPN2
1554
1555#define M_XContext0Fields 0x0000000f
1556
1557
1558/*
1559 ************************************************************************
1560 * D E B U G R E G I S T E R ( 2 3 ) *
1561 ************************************************************************
1562 *
1563 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1564 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1565 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1566 * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D|
1567 * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S|
1568 * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S|
1569 * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug
1570 * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | |
1571 * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | |
1572 * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | |
1573 * | | | | | | | | | | | | |r|r| | | | | | | | | | | |
1574 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1575 */
1576
1577#define C0_Debug $23 /* EJTAG */
1578#define R_C0_Debug 23
1579
1580#define S_DebugDBD 31 /* Debug branch delay (R) */
1581#define M_DebugDBD (0x1 << S_DebugDBD)
1582#define S_DebugDM 30 /* Debug mode (R) */
1583#define M_DebugDM (0x1 << S_DebugDM)
1584#define S_DebugNoDCR 29 /* No debug control register present (R) */
1585#define M_DebugNoDCR (0x1 << S_DebugNoDCR)
1586#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */
1587#define M_DebugLSNM (0x1 << S_DebugLSNM)
1588#define S_DebugDoze 27 /* Doze (R) */
1589#define M_DebugDoze (0x1 << S_DebugDoze)
1590#define S_DebugHalt 26 /* Halt (R) */
1591#define M_DebugHalt (0x1 << S_DebugHalt)
1592#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */
1593#define M_DebugCountDM (0x1 << S_DebugCountDM)
1594#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */
1595#define M_DebugIBusEP (0x1 << S_DebugIBusEP)
1596#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */
1597#define M_DebugMCheckP (0x1 << S_DebugMCheckP)
1598#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */
1599#define M_DebugCacheEP (0x1 << S_DebugCacheEP)
1600#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */
1601#define M_DebugDBusEP (0x1 << S_DebugDBusEP)
1602#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */
1603#define M_DebugIEXI (0x1 << S_DebugIEXI)
1604#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */
1605#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr)
1606#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */
1607#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr)
1608#define S_DebugEJTAGver 15 /* EJTAG version number (R) */
1609#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver)
1610#define S_DebugDExcCode 10 /* Debug exception code (R) */
1611#define M_DebugDExcCode (0x1f << S_DebugDExcCode)
1612#define S_DebugNoSSt 9 /* No single step implemented (R) */
1613#define M_DebugNoSSt (0x1 << S_DebugNoSSt)
1614#define S_DebugSSt 8 /* Single step enable (R/W) */
1615#define M_DebugSSt (0x1 << S_DebugSSt)
1616#define S_DebugDINT 5 /* Debug interrupt (R) */
1617#define M_DebugDINT (0x1 << S_DebugDINT)
1618#define S_DebugDIB 4 /* Debug instruction break (R) */
1619#define M_DebugDIB (0x1 << S_DebugDIB)
1620#define S_DebugDDBS 3 /* Debug data break store (R) */
1621#define M_DebugDDBS (0x1 << S_DebugDDBS)
1622#define S_DebugDDBL 2 /* Debug data break load (R) */
1623#define M_DebugDDBL (0x1 << S_DebugDDBL)
1624#define S_DebugDBp 1 /* Debug breakpoint (R) */
1625#define M_DebugDBp (0x1 << S_DebugDBp)
1626#define S_DebugDSS 0 /* Debug single step (R) */
1627#define M_DebugDSS (0x1 << S_DebugDSS)
1628
1629#define M_Debug0Fields 0x01f000c0
1630#define M_DebugRFields 0xec0ffe3f
1631
1632
1633/*
1634 ************************************************************************
1635 * D E P C R E G I S T E R ( 2 4 ) *
1636 ************************************************************************
1637 *
1638 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1639 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1640 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1641 * | // EJTAG Debug Exception PC | DEPC
1642 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1643 */
1644
1645
1646#define C0_DEPC $24
1647#define R_C0_DEPC 24
1648
1649#define M_DEEPC0Fields 0x00000000
1650#define M_DEEPCRFields 0x00000000
1651#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000)
1652#define M_DEEPCRFields64 UNS64Const(0x0000000000000000)
1653
1654
1655/*
1656 ************************************************************************
1657 * P E R F C N T R E G I S T E R ( 2 5 ) *
1658 ************************************************************************
1659 *
1660 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1661 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1662 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1663 * | | | |I| | | |E|
1664 * |M| 0 | Event |E|U|S|K|X| PerfCnt
1665 * | | | | | | | |L|
1666 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1667 *
1668 *
1669 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1670 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1671 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1672 * | Event Count | PerfCnt
1673 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1674 */
1675
1676#define C0_PerfCnt $25
1677#define R_C0_PerfCnt 25
1678#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
1679#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
1680
1681#define S_PerfCntM 31 /* More performance counters exist (R) */
1682#define M_PerfCntM (1 << S_PerfCntM)
1683#define S_PerfCntEvent 5 /* Enabled event (R/W) */
1684#define M_PerfCntEvent (0x3f << S_PerfCntEvent)
1685#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */
1686#define M_PerfCntIE (1 << S_PerfCntIE)
1687#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */
1688#define M_PerfCntU (1 << S_PerfCntU)
1689#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */
1690#define M_PerfCntS (1 << S_PerfCntS)
1691#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */
1692#define M_PerfCntK (1 << S_PerfCntK)
1693#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */
1694#define M_PerfCntEXL (1 << S_PerfCntEXL)
1695
1696#define M_PerfCnt0Fields 0x7ffff800
1697#define M_PerfCntRFields 0x80000000
1698
1699
1700/*
1701 ************************************************************************
1702 * E R R C T L R E G I S T E R ( 2 6 ) *
1703 ************************************************************************
1704 *
1705 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1706 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1707 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1708 * | Error Control | ErrCtl
1709 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1710 */
1711
1712#define C0_ErrCtl $26
1713#define R_C0_ErrCtl 26
1714#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */
1715#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */
1716
1717#define M_ErrCtl0Fields 0x00000000
1718#define M_ErrCtlRFields 0x00000000
1719
1720
1721/*
1722 ************************************************************************
1723 * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr
1724 ************************************************************************
1725 *
1726 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1727 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1728 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1729 * | Cache Error Control | CacheErr
1730 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1731 */
1732
1733#define C0_CacheErr $27
1734#define R_C0_CacheErr 27
1735#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */
1736
1737#define M_CacheErr0Fields 0x00000000
1738#define M_CachErrRFields 0x00000000
1739
1740
1741/*
1742 ************************************************************************
1743 * T A G L O R E G I S T E R ( 2 8 ) * TagLo
1744 ************************************************************************
1745 *
1746 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1747 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1748 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1749 * | TagLo | TagLo
1750 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1751 */
1752
1753#define C0_TagLo $28
1754#define R_C0_TagLo 28
1755#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */
1756
1757/*
1758 * Some implementations use separate TagLo registers for the
1759 * instruction and data caches. In those cases, the following
1760 * definitions can be used in relevant code
1761 */
1762
1763#define C0_ITagLo $28,0
1764#define C0_DTagLo $28,2
1765
1766#define M_TagLo0Fields 0x00000000
1767#define M_TagLoRFields 0x00000000
1768
1769
1770/*
1771 ************************************************************************
1772 * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo
1773 ************************************************************************
1774 *
1775 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1776 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1777 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1778 * | DataLo | DataLo
1779 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1780 */
1781
1782#define C0_DataLo $28,1
1783#define R_C0_DataLo 28
1784
1785/*
1786 * Some implementations use separate DataLo registers for the
1787 * instruction and data caches. In those cases, the following
1788 * definitions can be used in relevant code
1789 */
1790
1791#define C0_IDataLo $28,1
1792#define C0_DDataLo $28,3
1793
1794#define M_DataLo0Fields 0x00000000
1795#define M_DataLoRFields 0xffffffff
1796
1797
1798/*
1799 ************************************************************************
1800 * T A G H I R E G I S T E R ( 2 9 ) * TagHi
1801 ************************************************************************
1802 *
1803 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1804 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1805 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1806 * | TagHi | TagHi
1807 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1808 */
1809
1810#define C0_TagHi $29
1811#define R_C0_TagHi 29
1812#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */
1813
1814/*
1815 * Some implementations use separate TagHi registers for the
1816 * instruction and data caches. In those cases, the following
1817 * definitions can be used in relevant code
1818 */
1819
1820#define C0_ITagHi $29,0
1821#define C0_DTagHi $29,2
1822
1823#define M_TagHi0Fields 0x00000000
1824#define M_TagHiRFields 0x00000000
1825
1826
1827/*
1828 ************************************************************************
1829 * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi
1830 ************************************************************************
1831 *
1832 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1833 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1834 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1835 * | DataHi | DataHi
1836 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1837 */
1838
1839#define C0_DataHi $29,1
1840#define R_C0_DataHi 29
1841
1842/*
1843 * Some implementations use separate DataHi registers for the
1844 * instruction and data caches. In those cases, the following
1845 * definitions can be used in relevant code
1846 */
1847
1848#define C0_IDataHi $29,1
1849#define C0_DDataHi $29,3
1850
1851#define M_DataHi0Fields 0x00000000
1852#define M_DataHiRFields 0xffffffff
1853
1854
1855/*
1856 ************************************************************************
1857 * E R R O R E P C R E G I S T E R ( 3 0 ) *
1858 ************************************************************************
1859 *
1860 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1861 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1862 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1863 * | // Error PC | ErrorEPC
1864 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1865 */
1866
1867#define C0_ErrorEPC $30
1868#define R_C0_ErrorEPC 30
1869#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */
1870
1871#define M_ErrorEPC0Fields 0x00000000
1872#define M_ErrorEPCRFields 0x00000000
1873#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000)
1874#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000)
1875
1876
1877/*
1878 ************************************************************************
1879 * D E S A V E R E G I S T E R ( 3 1 ) *
1880 ************************************************************************
1881 *
1882 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1883 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1884 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1885 * | // EJTAG Register Save Value | DESAVE
1886 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1887 */
1888
1889#define C0_DESAVE $31
1890#define R_C0_DESAVE 31
1891
1892#define M_DESAVE0Fields 0x00000000
1893#define M_DESAVERFields 0x00000000
1894#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000)
1895#define M_DESAVERFields64 UNS64Const(0x0000000000000000)
1896
1897
1898/*
1899 *************************************************************************
1900 * C P 1 R E G I S T E R D E F I N I T I O N S *
1901 *************************************************************************
1902 */
1903
1904
1905/*
1906 *************************************************************************
1907 * H A R D W A R E F P R N A M E S *
1908 *************************************************************************
1909 */
1910
1911#define fp0 $f0
1912#define fp1 $f1
1913#define fp2 $f2
1914#define fp3 $f3
1915#define fp4 $f4
1916#define fp5 $f5
1917#define fp6 $f6
1918#define fp7 $f7
1919#define fp8 $f8
1920#define fp9 $f9
1921#define fp10 $f10
1922#define fp11 $f11
1923#define fp12 $f12
1924#define fp13 $f13
1925#define fp14 $f14
1926#define fp15 $f15
1927#define fp16 $f16
1928#define fp17 $f17
1929#define fp18 $f18
1930#define fp19 $f19
1931#define fp20 $f20
1932#define fp21 $f21
1933#define fp22 $f22
1934#define fp23 $f23
1935#define fp24 $f24
1936#define fp25 $f25
1937#define fp26 $f26
1938#define fp27 $f27
1939#define fp28 $f28
1940#define fp29 $f29
1941#define fp30 $f30
1942#define fp31 $f31
1943
1944/*
1945 * The following definitions are used to convert an FPR name
1946 * into the corresponding even or odd name, respectively.
1947 * This is used in macro substitution in the AVPs.
1948 */
1949
1950#define fp1_even $f0
1951#define fp3_even $f2
1952#define fp5_even $f4
1953#define fp7_even $f6
1954#define fp9_even $f8
1955#define fp11_even $f10
1956#define fp13_even $f12
1957#define fp15_even $f14
1958#define fp17_even $f16
1959#define fp19_even $f18
1960#define fp21_even $f20
1961#define fp23_even $f22
1962#define fp25_even $f24
1963#define fp27_even $f26
1964#define fp29_even $f28
1965#define fp31_even $f30
1966
1967#define fp0_odd $f1
1968#define fp2_odd $f3
1969#define fp4_odd $f5
1970#define fp6_odd $f7
1971#define fp8_odd $f9
1972#define fp10_odd $f11
1973#define fp12_odd $f13
1974#define fp14_odd $f15
1975#define fp16_odd $f17
1976#define fp18_odd $f19
1977#define fp20_odd $f21
1978#define fp22_odd $f23
1979#define fp24_odd $f25
1980#define fp26_odd $f27
1981#define fp28_odd $f29
1982#define fp30_odd $f31
1983
1984
1985/*
1986 *************************************************************************
1987 * H A R D W A R E F P R I N D I C E S *
1988 *************************************************************************
1989 *
1990 * These definitions provide the index (number) of the FPR, as opposed
1991 * to the assembler register name ($n).
1992 */
1993
1994#define R_fp0 0
1995#define R_fp1 1
1996#define R_fp2 2
1997#define R_fp3 3
1998#define R_fp4 4
1999#define R_fp5 5
2000#define R_fp6 6
2001#define R_fp7 7
2002#define R_fp8 8
2003#define R_fp9 9
2004#define R_fp10 10
2005#define R_fp11 11
2006#define R_fp12 12
2007#define R_fp13 13
2008#define R_fp14 14
2009#define R_fp15 15
2010#define R_fp16 16
2011#define R_fp17 17
2012#define R_fp18 18
2013#define R_fp19 19
2014#define R_fp20 20
2015#define R_fp21 21
2016#define R_fp22 22
2017#define R_fp23 23
2018#define R_fp24 24
2019#define R_fp25 25
2020#define R_fp26 26
2021#define R_fp27 27
2022#define R_fp28 28
2023#define R_fp29 29
2024#define R_fp30 30
2025#define R_fp31 31
2026
2027
2028/*
2029 *************************************************************************
2030 * H A R D W A R E F C R N A M E S *
2031 *************************************************************************
2032 */
2033
2034#define fc0 $0
2035#define fc25 $25
2036#define fc26 $26
2037#define fc28 $28
2038#define fc31 $31
2039
2040
2041/*
2042 *************************************************************************
2043 * H A R D W A R E F C R I N D I C E S *
2044 *************************************************************************
2045 *
2046 * These definitions provide the index (number) of the FCR, as opposed
2047 * to the assembler register name ($n).
2048 */
2049
2050#define R_fc0 0
2051#define R_fc25 25
2052#define R_fc26 26
2053#define R_fc28 28
2054#define R_fc31 31
2055
2056
2057/*
2058 *************************************************************************
2059 * H A R D W A R E F C C N A M E S *
2060 *************************************************************************
2061 */
2062
2063#define cc0 $fcc0
2064#define cc1 $fcc1
2065#define cc2 $fcc2
2066#define cc3 $fcc3
2067#define cc4 $fcc4
2068#define cc5 $fcc5
2069#define cc6 $fcc6
2070#define cc7 $fcc7
2071
2072
2073/*
2074 *************************************************************************
2075 * H A R D W A R E F C C I N D I C E S *
2076 *************************************************************************
2077 *
2078 * These definitions provide the index (number) of the CC, as opposed
2079 * to the assembler register name ($n).
2080 */
2081
2082#define R_cc0 0
2083#define R_cc1 1
2084#define R_cc2 2
2085#define R_cc3 3
2086#define R_cc4 4
2087#define R_cc5 5
2088#define R_cc6 6
2089#define R_cc7 7
2090
2091
2092/*
2093 ************************************************************************
2094 * I M P L E M E N T A T I O N R E G I S T E R *
2095 ************************************************************************
2096 *
2097 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2098 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2099 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2100 * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR
2101 * | Configuration Bits |D|S| | | | |
2102 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2103 */
2104
2105#define C1_FIR $0
2106#define R_C1_FIR 0
2107
2108#define S_FIRConfigS 16
2109#define M_FIRConfigS (0x1 << S_FIRConfigS)
2110#define S_FIRConfigD 17
2111#define M_FIRConfigD (0x1 << S_FIRConfigD)
2112#define S_FIRConfigPS 18
2113#define M_FIRConfigPS (0x1 << S_FIRConfigPS)
2114#define S_FIRConfig3D 19
2115#define M_FIRConfig3D (0x1 << S_FIRConfig3D)
2116#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D)
2117
2118#define S_FIRImp 8
2119#define M_FIRImp (0xff << S_FIRImp)
2120
2121#define S_FIRRev 0
2122#define M_FIRRev (0xff << S_FIRRev)
2123
2124#define M_FIR0Fields 0xfff00000
2125#define M_FIRRFields 0x000fffff
2126
2127/*
2128 ************************************************************************
2129 * C O N D I T I O N C O D E S R E G I S T E R *
2130 ************************************************************************
2131 *
2132 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2133 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2134 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2135 * | 0 | CC | FCCR
2136 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2137 */
2138
2139#define C1_FCCR $25
2140#define R_C1_FCCR 25
2141
2142#define S_FCCRCC 0
2143#define M_FCCRCC (0xff << S_FCCRCC)
2144#define S_FCCRCC7 7
2145#define M_FCCRCC7 (0x1 << S_FCCRCC7)
2146#define S_FCCRCC6 6
2147#define M_FCCRCC6 (0x1 << S_FCCRCC6)
2148#define S_FCCRCC5 5
2149#define M_FCCRCC5 (0x1 << S_FCCRCC5)
2150#define S_FCCRCC4 4
2151#define M_FCCRCC4 (0x1 << S_FCCRCC4)
2152#define S_FCCRCC3 3
2153#define M_FCCRCC3 (0x1 << S_FCCRCC3)
2154#define S_FCCRCC2 2
2155#define M_FCCRCC2 (0x1 << S_FCCRCC2)
2156#define S_FCCRCC1 1
2157#define M_FCCRCC1 (0x1 << S_FCCRCC1)
2158#define S_FCCRCC0 0
2159#define M_FCCRCC0 (0x1 << S_FCCRCC0)
2160
2161#define M_FCCR0Fields 0xffffff00
2162#define M_FCCRRFields 0x000000ff
2163
2164
2165/*
2166 ************************************************************************
2167 * E X C E P T I O N S R E G I S T E R *
2168 ************************************************************************
2169 *
2170 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2171 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2172 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2173 * | 0 | Cause | 0 | Flags | 0 | FEXR
2174 * | |E|V|Z|O|U|I| |V|Z|O|U|I| |
2175 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2176 */
2177
2178#define C1_FEXR $26
2179#define R_C1_FEXR 26
2180
2181#define S_FEXRExc 12
2182#define M_FEXRExc (0x3f << S_FEXRExc)
2183#define S_FEXRExcE 17
2184#define M_FEXRExcE (0x1 << S_FEXRExcE)
2185#define S_FEXRExcV 16
2186#define M_FEXRExcV (0x1 << S_FEXRExcV)
2187#define S_FEXRExcZ 15
2188#define M_FEXRExcZ (0x1 << S_FEXRExcZ)
2189#define S_FEXRExcO 14
2190#define M_FEXRExcO (0x1 << S_FEXRExcO)
2191#define S_FEXRExcU 13
2192#define M_FEXRExcU (0x1 << S_FEXRExcU)
2193#define S_FEXRExcI 12
2194#define M_FEXRExcI (0x1 << S_FEXRExcI)
2195
2196#define S_FEXRFlg 2
2197#define M_FEXRFlg (0x1f << S_FEXRFlg)
2198#define S_FEXRFlgV 6
2199#define M_FEXRFlgV (0x1 << S_FEXRFlgV)
2200#define S_FEXRFlgZ 5
2201#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ)
2202#define S_FEXRFlgO 4
2203#define M_FEXRFlgO (0x1 << S_FEXRFlgO)
2204#define S_FEXRFlgU 3
2205#define M_FEXRFlgU (0x1 << S_FEXRFlgU)
2206#define S_FEXRFlgI 2
2207#define M_FEXRFlgI (0x1 << S_FEXRFlgI)
2208
2209#define M_FEXR0Fields 0xfffc0f83
2210#define M_FEXRRFields 0x00000000
2211
2212
2213/*
2214 ************************************************************************
2215 * E N A B L E S R E G I S T E R *
2216 ************************************************************************
2217 *
2218 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2219 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2220 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2221 * | 0 | Enables | 0 |F|RM | FENR
2222 * | |V|Z|O|U|I| |S| |
2223 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2224 */
2225
2226#define C1_FENR $28
2227#define R_C1_FENR 28
2228
2229#define S_FENREna 7
2230#define M_FENREna (0x1f << S_FENREna)
2231#define S_FENREnaV 11
2232#define M_FENREnaV (0x1 << S_FENREnaV)
2233#define S_FENREnaZ 10
2234#define M_FENREnaZ (0x1 << S_FENREnaZ)
2235#define S_FENREnaO 9
2236#define M_FENREnaO (0x1 << S_FENREnaO)
2237#define S_FENREnaU 8
2238#define M_FENREnaU (0x1 << S_FENREnaU)
2239#define S_FENREnaI 7
2240#define M_FENREnaI (0x1 << S_FENREnaI)
2241
2242#define S_FENRFS 2
2243#define M_FENRFS (0x1 << S_FENRFS)
2244
2245#define S_FENRRM 0
2246#define M_FENRRM (0x3 << S_FENRRM)
2247
2248#define M_FENR0Fields 0xfffff078
2249#define M_FENRRFields 0x00000000
2250
2251
2252/*
2253 ************************************************************************
2254 * C O N T R O L / S T A T U S R E G I S T E R *
2255 ************************************************************************
2256 *
2257 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2258 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2259 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2260 * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR
2261 * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| |
2262 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2263 */
2264
2265#define C1_FCSR $31
2266#define R_C1_FCSR 31
2267
2268#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */
2269#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1)
2270#define S_FCSRCC7 31
2271#define M_FCSRCC7 (0x1 << S_FCSRCC7)
2272#define S_FCSRCC6 30
2273#define M_FCSRCC6 (0x1 << S_FCSRCC6)
2274#define S_FCSRCC5 29
2275#define M_FCSRCC5 (0x1 << S_FCSRCC5)
2276#define S_FCSRCC4 28
2277#define M_FCSRCC4 (0x1 << S_FCSRCC4)
2278#define S_FCSRCC3 27
2279#define M_FCSRCC3 (0x1 << S_FCSRCC3)
2280#define S_FCSRCC2 26
2281#define M_FCSRCC2 (0x1 << S_FCSRCC2)
2282#define S_FCSRCC1 25
2283#define M_FCSRCC1 (0x1 << S_FCSRCC1)
2284
2285#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */
2286#define M_FCSRFS (0x1 << S_FCSRFS)
2287
2288#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */
2289#define M_FCSRCC0 (0x1 << S_FCSRCC0)
2290#define S_FCSRCC S_FCSRCC0
2291#define M_FCSRCC M_FCSRCC0
2292
2293#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */
2294#define M_FCSRImpl (0x3 << S_FCSRImpl)
2295
2296#define S_FCSRExc 12 /* Exception cause (R/W) */
2297#define M_FCSRExc (0x3f << S_FCSRExc)
2298#define S_FCSRExcE 17
2299#define M_FCSRExcE (0x1 << S_FCSRExcE)
2300#define S_FCSRExcV 16
2301#define M_FCSRExcV (0x1 << S_FCSRExcV)
2302#define S_FCSRExcZ 15
2303#define M_FCSRExcZ (0x1 << S_FCSRExcZ)
2304#define S_FCSRExcO 14
2305#define M_FCSRExcO (0x1 << S_FCSRExcO)
2306#define S_FCSRExcU 13
2307#define M_FCSRExcU (0x1 << S_FCSRExcU)
2308#define S_FCSRExcI 12
2309#define M_FCSRExcI (0x1 << S_FCSRExcI)
2310
2311#define S_FCSREna 7 /* Exception enable (R/W) */
2312#define M_FCSREna (0x1f << S_FCSREna)
2313#define S_FCSREnaV 11
2314#define M_FCSREnaV (0x1 << S_FCSREnaV)
2315#define S_FCSREnaZ 10
2316#define M_FCSREnaZ (0x1 << S_FCSREnaZ)
2317#define S_FCSREnaO 9
2318#define M_FCSREnaO (0x1 << S_FCSREnaO)
2319#define S_FCSREnaU 8
2320#define M_FCSREnaU (0x1 << S_FCSREnaU)
2321#define S_FCSREnaI 7
2322#define M_FCSREnaI (0x1 << S_FCSREnaI)
2323
2324#define S_FCSRFlg 2 /* Exception flags (R/W) */
2325#define M_FCSRFlg (0x1f << S_FCSRFlg)
2326#define S_FCSRFlgV 6
2327#define M_FCSRFlgV (0x1 << S_FCSRFlgV)
2328#define S_FCSRFlgZ 5
2329#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ)
2330#define S_FCSRFlgO 4
2331#define M_FCSRFlgO (0x1 << S_FCSRFlgO)
2332#define S_FCSRFlgU 3
2333#define M_FCSRFlgU (0x1 << S_FCSRFlgU)
2334#define S_FCSRFlgI 2
2335#define M_FCSRFlgI (0x1 << S_FCSRFlgI)
2336
2337#define S_FCSRRM 0 /* Rounding mode (R/W) */
2338#define M_FCSRRM (0x3 << S_FCSRRM)
2339
2340#define M_FCSR0Fields 0x001c0000
2341#define M_FCSRRFields 0x00000000
2342
2343/*
2344 * Values in the rounding mode field (of both FCSR and FCCR)
2345 */
2346#define K_FCSRRM_RN 0
2347#define K_FCSRRM_RZ 1
2348#define K_FCSRRM_RP 2
2349#define K_FCSRRM_RM 3
2350
2351
2352/* ********************************************************************* */
2353/* Interface function definition */
2354
2355
2356/* ********************************************************************* */
2357
2358#endif /* __ARCHDEFS_H__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-23 21:32:53 +0000