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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2017-01-17 22:54:13 +0100 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2017-01-24 15:34:19 +0100 |
| commit | f3cce72269703e983e4a4e6ec8dc9217b0c2b6fe (patch) | |
| tree | dc66a06febd287a5f0d146376b69d6a4322d81f1 /utils/hwstub/stub/jz4760b/target-config.h | |
| parent | 07bc348c914f04657b284cb1ace92df8ef3a15d9 (diff) | |
| download | rockbox-f3cce72269703e983e4a4e6ec8dc9217b0c2b6fe.tar.gz rockbox-f3cce72269703e983e4a4e6ec8dc9217b0c2b6fe.zip | |
hwstub/jz460b: implement exception recovery
Now that we now that jz4760b implements EBASE, we can use it to rebase
exceptions to use a k1seg address, that maps to the physical address of the
TCSM0. It requires to enable HAB1 to have this translation. This most the most
inefficient way to access tighly coupled memory ever, but it works.
Change-Id: I894ca929c9835696102eb2fef44b06e6eaf96d44
Diffstat (limited to 'utils/hwstub/stub/jz4760b/target-config.h')
| -rw-r--r-- | utils/hwstub/stub/jz4760b/target-config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/utils/hwstub/stub/jz4760b/target-config.h b/utils/hwstub/stub/jz4760b/target-config.h index 681e17e6f6..5737e0bc87 100644 --- a/utils/hwstub/stub/jz4760b/target-config.h +++ b/utils/hwstub/stub/jz4760b/target-config.h | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | #define CONFIG_JZ4760B | 1 | #define CONFIG_JZ4760B |
| 2 | #define TCSM0_ORIG 0xf4000000 | 2 | #define TCSM0_ORIG 0xf4000000 |
| 3 | #define TCSM0_SIZE 0x4000 | 3 | #define TCSM0_SIZE 0x4000 |
| 4 | #define TCSM0_UNCACHED_ADDRESS 0xb32b0000 | ||
| 4 | #define CPU_MIPS | 5 | #define CPU_MIPS |
| 5 | #define STACK_SIZE 0x300 | 6 | #define STACK_SIZE 0x300 |
| 6 | #define DCACHE_SIZE 0x4000 /* 16 kB */ | 7 | #define DCACHE_SIZE 0x4000 /* 16 kB */ |