hwstub: add the possibility to flush caches before exec

This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h

Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e

1 files changed, 25 insertions, 0 deletions

diff --git a/utils/hwstub/stub/asm/mips/system.S b/utils/hwstub/stub/asm/mips/system.S
index ab134aed48..97b0207ec9 100644
--- a/utils/hwstub/stub/asm/mips/system.S
+++ b/utils/hwstub/stub/asm/mips/system.S
@@ -18,6 +18,7 @@
  *
  ****************************************************************************/
 #include "mips.h"
+#include "target-config.h"
 
 /* Handling of data abort:
  * the code can register a "longjmp" buffer to restore the context in case of
@@ -49,3 +50,27 @@ set_data_abort_jmp:
     jr ra
     move v0, zero
 .set reorder
+
+#ifdef CONFIG_FLUSH_CACHES
+.set noreorder
+.text
+.global target_flush_caches
+target_flush_caches:
+    /* commit dcache and invalidate icache */
+    la      t0, 0x80000000   /* an idx op should use an unmappable address */
+    ori     t1, t0, DCACHE_SIZE   /* cache size */
+reloc_dcache_loop:
+    cache   DCIndexWBInv, 0(t0) /* invalidate and write-back dcache index */
+    addiu   t0, t0, DCACHE_LINE_SIZE /* bytes per cache line */
+    bne     t0, t1, reloc_dcache_loop
+    nop
+    la      t0, 0x80000000   /* an idx op should use an unmappable address */
+    ori     t1, t0, ICACHE_SIZE   /* cache size */
+reloc_icache_loop:
+    cache   ICIndexInv, 0(t0) /* invalidate icache index */
+    addiu   t0, t0, ICACHE_LINE_SIZE  /* bytes per cache line */
+    bne     t0, t1, reloc_icache_loop
+    nop
+    jr      ra
+    nop
+#endif