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authorAmaury Pouly <amaury.pouly@gmail.com>2017-01-18 14:36:27 +0100
committerAmaury Pouly <amaury.pouly@gmail.com>2017-01-24 15:34:19 +0100
commit9bb6050d40b9936beda5cb1cd15040f6c1b07179 (patch)
tree03fa1ad2b5d20db4cae1d8f7b75deb4d98fbdeee /utils/hwstub/stub/asm/arm/system.S
parentf3cce72269703e983e4a4e6ec8dc9217b0c2b6fe (diff)
downloadrockbox-9bb6050d40b9936beda5cb1cd15040f6c1b07179.tar.gz
rockbox-9bb6050d40b9936beda5cb1cd15040f6c1b07179.zip
hwstub: rewrite exception catching
Since we can catch exceptions like data aborts on read/write, it takes very little to also catch exceptions in calls. When extending this with the catching of illegal instructions, the call instruction now becomes much more robust and also for address and instruction probing. Since we can catch several types of exception, rename set_data_abort_jmp to set_exception_jmp. At the same time, simplify the logic in read/write request handlers. Also fix a bug in ARM jump code: it was using stmia r1, {..., pc} as if pc would get current pc + 8 but this is actually implementation defined on older ARMs (typically pc + 12) and deprecated on newer ARMs, so rewrite the code avoid that. The set_exception_jmp() function now also reports the exception type. Change-Id: Icd0dd52d2456b361b27c4776be09c3d13528ed93
Diffstat (limited to 'utils/hwstub/stub/asm/arm/system.S')
-rw-r--r--utils/hwstub/stub/asm/arm/system.S28
1 files changed, 15 insertions, 13 deletions
diff --git a/utils/hwstub/stub/asm/arm/system.S b/utils/hwstub/stub/asm/arm/system.S
index df6b5a2e81..41551a8004 100644
--- a/utils/hwstub/stub/asm/arm/system.S
+++ b/utils/hwstub/stub/asm/arm/system.S
@@ -18,32 +18,33 @@
18 * KIND, either express or implied. 18 * KIND, either express or implied.
19 * 19 *
20 ****************************************************************************/ 20 ****************************************************************************/
21#include "system.h"
21 22
22/* Handling of data abort: 23/* Handling of data abort:
23 * the code can register a "longjmp" buffer to restore the context in case of 24 * the code can register a "longjmp" buffer to restore the context in case of
24 * fault */ 25 * fault */
25.data 26.data
26data_abort_jmp_ctx_ptr: 27exception_jmp_ctx_ptr:
27/* buffer contains in order: cpsr,r4-r11,sp,lr,pc */ 28/* buffer contains in order: cpsr,r4-r11,sp,lr,pc */
28.skip 48 /* = 4 * (cpsr + 11 registers) */ 29.skip 48 /* = 4 * (cpsr + 11 registers) */
29 30
30.text 31.text
31/* Prototype: int set_data_abort_jmp() 32/* Prototype: int set_exception_jmp()
32 * Return: 1 in case of data abort, 0 otherwise */ 33 * Return: !=0 in case of exception, 0 otherwise */
33.global set_data_abort_jmp 34.global set_exception_jmp
34set_data_abort_jmp: 35set_exception_jmp:
35 mrs r2, cpsr 36 mrs r2, cpsr
36 ldr r1, =data_abort_jmp_ctx_ptr 37 ldr r1, =exception_jmp_ctx_ptr
37 mov r0, #0 38 mov r0, #EXCEPTION_NONE /* nothing to report */
38 stmia r1, {r2,r4-r11,sp,lr,pc} /* see PC note below */ 39 stmia r1!, {r2,r4-r11,sp,lr} /* see PC note below */
39 bx lr 40 mov r3, pc /* see note below */
40 mov r0, #1 /* <-- PC points here in stmia */ 41 str r3, [r1] /* store PC */
41 bx lr 42 bx lr /* <-- PC points here in mov */
42 43
43.global data_abort_handler 44.global data_abort_handler
44data_abort_handler: 45data_abort_handler:
45 /* restore everything from context */ 46 /* restore everything from context */
46 ldr r1, =data_abort_jmp_ctx_ptr 47 ldr r1, =exception_jmp_ctx_ptr
47 /* NOTE: we need to restore sp_sys and lr_sys, for this we need the 48 /* NOTE: we need to restore sp_sys and lr_sys, for this we need the
48 * LDM Rn, {}^ 49 * LDM Rn, {}^
49 * variant, but we cannot restore PC from it because ^ has a different 50 * variant, but we cannot restore PC from it because ^ has a different
@@ -54,4 +55,5 @@ data_abort_handler:
54 * because we do not save the abort address and we don't use an abort stack */ 55 * because we do not save the abort address and we don't use an abort stack */
55 ldmia r1, {r0,r4-r11,sp,lr}^ /* this variant cannot have writeback (r1!) */ 56 ldmia r1, {r0,r4-r11,sp,lr}^ /* this variant cannot have writeback (r1!) */
56 msr spsr, r0 57 msr spsr, r0
57 ldmia r1, {r0,r4-r11,sp,lr,pc}^ /* reload some registers but we don't care */ 58 mov r0, #EXCEPTION_ADDR
59 ldmia r1, {r1,r4-r11,sp,lr,pc}^ /* reload some registers but we don't care */