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author | Sean Bartell <wingedtachikoma@gmail.com> | 2011-06-25 21:32:25 -0400 |
---|---|---|
committer | Nils Wallménius <nils@rockbox.org> | 2012-04-25 22:13:20 +0200 |
commit | f40bfc9267b13b54e6379dfe7539447662879d24 (patch) | |
tree | 9b20069d5e62809ff434061ad730096836f916f2 /lib/rbcodec/codecs/libmad/synth_full_arm.S | |
parent | a0009907de7a0107d49040d8a180f140e2eff299 (diff) | |
download | rockbox-f40bfc9267b13b54e6379dfe7539447662879d24.tar.gz rockbox-f40bfc9267b13b54e6379dfe7539447662879d24.zip |
Add codecs to librbcodec.
Change-Id: Id7f4717d51ed02d67cb9f9cb3c0ada4a81843f97
Reviewed-on: http://gerrit.rockbox.org/137
Reviewed-by: Nils Wallménius <nils@rockbox.org>
Tested-by: Nils Wallménius <nils@rockbox.org>
Diffstat (limited to 'lib/rbcodec/codecs/libmad/synth_full_arm.S')
-rw-r--r-- | lib/rbcodec/codecs/libmad/synth_full_arm.S | 340 |
1 files changed, 340 insertions, 0 deletions
diff --git a/lib/rbcodec/codecs/libmad/synth_full_arm.S b/lib/rbcodec/codecs/libmad/synth_full_arm.S new file mode 100644 index 0000000000..0a4f9b93c2 --- /dev/null +++ b/lib/rbcodec/codecs/libmad/synth_full_arm.S | |||
@@ -0,0 +1,340 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2007 by Tomasz Malesinski | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "mad_iram.h" | ||
24 | |||
25 | .section ICODE_SECTION_MPA_ARM,"ax",%progbits | ||
26 | |||
27 | .global synth_full_odd_sbsample | ||
28 | .global synth_full_even_sbsample | ||
29 | |||
30 | /* | ||
31 | ;; r0 = pcm (pushed on the stack to free a register) | ||
32 | ;; r1 = fo | ||
33 | ;; r2 = fe | ||
34 | ;; r3 = D0ptr | ||
35 | ;; r4 = D1ptr | ||
36 | |||
37 | ;; r5 = loop counter | ||
38 | ;; r6,r7 accumulator1 | ||
39 | ;; r8,r9 accumulator2 | ||
40 | */ | ||
41 | |||
42 | synth_full_odd_sbsample: | ||
43 | stmdb sp!, {r0, r4-r11, lr} | ||
44 | ldr r4, [sp, #40] | ||
45 | mov r5, #15 | ||
46 | add r2, r2, #32 | ||
47 | .l: | ||
48 | /* ;; PROD_O and odd half of SB_SAMPLE*/ | ||
49 | add r3, r3, #128 | ||
50 | add r4, r4, #128 | ||
51 | ldr r7, [r3, #4] | ||
52 | ldmia r1!, {r0, r10, r11, lr} | ||
53 | ldr r9, [r4, #120] | ||
54 | smull r6, r7, r0, r7 | ||
55 | ldr r12, [r3, #60] | ||
56 | smull r8, r9, r0, r9 | ||
57 | ldr r0, [r3, #52] | ||
58 | smlal r6, r7, r10, r12 | ||
59 | ldr r12, [r3, #44] | ||
60 | smlal r6, r7, r11, r0 | ||
61 | ldr r0, [r4, #64] | ||
62 | smlal r6, r7, lr, r12 | ||
63 | ldr r12, [r4, #72] | ||
64 | smlal r8, r9, r10, r0 | ||
65 | ldr r0, [r4, #80] | ||
66 | smlal r8, r9, r11, r12 | ||
67 | smlal r8, r9, lr, r0 | ||
68 | ldr r0, [r3, #36] | ||
69 | |||
70 | ldmia r1!, {r10, r11, r12, lr} | ||
71 | smlal r6, r7, r10, r0 | ||
72 | |||
73 | ldr r0, [r4, #88] /*;;1 cycle stall on arm9, but we free up r10*/ | ||
74 | smlal r8, r9, r10, r0 | ||
75 | |||
76 | ldr r0, [r3, #28] | ||
77 | ldr r10, [r3, #20] | ||
78 | smlal r6, r7, r11, r0 | ||
79 | ldr r0, [r3, #12] | ||
80 | smlal r6, r7, r12, r10 | ||
81 | ldr r10, [r4, #96] | ||
82 | smlal r6, r7, lr, r0 | ||
83 | ldr r0, [r4, #104] | ||
84 | smlal r8, r9, r11, r10 | ||
85 | ldr r10, [r4, #112] | ||
86 | smlal r8, r9, r12, r0 | ||
87 | smlal r8, r9, lr, r10 | ||
88 | |||
89 | rsbs r6, r6, #0 | ||
90 | rsc r7, r7, #0 | ||
91 | |||
92 | /* ;; PROD_A and even half of SB_SAMPLE*/ | ||
93 | ldr r0, [r3, #0] | ||
94 | ldmia r2!, {r10, r11, r12, lr} | ||
95 | smlal r6, r7, r10, r0 | ||
96 | |||
97 | ldr r0, [r4, #60] /*;;1 cycle stall on arm9, but we free up r10*/ | ||
98 | smlal r8, r9, r10, r0 | ||
99 | ldr r10, [r3, #56] | ||
100 | ldr r0, [r3, #48] | ||
101 | smlal r6, r7, r11, r10 | ||
102 | ldr r10, [r3, #40] | ||
103 | smlal r6, r7, r12, r0 | ||
104 | ldr r0, [r4, #68] | ||
105 | smlal r6, r7, lr, r10 | ||
106 | ldr r10, [r4, #76] | ||
107 | smlal r8, r9, r11, r0 | ||
108 | ldr r0, [r4, #84] | ||
109 | smlal r8, r9, r12, r10 | ||
110 | smlal r8, r9, lr, r0 | ||
111 | |||
112 | ldr r0, [r3, #32] | ||
113 | ldmia r2!, {r10, r11, r12, lr} | ||
114 | smlal r6, r7, r10, r0 | ||
115 | |||
116 | ldr r0, [r4, #92] /*;;1 cycle stall on arm9, but we free up r10*/ | ||
117 | smlal r8, r9, r10, r0 | ||
118 | |||
119 | ldr r0, [r3, #24] | ||
120 | ldr r10, [r3, #16] | ||
121 | smlal r6, r7, r11, r0 | ||
122 | ldr r0, [r3, #8] | ||
123 | smlal r6, r7, r12, r10 | ||
124 | ldr r10, [r4, #100] | ||
125 | smlal r6, r7, lr, r0 | ||
126 | ldr r0, [r4, #108] | ||
127 | smlal r8, r9, r11, r10 | ||
128 | ldr r10, [r4, #116] | ||
129 | smlal r8, r9, r12, r0 | ||
130 | smlal r8, r9, lr, r10 | ||
131 | |||
132 | ldr r0, [sp] | ||
133 | |||
134 | movs r6, r6, lsr #16 | ||
135 | adc r6, r6, r7, lsl #16 | ||
136 | str r6, [r0, -r5, lsl #2] | ||
137 | |||
138 | movs r8, r8, lsr #16 | ||
139 | adc r8, r8, r9, lsl #16 | ||
140 | str r8, [r0, r5, lsl #2] | ||
141 | |||
142 | subs r5, r5, #1 | ||
143 | bne .l | ||
144 | |||
145 | ldmpc regs="r0,r4-r11" | ||
146 | |||
147 | synth_full_even_sbsample: | ||
148 | stmdb sp!, {r0, r4-r11, lr} | ||
149 | ldr r4, [sp, #40] | ||
150 | mov r5, #15 | ||
151 | add r2, r2, #32 | ||
152 | .l2: | ||
153 | /* ;; PROD_O and odd half of SB_SAMPLE*/ | ||
154 | add r3, r3, #128 | ||
155 | add r4, r4, #128 | ||
156 | ldr r7, [r3, #0] | ||
157 | ldmia r1!, {r0, r10, r11, lr} | ||
158 | ldr r9, [r4, #60] | ||
159 | smull r6, r7, r0, r7 | ||
160 | ldr r12, [r3, #56] | ||
161 | smull r8, r9, r0, r9 | ||
162 | ldr r0, [r3, #48] | ||
163 | smlal r6, r7, r10, r12 | ||
164 | ldr r12, [r3, #40] | ||
165 | smlal r6, r7, r11, r0 | ||
166 | ldr r0, [r4, #68] | ||
167 | smlal r6, r7, lr, r12 | ||
168 | |||
169 | ldr r12, [r4, #76] | ||
170 | smlal r8, r9, r10, r0 | ||
171 | ldr r0, [r4, #84] | ||
172 | smlal r8, r9, r11, r12 | ||
173 | smlal r8, r9, lr, r0 | ||
174 | |||
175 | ldr r0, [r3, #32] | ||
176 | ldmia r1!, {r10, r11, r12, lr} | ||
177 | |||
178 | smlal r6, r7, r10, r0 | ||
179 | ldr r0, [r4, #92] | ||
180 | smlal r8, r9, r10, r0 | ||
181 | ldr r0, [r3, #24] | ||
182 | ldr r10, [r3, #16] | ||
183 | smlal r6, r7, r11, r0 | ||
184 | ldr r0, [r3, #8] | ||
185 | smlal r6, r7, r12, r10 | ||
186 | ldr r10, [r4, #100] | ||
187 | smlal r6, r7, lr, r0 | ||
188 | ldr r0, [r4, #108] | ||
189 | smlal r8, r9, r11, r10 | ||
190 | ldr r10, [r4, #116] | ||
191 | smlal r8, r9, r12, r0 | ||
192 | smlal r8, r9, lr, r10 | ||
193 | |||
194 | rsbs r6, r6, #0 | ||
195 | rsc r7, r7, #0 | ||
196 | |||
197 | ldr r0, [r3, #4] | ||
198 | ldmia r2!, {r10, r11, r12, lr} | ||
199 | smlal r6, r7, r10, r0 | ||
200 | ldr r0, [r4, #120] /*;;1 cycle stall on arm9, but we free up r10*/ | ||
201 | smlal r8, r9, r10, r0 | ||
202 | ldr r0, [r3, #60] | ||
203 | ldr r10, [r3, #52] | ||
204 | smlal r6, r7, r11, r0 | ||
205 | ldr r0, [r3, #44] | ||
206 | smlal r6, r7, r12, r10 | ||
207 | ldr r10, [r4, #64] | ||
208 | smlal r6, r7, lr, r0 | ||
209 | |||
210 | ldr r0, [r4, #72] | ||
211 | smlal r8, r9, r11, r10 | ||
212 | ldr r10, [r4, #80] | ||
213 | smlal r8, r9, r12, r0 | ||
214 | |||
215 | smlal r8, r9, lr, r10 | ||
216 | |||
217 | ldr r0, [r3, #36] | ||
218 | ldmia r2!, {r10, r11, r12, lr} | ||
219 | smlal r6, r7, r10, r0 | ||
220 | ldr r0, [r4, #88] /*;;1 cycle stall on arm9, but we free up r10*/ | ||
221 | smlal r8, r9, r10, r0 | ||
222 | |||
223 | ldr r0, [r3, #28] | ||
224 | ldr r10, [r3, #20] | ||
225 | smlal r6, r7, r11, r0 | ||
226 | ldr r0, [r3, #12] | ||
227 | smlal r6, r7, r12, r10 | ||
228 | ldr r10, [r4, #96] | ||
229 | smlal r6, r7, lr, r0 | ||
230 | ldr r0, [r4, #104] | ||
231 | smlal r8, r9, r11, r10 | ||
232 | ldr r10, [r4, #112] | ||
233 | smlal r8, r9, r12, r0 | ||
234 | smlal r8, r9, lr, r10 | ||
235 | |||
236 | ldr r0, [sp] | ||
237 | |||
238 | movs r6, r6, lsr #16 | ||
239 | adc r6, r6, r7, lsl #16 | ||
240 | str r6, [r0, -r5, lsl #2] | ||
241 | |||
242 | movs r8, r8, lsr #16 | ||
243 | adc r8, r8, r9, lsl #16 | ||
244 | str r8, [r0, r5, lsl #2] | ||
245 | |||
246 | subs r5, r5, #1 | ||
247 | bne .l2 | ||
248 | |||
249 | ldmpc regs="r0,r4-r11" | ||
250 | |||
251 | .global III_aliasreduce | ||
252 | |||
253 | III_aliasreduce: | ||
254 | stmdb sp!, {r4-r11, lr} | ||
255 | add r1, r0, r1, lsl #2 | ||
256 | add r0, r0, #72 | ||
257 | .arl1: | ||
258 | mov r2, #8 | ||
259 | mov r3, r0 @ a | ||
260 | mov r4, r0 @ b | ||
261 | ldr r5, =csa @ cs/ca | ||
262 | .arl2: | ||
263 | ldmdb r3, {r6, r12} | ||
264 | ldmia r4, {r7, lr} | ||
265 | |||
266 | ldmia r5!, {r8, r9} | ||
267 | smull r10, r11, r7, r8 | ||
268 | smlal r10, r11, r12, r9 | ||
269 | movs r10, r10, lsr #28 | ||
270 | adc r10, r10, r11, lsl #4 | ||
271 | |||
272 | rsb r7, r7, #0 | ||
273 | smull r11, r8, r12, r8 | ||
274 | smlal r11, r8, r7, r9 | ||
275 | movs r11, r11, lsr #28 | ||
276 | adc r11, r11, r8, lsl #4 | ||
277 | |||
278 | ldmia r5!, {r8, r9} | ||
279 | smull r12, r7, lr, r8 | ||
280 | smlal r12, r7, r6, r9 | ||
281 | movs r12, r12, lsr #28 | ||
282 | adc r12, r12, r7, lsl #4 | ||
283 | stmia r4!, {r10, r12} | ||
284 | |||
285 | rsb lr, lr, #0 | ||
286 | smull r7, r10, r6, r8 | ||
287 | smlal r7, r10, lr, r9 | ||
288 | movs r7, r7, lsr #28 | ||
289 | adc r7, r7, r10, lsl #4 | ||
290 | stmdb r3!, {r7, r11} | ||
291 | |||
292 | subs r2, r2, #2 | ||
293 | bne .arl2 | ||
294 | add r0, r0, #72 | ||
295 | cmp r0, r1 | ||
296 | blo .arl1 | ||
297 | ldmpc regs=r4-r11 | ||
298 | |||
299 | csa: | ||
300 | .word +0x0db84a81 | ||
301 | .word -0x083b5fe7 | ||
302 | .word +0x0e1b9d7f | ||
303 | .word -0x078c36d2 | ||
304 | .word +0x0f31adcf | ||
305 | .word -0x05039814 | ||
306 | .word +0x0fbba815 | ||
307 | .word -0x02e91dd1 | ||
308 | .word +0x0feda417 | ||
309 | .word -0x0183603a | ||
310 | .word +0x0ffc8fc8 | ||
311 | .word -0x00a7cb87 | ||
312 | .word +0x0fff964c | ||
313 | .word -0x003a2847 | ||
314 | .word +0x0ffff8d3 | ||
315 | .word -0x000f27b4 | ||
316 | |||
317 | .global III_overlap | ||
318 | III_overlap: | ||
319 | stmdb sp!, {r4-r7, lr} | ||
320 | add r2, r2, r3, lsl #2 | ||
321 | mov r3, #6 | ||
322 | .ol: | ||
323 | ldmia r0!, {r4, r5, r6} | ||
324 | ldmia r1!, {r7, r12, lr} | ||
325 | add r4, r4, r7 | ||
326 | add r5, r5, r12 | ||
327 | add r6, r6, lr | ||
328 | str r4, [r2], #128 | ||
329 | str r5, [r2], #128 | ||
330 | str r6, [r2], #128 | ||
331 | subs r3, r3, #1 | ||
332 | bne .ol | ||
333 | sub r1, r1, #72 | ||
334 | ldmia r0!, {r4, r5, r6, r7, r12, lr} | ||
335 | stmia r1!, {r4, r5, r6, r7, r12, lr} | ||
336 | ldmia r0!, {r4, r5, r6, r7, r12, lr} | ||
337 | stmia r1!, {r4, r5, r6, r7, r12, lr} | ||
338 | ldmia r0!, {r4, r5, r6, r7, r12, lr} | ||
339 | stmia r1!, {r4, r5, r6, r7, r12, lr} | ||
340 | ldmpc regs=r4-r7 | ||