diff options
author | Dave Chapman <dave@dchapman.com> | 2009-10-04 15:38:36 +0000 |
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committer | Dave Chapman <dave@dchapman.com> | 2009-10-04 15:38:36 +0000 |
commit | fbf034fcff15bb972c94188d6f58b83fff4529d5 (patch) | |
tree | 3588c424de6dad198ce7ba96a57f622e50bdd8e2 /firmware | |
parent | a7ea270e9c3c181f3f2766860f2245c09a5c9f97 (diff) | |
download | rockbox-fbf034fcff15bb972c94188d6f58b83fff4529d5.tar.gz rockbox-fbf034fcff15bb972c94188d6f58b83fff4529d5.zip |
Another part of FS#10633 by Michael Sparmann - correct cache/protection unit init for the Nano 2G. This should be unified with the Meizu code at some point, but is currently #ifdef'd as it is known (for some as yet unknown reason) to break the Meizu.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22919 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/s5l8700/crt0.S | 87 |
1 files changed, 78 insertions, 9 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index 12a042ba41..4a89f3da39 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S | |||
@@ -62,12 +62,12 @@ newstart2: | |||
62 | ldr r1, =0x39c00020 | 62 | ldr r1, =0x39c00020 |
63 | str r0, [r1] // mask all external interrupts | 63 | str r0, [r1] // mask all external interrupts |
64 | mvn r0, #0 | 64 | mvn r0, #0 |
65 | ldr r1, =0x39c0001c | ||
66 | str r0, [r1] // clear pending external interrupts | ||
65 | mov r1, #0x39c00000 | 67 | mov r1, #0x39c00000 |
66 | str r0, [r1] // irq priority | 68 | str r0, [r1] // irq priority |
67 | ldr r1, =0x39c00010 | 69 | ldr r1, =0x39c00010 |
68 | str r0, [r1] // clear pending interrupts | 70 | str r0, [r1] // clear pending interrupts |
69 | ldr r1, =0x39c0001c | ||
70 | str r0, [r1] // clear pending external interrupts | ||
71 | 71 | ||
72 | // ldr r1, =0x3cf00000 | 72 | // ldr r1, =0x3cf00000 |
73 | // ldr r0, [r1] | 73 | // ldr r0, [r1] |
@@ -146,12 +146,80 @@ newstart2: | |||
146 | // nop | 146 | // nop |
147 | // nop | 147 | // nop |
148 | 148 | ||
149 | /* The following two sections of code (i.e. Nano2G and Meizus) should | ||
150 | be unified at some point. */ | ||
151 | #ifdef IPOD_NANO2G | ||
152 | mrc 15, 0, r0, c1, c0, 0 | ||
153 | bic r0, r0, #0x1000 | ||
154 | bic r0, r0, #0x5 | ||
155 | mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit | ||
156 | |||
157 | mov r1, #0 | ||
158 | 1: | ||
159 | mov r0, #0 | ||
160 | 2: | ||
161 | orr r2, r1, r0 | ||
162 | mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry | ||
163 | add r0, r0, #0x10 | ||
164 | cmp r0, #0x40 | ||
165 | bne 2b | ||
166 | add r1, r1, #0x4000000 | ||
167 | cmp r1, #0x0 | ||
168 | bne 1b | ||
169 | nop | ||
170 | nop | ||
171 | mov r0, #0 | ||
172 | mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache | ||
173 | mcr 15, 0, r0, c7, c5, 0 // flush icache | ||
174 | mcr 15, 0, r0, c7, c6, 0 // flush dcache | ||
175 | |||
176 | mov r0, #0x3f | ||
177 | mcr 15, 0, r0, c6, c0, 1 // CS0: 4GB at offset 0 - everything | ||
178 | mcr 15, 0, r0, c6, c0, 0 // DS0: 4GB at offset 0 - everything | ||
179 | #ifdef IPOD_NANO2G | ||
180 | mov r0, #0x31 // FIXME: calculate that from MEMORYSIZE | ||
181 | #else | ||
182 | mov r0, #0x2f // FIXME: calculate that from MEMORYSIZE | ||
183 | #endif | ||
184 | mcr 15, 0, r0, c6, c1, 1 // CS1: SRAM/SDRAM mirror | ||
185 | mcr 15, 0, r0, c6, c1, 0 // DS1: SRAM/SDRAM mirror | ||
186 | add r0, r0, #0x08000000 | ||
187 | mcr 15, 0, r0, c6, c2, 1 // CS2: SDRAM | ||
188 | mcr 15, 0, r0, c6, c2, 0 // DS2: SDRAM | ||
189 | ldr r0, =0x22000023 | ||
190 | mcr 15, 0, r0, c6, c3, 1 // CS3: SRAM | ||
191 | mcr 15, 0, r0, c6, c3, 0 // DS3: SRAM | ||
192 | ldr r0, =0x24000027 | ||
193 | mcr 15, 0, r0, c6, c4, 1 // CS4: NOR flash | ||
194 | mcr 15, 0, r0, c6, c4, 0 // DS4: NOR flash | ||
195 | mov r0, #0 | ||
196 | mcr 15, 0, r0, c6, c5, 1 // CS5: unused | ||
197 | mcr 15, 0, r0, c6, c5, 0 // DS5: unused | ||
198 | mcr 15, 0, r0, c6, c6, 1 // CS6: unused | ||
199 | mcr 15, 0, r0, c6, c6, 0 // DS6: unused | ||
200 | mcr 15, 0, r0, c6, c7, 1 // CS7: unused | ||
201 | mcr 15, 0, r0, c6, c7, 0 // DS7: unused | ||
202 | mov r0, #0x1e | ||
203 | mcr 15, 0, r0, c2, c0, 1 // CS1-4: cacheable | ||
204 | mcr 15, 0, r0, c2, c0, 0 // DS1-4: cacheable | ||
205 | mcr 15, 0, r0, c3, c0, 0 // DS1-4: write cacheable | ||
206 | ldr r0, =0x000003ff | ||
207 | mcr 15, 0, r0, c5, c0, 1 // CS0-4: full access | ||
208 | mcr 15, 0, r0, c5, c0, 0 // DS0-4: full access | ||
209 | |||
210 | mrc 15, 0, r0, c1, c0, 0 | ||
211 | orr r0, r0, #0x5 | ||
212 | orr r0, r0, #0x1000 | ||
213 | mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches | ||
214 | |||
215 | #else | ||
216 | |||
149 | ldr r1, =0x3c500000 | 217 | ldr r1, =0x3c500000 |
150 | mov r0, #0 // 0x0 | 218 | mov r0, #0 // 0x0 |
151 | str r0, [r1, #40] // enable clock for all peripherals | 219 | str r0, [r1, #40] // enable clock for all peripherals |
152 | mov r0, #0 // 0x0 | 220 | mov r0, #0 // 0x0 |
153 | str r0, [r1, #44] // do not enter any power saving mode | 221 | str r0, [r1, #44] // do not enter any power saving mode |
154 | 222 | ||
155 | mov r1, #0x1 | 223 | mov r1, #0x1 |
156 | mrc 15, 0, r0, c1, c0, 0 | 224 | mrc 15, 0, r0, c1, c0, 0 |
157 | bic r0, r0, r1 | 225 | bic r0, r0, r1 |
@@ -183,13 +251,13 @@ newstart2: | |||
183 | nop | 251 | nop |
184 | mov r0, #0 | 252 | mov r0, #0 |
185 | mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache | 253 | mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache |
186 | 254 | ||
187 | mov r0, #0 | 255 | mov r0, #0 |
188 | mcr 15, 0, r0, c7, c5, 0 // flush icache | 256 | mcr 15, 0, r0, c7, c5, 0 // flush icache |
189 | 257 | ||
190 | mov r0, #0 | 258 | mov r0, #0 |
191 | mcr 15, 0, r0, c7, c6, 0 // flush dcache | 259 | mcr 15, 0, r0, c7, c6, 0 // flush dcache |
192 | 260 | ||
193 | mov r0, #0x3f | 261 | mov r0, #0x3f |
194 | mcr 15, 0, r0, c6, c0, 1 | 262 | mcr 15, 0, r0, c6, c0, 1 |
195 | mov r0, #0x2f | 263 | mov r0, #0x2f |
@@ -220,22 +288,23 @@ newstart2: | |||
220 | mcr 15, 0, r0, c5, c0, 1 | 288 | mcr 15, 0, r0, c5, c0, 1 |
221 | ldr r0, =0x0000ffff | 289 | ldr r0, =0x0000ffff |
222 | mcr 15, 0, r0, c5, c0, 0 // set up protection and caching | 290 | mcr 15, 0, r0, c5, c0, 0 // set up protection and caching |
223 | 291 | ||
224 | mov r1, #0x4 | 292 | mov r1, #0x4 |
225 | mrc 15, 0, r0, c1, c0, 0 | 293 | mrc 15, 0, r0, c1, c0, 0 |
226 | orr r0, r0, r1 | 294 | orr r0, r0, r1 |
227 | mcr 15, 0, r0, c1, c0, 0 // dcache enable | 295 | mcr 15, 0, r0, c1, c0, 0 // dcache enable |
228 | 296 | ||
229 | mov r1, #0x1000 | 297 | mov r1, #0x1000 |
230 | mrc 15, 0, r0, c1, c0, 0 | 298 | mrc 15, 0, r0, c1, c0, 0 |
231 | orr r0, r0, r1 | 299 | orr r0, r0, r1 |
232 | mcr 15, 0, r0, c1, c0, 0 // icache enable | 300 | mcr 15, 0, r0, c1, c0, 0 // icache enable |
233 | 301 | ||
234 | mov r1, #0x1 | 302 | mov r1, #0x1 |
235 | mrc 15, 0, r0, c1, c0, 0 | 303 | mrc 15, 0, r0, c1, c0, 0 |
236 | orr r0, r0, r1 | 304 | orr r0, r0, r1 |
237 | mcr 15, 0, r0, c1, c0, 0 // enable protection unit | 305 | mcr 15, 0, r0, c1, c0, 0 // enable protection unit |
238 | 306 | #endif | |
307 | |||
239 | #if CONFIG_CPU==S5L8700 || !defined(BOOTLOADER) | 308 | #if CONFIG_CPU==S5L8700 || !defined(BOOTLOADER) |
240 | /* Copy interrupt vectors to iram */ | 309 | /* Copy interrupt vectors to iram */ |
241 | ldr r2, =_intvectstart | 310 | ldr r2, =_intvectstart |