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author | Linus Nielsen Feltzing <linus@haxx.se> | 2002-04-20 23:03:48 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2002-04-20 23:03:48 +0000 |
commit | f3989d3c930a7f233eac5bb3bedc7712c126fa47 (patch) | |
tree | 1d1e5291948eff1dad6bb4b4ec076f362ae6026c /firmware | |
parent | d057c07154b02a067051f8a4711b19e4011a16aa (diff) | |
download | rockbox-f3989d3c930a7f233eac5bb3bedc7712c126fa47.tar.gz rockbox-f3989d3c930a7f233eac5bb3bedc7712c126fa47.zip |
Added serial port bit definitions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@157 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/sh7034.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/firmware/sh7034.h b/firmware/sh7034.h index 5fca9f51fd..6d6fb6d714 100644 --- a/firmware/sh7034.h +++ b/firmware/sh7034.h | |||
@@ -291,4 +291,46 @@ | |||
291 | 291 | ||
292 | #define CASCR (*((volatile unsigned char*)CASCR_ADDR)) | 292 | #define CASCR (*((volatile unsigned char*)CASCR_ADDR)) |
293 | 293 | ||
294 | /*************************************************************************** | ||
295 | * Register bit definitions | ||
296 | **************************************************************************/ | ||
297 | |||
298 | /* | ||
299 | * Serial mode register bits | ||
300 | */ | ||
301 | |||
302 | #define SYNC_MODE 0x80 | ||
303 | #define SEVEN_BIT_DATA 0x40 | ||
304 | #define PARITY_ON 0x20 | ||
305 | #define ODD_PARITY 0x10 | ||
306 | #define STOP_BITS_2 0x08 | ||
307 | #define ENABLE_MULTIP 0x04 | ||
308 | #define PHI_64 0x03 | ||
309 | #define PHI_16 0x02 | ||
310 | #define PHI_4 0x01 | ||
311 | |||
312 | /* | ||
313 | * Serial control register bits | ||
314 | */ | ||
315 | #define SCI_TIE 0x80 /* Transmit interrupt enable */ | ||
316 | #define SCI_RIE 0x40 /* Receive interrupt enable */ | ||
317 | #define SCI_TE 0x20 /* Transmit enable */ | ||
318 | #define SCI_RE 0x10 /* Receive enable */ | ||
319 | #define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ | ||
320 | #define SCI_TEIE 0x04 /* Transmit end interrupt enable */ | ||
321 | #define SCI_CKE1 0x02 /* Clock enable 1 */ | ||
322 | #define SCI_CKE0 0x01 /* Clock enable 0 */ | ||
323 | |||
324 | /* | ||
325 | * Serial status register bits | ||
326 | */ | ||
327 | #define SCI_TDRE 0x80 /* Transmit data register empty */ | ||
328 | #define SCI_RDRF 0x40 /* Receive data register full */ | ||
329 | #define SCI_ORER 0x20 /* Overrun error */ | ||
330 | #define SCI_FER 0x10 /* Framing error */ | ||
331 | #define SCI_PER 0x08 /* Parity error */ | ||
332 | #define SCI_TEND 0x04 /* Transmit end */ | ||
333 | #define SCI_MPB 0x02 /* Multiprocessor bit */ | ||
334 | #define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ | ||
335 | |||
294 | #endif | 336 | #endif |