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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-02-16 22:14:36 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-02-16 22:14:36 +0000 |
commit | e52e3f713fced646a254c150066cd6a8145a2b4d (patch) | |
tree | 5c786d4804550b9e08c60e9a5af6912226e9fc28 /firmware | |
parent | b57fd974de48c7e5f8729353a3869a93cbbbbf3f (diff) | |
download | rockbox-e52e3f713fced646a254c150066cd6a8145a2b4d.tar.gz rockbox-e52e3f713fced646a254c150066cd6a8145a2b4d.zip |
Correct size for the DCRx registers
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5993 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/mcf5249.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/export/mcf5249.h b/firmware/export/mcf5249.h index 339030df28..3fe7c6c7c3 100644 --- a/firmware/export/mcf5249.h +++ b/firmware/export/mcf5249.h | |||
@@ -104,28 +104,28 @@ | |||
104 | 104 | ||
105 | #define SAR0 (*(volatile unsigned long *)(MBAR + 0x300)) | 105 | #define SAR0 (*(volatile unsigned long *)(MBAR + 0x300)) |
106 | #define DAR0 (*(volatile unsigned long *)(MBAR + 0x304)) | 106 | #define DAR0 (*(volatile unsigned long *)(MBAR + 0x304)) |
107 | #define DCR0 (*(volatile unsigned short *)(MBAR + 0x308)) | 107 | #define DCR0 (*(volatile unsigned long *)(MBAR + 0x308)) |
108 | #define BCR0 (*(volatile unsigned long *)(MBAR + 0x30c)) | 108 | #define BCR0 (*(volatile unsigned long *)(MBAR + 0x30c)) |
109 | #define DSR0 (*(volatile unsigned char *)(MBAR + 0x310)) | 109 | #define DSR0 (*(volatile unsigned char *)(MBAR + 0x310)) |
110 | #define DIVR0 (*(volatile unsigned char *)(MBAR + 0x314)) | 110 | #define DIVR0 (*(volatile unsigned char *)(MBAR + 0x314)) |
111 | 111 | ||
112 | #define SAR1 (*(volatile unsigned long *)(MBAR + 0x340)) | 112 | #define SAR1 (*(volatile unsigned long *)(MBAR + 0x340)) |
113 | #define DAR1 (*(volatile unsigned long *)(MBAR + 0x344)) | 113 | #define DAR1 (*(volatile unsigned long *)(MBAR + 0x344)) |
114 | #define DCR1 (*(volatile unsigned short *)(MBAR + 0x348)) | 114 | #define DCR1 (*(volatile unsigned long *)(MBAR + 0x348)) |
115 | #define BCR1 (*(volatile unsigned long *)(MBAR + 0x34c)) | 115 | #define BCR1 (*(volatile unsigned long *)(MBAR + 0x34c)) |
116 | #define DSR1 (*(volatile unsigned char *)(MBAR + 0x350)) | 116 | #define DSR1 (*(volatile unsigned char *)(MBAR + 0x350)) |
117 | #define DIVR1 (*(volatile unsigned char *)(MBAR + 0x354)) | 117 | #define DIVR1 (*(volatile unsigned char *)(MBAR + 0x354)) |
118 | 118 | ||
119 | #define SAR2 (*(volatile unsigned long *)(MBAR + 0x380)) | 119 | #define SAR2 (*(volatile unsigned long *)(MBAR + 0x380)) |
120 | #define DAR2 (*(volatile unsigned long *)(MBAR + 0x384)) | 120 | #define DAR2 (*(volatile unsigned long *)(MBAR + 0x384)) |
121 | #define DCR2 (*(volatile unsigned short *)(MBAR + 0x388)) | 121 | #define DCR2 (*(volatile unsigned long *)(MBAR + 0x388)) |
122 | #define BCR2 (*(volatile unsigned long *)(MBAR + 0x38c)) | 122 | #define BCR2 (*(volatile unsigned long *)(MBAR + 0x38c)) |
123 | #define DSR2 (*(volatile unsigned char *)(MBAR + 0x390)) | 123 | #define DSR2 (*(volatile unsigned char *)(MBAR + 0x390)) |
124 | #define DIVR2 (*(volatile unsigned char *)(MBAR + 0x394)) | 124 | #define DIVR2 (*(volatile unsigned char *)(MBAR + 0x394)) |
125 | 125 | ||
126 | #define SAR3 (*(volatile unsigned long *)(MBAR + 0x3c0)) | 126 | #define SAR3 (*(volatile unsigned long *)(MBAR + 0x3c0)) |
127 | #define DAR3 (*(volatile unsigned long *)(MBAR + 0x3c4)) | 127 | #define DAR3 (*(volatile unsigned long *)(MBAR + 0x3c4)) |
128 | #define DCR3 (*(volatile unsigned short *)(MBAR + 0x3c8)) | 128 | #define DCR3 (*(volatile unsigned long *)(MBAR + 0x3c8)) |
129 | #define BCR3 (*(volatile unsigned long *)(MBAR + 0x3cc)) | 129 | #define BCR3 (*(volatile unsigned long *)(MBAR + 0x3cc)) |
130 | #define DSR3 (*(volatile unsigned char *)(MBAR + 0x3d0)) | 130 | #define DSR3 (*(volatile unsigned char *)(MBAR + 0x3d0)) |
131 | #define DIVR3 (*(volatile unsigned char *)(MBAR + 0x3d4)) | 131 | #define DIVR3 (*(volatile unsigned char *)(MBAR + 0x3d4)) |