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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-08 15:03:05 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-08 15:03:05 +0000 |
commit | e257042a5d36086b7eb42f150d952467f253480b (patch) | |
tree | f3eba4b2583fbcce2314e63be6d972e517cf2b0f /firmware | |
parent | 3b5fdbeb1fbe47fda11148d6c5c7011dbb39194f (diff) | |
download | rockbox-e257042a5d36086b7eb42f150d952467f253480b.tar.gz rockbox-e257042a5d36086b7eb42f150d952467f253480b.zip |
Adjusted refresh timer for H110
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7069 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/system.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/firmware/system.c b/firmware/system.c index 1c384d2fe1..44655bd7d6 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -502,6 +502,14 @@ void system_init(void) | |||
502 | : : : "d0"); | 502 | : : : "d0"); |
503 | } | 503 | } |
504 | 504 | ||
505 | #ifdef IRIVER_H100 | ||
506 | #define MAX_REFRESH_TIMER 56 | ||
507 | #define NORMAL_REFRESH_TIMER 20 | ||
508 | #else | ||
509 | #define MAX_REFRESH_TIMER 28 | ||
510 | #define NORMAL_REFRESH_TIMER 10 | ||
511 | #endif | ||
512 | |||
505 | void set_cpu_frequency (long) __attribute__ ((section (".icode"))); | 513 | void set_cpu_frequency (long) __attribute__ ((section (".icode"))); |
506 | void set_cpu_frequency(long frequency) | 514 | void set_cpu_frequency(long frequency) |
507 | { | 515 | { |
@@ -516,7 +524,7 @@ void set_cpu_frequency(long frequency) | |||
516 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ | 524 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ |
517 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 525 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
518 | This may take up to 10ms! */ | 526 | This may take up to 10ms! */ |
519 | DCR = (DCR & ~0x01ff) | 28; /* Refresh timer */ | 527 | DCR = (DCR & ~0x01ff) | MAX_REFRESH_TIMER; /* Refresh timer */ |
520 | cpu_frequency = CPUFREQ_MAX; | 528 | cpu_frequency = CPUFREQ_MAX; |
521 | tick_start(1000/HZ); | 529 | tick_start(1000/HZ); |
522 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 530 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
@@ -535,7 +543,7 @@ void set_cpu_frequency(long frequency) | |||
535 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 543 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
536 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 544 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
537 | This may take up to 10ms! */ | 545 | This may take up to 10ms! */ |
538 | DCR = (DCR & ~0x01ff) | 10; /* Refresh timer */ | 546 | DCR = (DCR & ~0x01ff) | NORMAL_REFRESH_TIMER; /* Refresh timer */ |
539 | cpu_frequency = CPUFREQ_NORMAL; | 547 | cpu_frequency = CPUFREQ_NORMAL; |
540 | tick_start(1000/HZ); | 548 | tick_start(1000/HZ); |
541 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 549 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |