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author | Bertrik Sikken <bertrik@sikken.nl> | 2009-11-11 21:31:38 +0000 |
---|---|---|
committer | Bertrik Sikken <bertrik@sikken.nl> | 2009-11-11 21:31:38 +0000 |
commit | daff26b1da20309a9f728b0f3a760b128bcd013a (patch) | |
tree | 3d5163b7a3518dbc4089396cc2820e9c0dd9e661 /firmware | |
parent | 12aed44e94218f9eebe92eb4e75a2e6360b1ac14 (diff) | |
download | rockbox-daff26b1da20309a9f728b0f3a760b128bcd013a.tar.gz rockbox-daff26b1da20309a9f728b0f3a760b128bcd013a.zip |
Meizu M3: configure and use SDRAM
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23614 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/config-meizu-m3.h | 3 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/boot.lds | 4 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/crt0.S | 37 |
3 files changed, 33 insertions, 11 deletions
diff --git a/firmware/export/config-meizu-m3.h b/firmware/export/config-meizu-m3.h index 12f2cfdfea..06720695eb 100644 --- a/firmware/export/config-meizu-m3.h +++ b/firmware/export/config-meizu-m3.h | |||
@@ -58,6 +58,9 @@ | |||
58 | 58 | ||
59 | #define CONFIG_NAND NAND_SAMSUNG | 59 | #define CONFIG_NAND NAND_SAMSUNG |
60 | 60 | ||
61 | /* The NAND flash has 2048-byte sectors, and is our only storage */ | ||
62 | #define SECTOR_SIZE 2048 | ||
63 | |||
61 | /* LCD dimensions */ | 64 | /* LCD dimensions */ |
62 | #define LCD_WIDTH 176 | 65 | #define LCD_WIDTH 176 |
63 | #define LCD_HEIGHT 132 | 66 | #define LCD_HEIGHT 132 |
diff --git a/firmware/target/arm/s5l8700/boot.lds b/firmware/target/arm/s5l8700/boot.lds index ba5a4a4cac..9ee7405a9f 100644 --- a/firmware/target/arm/s5l8700/boot.lds +++ b/firmware/target/arm/s5l8700/boot.lds | |||
@@ -104,9 +104,5 @@ SECTIONS | |||
104 | *(COMMON); | 104 | *(COMMON); |
105 | . = ALIGN(0x4); | 105 | . = ALIGN(0x4); |
106 | _end = .; | 106 | _end = .; |
107 | #if defined(IPOD_NANO2G) || defined(MEIZU_M6SP) | ||
108 | } > DRAM | 107 | } > DRAM |
109 | #else /* other targets don't have DRAM set up yet */ | ||
110 | } > IRAM | ||
111 | #endif | ||
112 | } | 108 | } |
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index 5faaf4e834..67bcc5a796 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S | |||
@@ -22,6 +22,28 @@ | |||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "cpu.h" | 23 | #include "cpu.h" |
24 | 24 | ||
25 | /* Meizu M3 SDRAM settings */ | ||
26 | #ifdef MEIZU_M3 | ||
27 | #define SDR_DSS_SEL_B 1 | ||
28 | #define SDR_DSS_SEL_O 1 | ||
29 | #define SDR_DSS_SEL_C 1 | ||
30 | #define SDR_TIMING 0x6A491D | ||
31 | #define SDR_CONFIG 0x900 | ||
32 | #define SDR_MRS 0x37 | ||
33 | #define SDR_EMRS 0x4000 | ||
34 | #endif | ||
35 | |||
36 | /* Meizu M6SP SDRAM settings */ | ||
37 | #ifdef MEIZU_M6SP | ||
38 | #define SDR_DSS_SEL_B 5 | ||
39 | #define SDR_DSS_SEL_O 2 | ||
40 | #define SDR_DSS_SEL_C 2 | ||
41 | #define SDR_TIMING 0x6A4965 | ||
42 | #define SDR_CONFIG 0x700 | ||
43 | #define SDR_MRS 0x33 | ||
44 | #define SDR_EMRS 0x4033 | ||
45 | #endif | ||
46 | |||
25 | .section .intvect,"ax",%progbits | 47 | .section .intvect,"ax",%progbits |
26 | .global start | 48 | .global start |
27 | .global _newstart | 49 | .global _newstart |
@@ -236,14 +258,15 @@ start_loc: | |||
236 | mov r0, #0 // 0x0 | 258 | mov r0, #0 // 0x0 |
237 | str r0, [r1, #44] // do not enter any power saving mode | 259 | str r0, [r1, #44] // do not enter any power saving mode |
238 | 260 | ||
239 | #ifdef MEIZU_M6SP | 261 | #if defined(MEIZU_M6SP) || defined(MEIZU_M3) |
240 | /* setup SDRAM for Meizu M6SP */ | 262 | /* setup SDRAM for Meizu M6SP */ |
241 | ldr r1, =0x38200000 | 263 | ldr r1, =0x38200000 |
242 | // configure SDR drive strength and pad settings | 264 | // configure SDR drive strength and pad settings |
243 | mov r0, #5 | 265 | mov r0, #SDR_DSS_SEL_B |
244 | str r0, [r1, #0x4C] // MIU_DSS_SEL_B | 266 | str r0, [r1, #0x4C] // MIU_DSS_SEL_B |
245 | mov r0, #2 | 267 | mov r0, #SDR_DSS_SEL_O |
246 | str r0, [r1, #0x50] // MIU_DSS_SEL_O | 268 | str r0, [r1, #0x50] // MIU_DSS_SEL_O |
269 | mov r0, #SDR_DSS_SEL_C | ||
247 | str r0, [r1, #0x54] // MIU_DSS_SEL_C | 270 | str r0, [r1, #0x54] // MIU_DSS_SEL_C |
248 | mov r0, #2 | 271 | mov r0, #2 |
249 | str r0, [r1, #0x60] // SSTL2_PAD_ON | 272 | str r0, [r1, #0x60] // SSTL2_PAD_ON |
@@ -254,10 +277,10 @@ start_loc: | |||
254 | orr r0, r0, #1 | 277 | orr r0, r0, #1 |
255 | str r0, [r1, #0x40] // MIUORG | 278 | str r0, [r1, #0x40] // MIUORG |
256 | // set controller configuration | 279 | // set controller configuration |
257 | mov r0, #0x700 | 280 | mov r0, #SDR_CONFIG |
258 | str r0, [r1] // MIUCON | 281 | str r0, [r1] // MIUCON |
259 | // set SDRAM timing | 282 | // set SDRAM timing |
260 | ldr r0, =0x6A4965 | 283 | ldr r0, =SDR_TIMING |
261 | str r0, [r1, #0x10] // MIUSDPARA | 284 | str r0, [r1, #0x10] // MIUSDPARA |
262 | // set refresh rate | 285 | // set refresh rate |
263 | mov r0, #0x1080 | 286 | mov r0, #0x1080 |
@@ -287,11 +310,11 @@ start_loc: | |||
287 | nop | 310 | nop |
288 | nop | 311 | nop |
289 | // set mode register | 312 | // set mode register |
290 | mov r0, #0x33 | 313 | mov r0, #SDR_MRS |
291 | str r0, [r1, #0x0C] // MIUMRS | 314 | str r0, [r1, #0x0C] // MIUMRS |
292 | ldr r0, =0x103 | 315 | ldr r0, =0x103 |
293 | str r0, [r1, #0x04] // MIUCOM = mode register set | 316 | str r0, [r1, #0x04] // MIUCOM = mode register set |
294 | ldr r0, =0x4033 | 317 | ldr r0, =SDR_EMRS |
295 | str r0, [r1, #0x0C] // MIUMRS | 318 | str r0, [r1, #0x0C] // MIUMRS |
296 | ldr r0, =0x103 | 319 | ldr r0, =0x103 |
297 | str r0, [r1, #0x04] // MIUCOM = mode register set | 320 | str r0, [r1, #0x04] // MIUCOM = mode register set |