diff options
author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-17 00:28:19 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-17 00:29:26 +0200 |
commit | dafc359fad4c6b8d4964bafcf6a1f61547c6e6d8 (patch) | |
tree | c7ea099e1806de78815c7ddc42c47ad26d92195e /firmware | |
parent | 8d7cc320b720c088a8ccb7e33ed85a7de0b89aeb (diff) | |
download | rockbox-dafc359fad4c6b8d4964bafcf6a1f61547c6e6d8.tar.gz rockbox-dafc359fad4c6b8d4964bafcf6a1f61547c6e6d8.zip |
imx233: fix system for stmp3600 and stmp3700
Change-Id: I2b425b56358ed21269beae27a4afb490939b7f9d
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index dcf3b82408..9a8ff61af0 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c | |||
@@ -30,7 +30,9 @@ | |||
30 | #include "dma-imx233.h" | 30 | #include "dma-imx233.h" |
31 | #include "ssp-imx233.h" | 31 | #include "ssp-imx233.h" |
32 | #include "i2c-imx233.h" | 32 | #include "i2c-imx233.h" |
33 | #if IMX233_SUBTARGET >= 3700 | ||
33 | #include "dcp-imx233.h" | 34 | #include "dcp-imx233.h" |
35 | #endif | ||
34 | #include "pwm-imx233.h" | 36 | #include "pwm-imx233.h" |
35 | #include "icoll-imx233.h" | 37 | #include "icoll-imx233.h" |
36 | #include "lradc-imx233.h" | 38 | #include "lradc-imx233.h" |
@@ -44,7 +46,11 @@ | |||
44 | 46 | ||
45 | void imx233_chip_reset(void) | 47 | void imx233_chip_reset(void) |
46 | { | 48 | { |
49 | #if IMX233_SUBTARGET >= 3700 | ||
47 | HW_CLKCTRL_RESET = BM_CLKCTRL_RESET_CHIP; | 50 | HW_CLKCTRL_RESET = BM_CLKCTRL_RESET_CHIP; |
51 | #else | ||
52 | HW_POWER_RESET = BF_OR2(POWER_RESET, UNLOCK_V(KEY), RST_DIG(1)); | ||
53 | #endif | ||
48 | } | 54 | } |
49 | 55 | ||
50 | void system_reboot(void) | 56 | void system_reboot(void) |
@@ -109,7 +115,9 @@ void system_init(void) | |||
109 | * Make sure IO clock is running at expected speed */ | 115 | * Make sure IO clock is running at expected speed */ |
110 | imx233_clkctrl_init(); | 116 | imx233_clkctrl_init(); |
111 | imx233_clkctrl_enable(CLK_PLL, true); | 117 | imx233_clkctrl_enable(CLK_PLL, true); |
118 | #if IMX233_SUBTARGET >= 3700 | ||
112 | imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll | 119 | imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll |
120 | #endif | ||
113 | 121 | ||
114 | imx233_rtc_init(); | 122 | imx233_rtc_init(); |
115 | imx233_icoll_init(); | 123 | imx233_icoll_init(); |
@@ -117,7 +125,9 @@ void system_init(void) | |||
117 | imx233_timrot_init(); | 125 | imx233_timrot_init(); |
118 | imx233_dma_init(); | 126 | imx233_dma_init(); |
119 | imx233_ssp_init(); | 127 | imx233_ssp_init(); |
128 | #if IMX233_SUBTARGET >= 3700 | ||
120 | imx233_dcp_init(); | 129 | imx233_dcp_init(); |
130 | #endif | ||
121 | imx233_pwm_init(); | 131 | imx233_pwm_init(); |
122 | imx233_lradc_init(); | 132 | imx233_lradc_init(); |
123 | imx233_power_init(); | 133 | imx233_power_init(); |
@@ -166,8 +176,13 @@ void udelay(unsigned us) | |||
166 | 176 | ||
167 | void imx233_digctl_set_arm_cache_timings(unsigned timings) | 177 | void imx233_digctl_set_arm_cache_timings(unsigned timings) |
168 | { | 178 | { |
179 | #if IMX233_SUBTARGET >= 3780 | ||
169 | HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings), | 180 | HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings), |
170 | DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings)); | 181 | DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings)); |
182 | #else | ||
183 | HW_DIGCTL_ARMCACHE = BF_OR3(DIGCTL_ARMCACHE, ITAG_SS(timings), | ||
184 | DTAG_SS(timings), CACHE_SS(timings)); | ||
185 | #endif | ||
171 | } | 186 | } |
172 | 187 | ||
173 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 188 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |