summaryrefslogtreecommitdiff
path: root/firmware
diff options
context:
space:
mode:
authorSolomon Peachy <pizza@shaftnet.org>2020-10-03 15:57:38 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-10-03 15:57:38 -0400
commitd5167b1221bb89c0241fa9f435a676d5a475e585 (patch)
tree3199d865c1ea2e0fddab0fbf519905f07410cb38 /firmware
parent2b358ffa7f65d3e67ae58a2f076477dae5bf67d5 (diff)
downloadrockbox-d5167b1221bb89c0241fa9f435a676d5a475e585.tar.gz
rockbox-d5167b1221bb89c0241fa9f435a676d5a475e585.zip
coldfire: Allow building when 88KHz audio is disabled
Change-Id: Ieeacf591ad4233428dca99c347043e61abae1d1f
Diffstat (limited to 'firmware')
-rw-r--r--firmware/drivers/audio/uda1380.c6
-rw-r--r--firmware/target/coldfire/pcm-coldfire.c2
2 files changed, 5 insertions, 3 deletions
diff --git a/firmware/drivers/audio/uda1380.c b/firmware/drivers/audio/uda1380.c
index 156eb822b6..079175d966 100644
--- a/firmware/drivers/audio/uda1380.c
+++ b/firmware/drivers/audio/uda1380.c
@@ -227,11 +227,11 @@ void audiohw_set_frequency(int fsel)
227 MIX_CTL_SEL_NS, 227 MIX_CTL_SEL_NS,
228 WSPLL_25_50 | SYSCLK_256FS 228 WSPLL_25_50 | SYSCLK_256FS
229 }, 229 },
230 [HW_FREQ_88] = 230 HW_HAVE_88_([HW_FREQ_88] =
231 { 231 {
232 MIX_CTL_SEL_NS, 232 MIX_CTL_SEL_NS,
233 WSPLL_50_100 | SYSCLK_256FS 233 WSPLL_50_100 | SYSCLK_256FS
234 }, 234 },)
235 }; 235 };
236 236
237 const unsigned short *ent; 237 const unsigned short *ent;
@@ -243,6 +243,7 @@ void audiohw_set_frequency(int fsel)
243 243
244#ifdef USE_WSPLL 244#ifdef USE_WSPLL
245 /* Enable WSPLL if needed (for Iriver H100 and H300 series) */ 245 /* Enable WSPLL if needed (for Iriver H100 and H300 series) */
246HW_HAVE_88_(
246 if (fsel == HW_FREQ_88) 247 if (fsel == HW_FREQ_88)
247 { 248 {
248 /* Only at this case we need use WSPLL on DAC part for Iriver H100 and H300 series, because Coldfire work 249 /* Only at this case we need use WSPLL on DAC part for Iriver H100 and H300 series, because Coldfire work
@@ -251,6 +252,7 @@ void audiohw_set_frequency(int fsel)
251 if (!wspll_enable) wspll_on(true); 252 if (!wspll_enable) wspll_on(true);
252 } 253 }
253 else 254 else
255)
254 { 256 {
255 /* At this case WSPLL clock and SYSCLK has same value and we don't use WSPLL to avoid WSPLL errors */ 257 /* At this case WSPLL clock and SYSCLK has same value and we don't use WSPLL to avoid WSPLL errors */
256 if (wspll_enable) wspll_on(false); 258 if (wspll_enable) wspll_on(false);
diff --git a/firmware/target/coldfire/pcm-coldfire.c b/firmware/target/coldfire/pcm-coldfire.c
index 2e2312f7ae..5a5d2d2350 100644
--- a/firmware/target/coldfire/pcm-coldfire.c
+++ b/firmware/target/coldfire/pcm-coldfire.c
@@ -77,7 +77,7 @@
77#if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380) 77#if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
78static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = 78static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
79{ 79{
80 [HW_FREQ_88] = { 0x0c, 0x01 }, 80HW_HAVE_88_([HW_FREQ_88] = { 0x0c, 0x01 },)
81 [HW_FREQ_44] = { 0x06, 0x01 }, 81 [HW_FREQ_44] = { 0x06, 0x01 },
82 [HW_FREQ_22] = { 0x04, 0x02 }, 82 [HW_FREQ_22] = { 0x04, 0x02 },
83 [HW_FREQ_11] = { 0x02, 0x02 }, 83 [HW_FREQ_11] = { 0x02, 0x02 },