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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-13 15:50:03 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-13 15:50:03 +0000 |
commit | d0af7f9601f9f1c9fe59829f1c8c402c04200b2f (patch) | |
tree | e28a40bd2e938bbf3965a4a2bf91905925137358 /firmware | |
parent | f9c7dc0859b83eacc940802a1b04bc633df5b838 (diff) | |
download | rockbox-d0af7f9601f9f1c9fe59829f1c8c402c04200b2f.tar.gz rockbox-d0af7f9601f9f1c9fe59829f1c8c402c04200b2f.zip |
s3c2440/system-target.h : CRLF -> LF
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25632 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 134 |
1 files changed, 67 insertions, 67 deletions
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index 7bb49c01c4..0721feeee4 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h | |||
@@ -1,80 +1,80 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2007 by Greg White | 10 | * Copyright (C) 2007 by Greg White |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #ifndef SYSTEM_TARGET_H | 21 | #ifndef SYSTEM_TARGET_H |
22 | #define SYSTEM_TARGET_H | 22 | #define SYSTEM_TARGET_H |
23 | 23 | ||
24 | #include "system-arm.h" | 24 | #include "system-arm.h" |
25 | #include "mmu-arm.h" | 25 | #include "mmu-arm.h" |
26 | 26 | ||
27 | /* NB: These values must match the register settings in s3c2440/crt0.S */ | 27 | /* NB: These values must match the register settings in s3c2440/crt0.S */ |
28 | 28 | ||
29 | #ifdef GIGABEAT_F | 29 | #ifdef GIGABEAT_F |
30 | #define CPUFREQ_DEFAULT 98784000 | 30 | #define CPUFREQ_DEFAULT 98784000 |
31 | #define CPUFREQ_NORMAL 98784000 | 31 | #define CPUFREQ_NORMAL 98784000 |
32 | #define CPUFREQ_MAX 296352000 | 32 | #define CPUFREQ_MAX 296352000 |
33 | 33 | ||
34 | /* Uses 1:3:6 */ | 34 | /* Uses 1:3:6 */ |
35 | #define FCLK CPUFREQ_MAX | 35 | #define FCLK CPUFREQ_MAX |
36 | #define HCLK (FCLK/3) /* = 98,784,000 */ | 36 | #define HCLK (FCLK/3) /* = 98,784,000 */ |
37 | #define PCLK (HCLK/2) /* = 49,392,000 */ | 37 | #define PCLK (HCLK/2) /* = 49,392,000 */ |
38 | 38 | ||
39 | #ifdef BOOTLOADER | 39 | #ifdef BOOTLOADER |
40 | /* All addresses within rockbox are in IRAM in the bootloader so | 40 | /* All addresses within rockbox are in IRAM in the bootloader so |
41 | are therefore uncached */ | 41 | are therefore uncached */ |
42 | #define UNCACHED_ADDR(a) (a) | 42 | #define UNCACHED_ADDR(a) (a) |
43 | #else /* !BOOTLOADER */ | 43 | #else /* !BOOTLOADER */ |
44 | #define UNCACHED_BASE_ADDR 0x30000000 | 44 | #define UNCACHED_BASE_ADDR 0x30000000 |
45 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) | 45 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) |
46 | #endif /* BOOTLOADER */ | 46 | #endif /* BOOTLOADER */ |
47 | 47 | ||
48 | #elif defined(MINI2440) | 48 | #elif defined(MINI2440) |
49 | 49 | ||
50 | /* Uses 1:4:8 */ | 50 | /* Uses 1:4:8 */ |
51 | #define FCLK 406000000 | 51 | #define FCLK 406000000 |
52 | #define HCLK (FCLK/4) /* = 101,250,000 */ | 52 | #define HCLK (FCLK/4) /* = 101,250,000 */ |
53 | #define PCLK (HCLK/2) /* = 50,625,000 */ | 53 | #define PCLK (HCLK/2) /* = 50,625,000 */ |
54 | 54 | ||
55 | #define CPUFREQ_DEFAULT FCLK /* 406 MHz */ | 55 | #define CPUFREQ_DEFAULT FCLK /* 406 MHz */ |
56 | #define CPUFREQ_NORMAL (FCLK/4)/* 101.25 MHz */ | 56 | #define CPUFREQ_NORMAL (FCLK/4)/* 101.25 MHz */ |
57 | #define CPUFREQ_MAX FCLK /* 406 MHz */ | 57 | #define CPUFREQ_MAX FCLK /* 406 MHz */ |
58 | 58 | ||
59 | #define UNCACHED_BASE_ADDR 0x30000000 | 59 | #define UNCACHED_BASE_ADDR 0x30000000 |
60 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) | 60 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) |
61 | 61 | ||
62 | #else | 62 | #else |
63 | #error Unknown target | 63 | #error Unknown target |
64 | #endif | 64 | #endif |
65 | 65 | ||
66 | 66 | ||
67 | void system_prepare_fw_start(void); | 67 | void system_prepare_fw_start(void); |
68 | void tick_stop(void); | 68 | void tick_stop(void); |
69 | 69 | ||
70 | /* Functions to set and clear register bits atomically */ | 70 | /* Functions to set and clear register bits atomically */ |
71 | 71 | ||
72 | /* Set and clear register bits */ | 72 | /* Set and clear register bits */ |
73 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, | 73 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, |
74 | unsigned long mask); | 74 | unsigned long mask); |
75 | /* Set register bits */ | 75 | /* Set register bits */ |
76 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits); | 76 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits); |
77 | /* Clear register bits */ | 77 | /* Clear register bits */ |
78 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); | 78 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); |
79 | 79 | ||
80 | #endif /* SYSTEM_TARGET_H */ | 80 | #endif /* SYSTEM_TARGET_H */ |